Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1603066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256091

1

T1

333

T2

26

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	629714	1			T1	883		T2	51		T3	49
values[0x0]	598694	1			T1	866		T2	53		T3	51
values[0x1]	630749	1			T1	872		T2	44		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1239892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

619265

1

T1

853

T2

52

T3

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29686	1			T1	11		T3	2		T9	245
valid_sources[0x01]	28946	1			T1	3		T9	186		T8	13
valid_sources[0x02]	28881	1			T2	6		T7	4		T9	188
valid_sources[0x03]	28762	1			T1	14		T2	1		T3	3
valid_sources[0x04]	28419	1			T1	57		T3	1		T7	3
valid_sources[0x05]	28446	1			T1	14		T2	3		T3	5
valid_sources[0x06]	29347	1			T3	2		T9	177		T8	31
valid_sources[0x07]	28654	1			T1	88		T3	1		T9	274
valid_sources[0x08]	27676	1			T1	53		T9	125		T8	18
valid_sources[0x09]	30332	1			T1	8		T3	2		T9	239
valid_sources[0x0a]	29639	1			T9	142		T8	26		T12	25
valid_sources[0x0b]	28994	1			T1	57		T2	1		T7	1
valid_sources[0x0c]	29074	1			T1	28		T2	3		T3	1
valid_sources[0x0d]	28658	1			T2	5		T3	1		T9	189
valid_sources[0x0e]	29646	1			T1	87		T3	4		T7	2
valid_sources[0x0f]	29955	1			T1	56		T3	4		T7	3
valid_sources[0x10]	29308	1			T1	233		T3	3		T7	6
valid_sources[0x11]	29261	1			T1	78		T2	2		T3	2
valid_sources[0x12]	29128	1			T7	3		T9	95		T8	14
valid_sources[0x13]	28173	1			T2	12		T3	6		T9	122
valid_sources[0x14]	28383	1			T1	29		T2	1		T3	1
valid_sources[0x15]	29085	1			T1	18		T3	9		T9	112
valid_sources[0x16]	28232	1			T1	11		T3	1		T7	4
valid_sources[0x17]	28946	1			T1	10		T3	5		T7	2
valid_sources[0x18]	28817	1			T1	23		T3	4		T7	1
valid_sources[0x19]	29026	1			T1	37		T2	4		T3	5
valid_sources[0x1a]	28547	1			T1	27		T7	3		T9	118
valid_sources[0x1b]	28496	1			T2	2		T7	3		T9	226
valid_sources[0x1c]	28241	1			T1	16		T3	2		T7	6
valid_sources[0x1d]	29127	1			T1	196		T2	3		T3	9
valid_sources[0x1e]	27586	1			T2	4		T7	1		T9	133
valid_sources[0x1f]	28220	1			T1	37		T2	9		T3	3
valid_sources[0x20]	29417	1			T9	193		T8	10		T10	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26677

1

T1

29

T2

2

T3

1

values[0x0]

all_enables

biggest_size

202507

1

T1

273

T2

22

T3

23

values[0x1]

all_enables

biggest_size

26907

1

T1

31

T2

2

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1613749	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261993

1

T1

391

T2

20

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	642362	1			T1	864		T2	37		T3	50
values[0x0]	592259	1			T1	876		T2	37		T3	59
values[0x1]	641121	1			T1	900		T2	32		T3	64

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1239216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

636526

1

T1

946

T2

32

T3

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29282	1			T1	35		T2	1		T3	5
valid_sources[0x01]	29261	1			T1	37		T2	2		T3	3
valid_sources[0x02]	29291	1			T1	30		T2	2		T3	2
valid_sources[0x03]	28973	1			T1	28		T2	2		T3	4
valid_sources[0x04]	29600	1			T1	32		T2	5		T3	2
valid_sources[0x05]	29599	1			T1	44		T3	4		T7	3
valid_sources[0x06]	28839	1			T1	46		T3	4		T9	198
valid_sources[0x07]	29547	1			T1	47		T2	1		T3	2
valid_sources[0x08]	29167	1			T1	38		T3	6		T7	5
valid_sources[0x09]	29922	1			T1	45		T2	2		T3	1
valid_sources[0x0a]	29270	1			T1	36		T2	1		T3	3
valid_sources[0x0b]	29584	1			T1	37		T2	2		T7	1
valid_sources[0x0c]	29481	1			T1	46		T3	7		T7	2
valid_sources[0x0d]	28673	1			T1	37		T2	1		T3	4
valid_sources[0x0e]	28722	1			T1	47		T2	2		T3	4
valid_sources[0x0f]	29348	1			T1	40		T3	2		T7	5
valid_sources[0x10]	29257	1			T1	53		T2	3		T3	3
valid_sources[0x11]	29569	1			T1	45		T2	3		T3	1
valid_sources[0x12]	29275	1			T1	30		T3	1		T7	2
valid_sources[0x13]	29432	1			T1	50		T2	6		T3	2
valid_sources[0x14]	29374	1			T1	39		T3	2		T7	2
valid_sources[0x15]	29229	1			T1	41		T2	3		T3	5
valid_sources[0x16]	29091	1			T1	33		T2	2		T7	1
valid_sources[0x17]	28882	1			T1	26		T2	2		T3	3
valid_sources[0x18]	28849	1			T1	47		T2	5		T3	2
valid_sources[0x19]	28933	1			T1	45		T2	3		T3	2
valid_sources[0x1a]	29560	1			T1	34		T2	1		T3	6
valid_sources[0x1b]	29575	1			T1	42		T2	1		T3	2
valid_sources[0x1c]	28929	1			T1	51		T2	3		T3	2
valid_sources[0x1d]	29033	1			T1	42		T3	3		T7	1
valid_sources[0x1e]	28723	1			T1	37		T7	3		T9	185
valid_sources[0x1f]	29010	1			T1	50		T2	2		T3	2
valid_sources[0x20]	29705	1			T1	35		T2	3		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27362

1

T1

34

T2

3

T3

5

values[0x0]

all_enables

biggest_size

207262

1

T1

318

T2

14

T3

13

values[0x1]

all_enables

biggest_size

27369

1

T1

39

T2

3

T3

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1615787	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

257005

1

T1

329

T2

16

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	634631	1			T1	837		T2	25		T3	49
values[0x0]	601844	1			T1	745		T2	34		T3	42
values[0x1]	636317	1			T1	798		T2	29		T3	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1248466	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

624326

1

T1

800

T2

28

T3

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29019	1			T1	36		T7	3		T9	220
valid_sources[0x01]	29322	1			T1	38		T7	1		T9	203
valid_sources[0x02]	29841	1			T1	35		T2	2		T7	4
valid_sources[0x03]	28983	1			T1	39		T2	1		T9	155
valid_sources[0x04]	29910	1			T1	18		T2	3		T7	4
valid_sources[0x05]	29378	1			T1	38		T7	3		T9	185
valid_sources[0x06]	28278	1			T1	42		T2	5		T7	2
valid_sources[0x07]	29514	1			T1	32		T2	1		T3	4
valid_sources[0x08]	29404	1			T1	33		T7	2		T9	154
valid_sources[0x09]	29756	1			T1	30		T2	1		T7	2
valid_sources[0x0a]	29014	1			T1	45		T2	4		T7	3
valid_sources[0x0b]	29584	1			T1	31		T2	1		T7	4
valid_sources[0x0c]	30305	1			T1	37		T2	3		T7	4
valid_sources[0x0d]	29908	1			T1	36		T3	19		T7	3
valid_sources[0x0e]	28794	1			T1	35		T7	1		T9	261
valid_sources[0x0f]	28358	1			T1	37		T7	4		T9	211
valid_sources[0x10]	29081	1			T1	36		T7	3		T9	131
valid_sources[0x11]	29331	1			T1	29		T7	3		T9	166
valid_sources[0x12]	29331	1			T1	40		T2	3		T7	7
valid_sources[0x13]	29686	1			T1	49		T2	1		T3	27
valid_sources[0x14]	28590	1			T1	43		T7	4		T9	168
valid_sources[0x15]	28817	1			T1	29		T7	2		T9	140
valid_sources[0x16]	29100	1			T1	30		T2	1		T7	2
valid_sources[0x17]	29521	1			T1	34		T7	3		T9	203
valid_sources[0x18]	29899	1			T1	44		T7	5		T9	151
valid_sources[0x19]	29627	1			T1	38		T2	1		T9	195
valid_sources[0x1a]	29283	1			T1	35		T7	1		T9	267
valid_sources[0x1b]	28789	1			T1	42		T7	1		T9	163
valid_sources[0x1c]	28792	1			T1	42		T2	1		T9	170
valid_sources[0x1d]	29785	1			T1	36		T2	1		T7	1
valid_sources[0x1e]	28575	1			T1	40		T2	2		T7	5
valid_sources[0x1f]	29554	1			T1	28		T2	1		T7	3
valid_sources[0x20]	29587	1			T1	45		T2	2		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26910

1

T1

35

T2

1

T3

2

values[0x0]

all_enables

biggest_size

203237

1

T1

254

T2

13

T3

14

values[0x1]

all_enables

biggest_size

26858

1

T1

40

T2

2

T3

1