Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7964660	0	0
GntImpliesValid_A	2147483647	7964660	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7964660	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	462298655	0	0
ReadyAndValidImplyGrant_A	2147483647	7964660	0	0
ReqAndReadyImplyGrant_A	2147483647	7964660	0	0
ReqImpliesValid_A	2147483647	34895746	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	38494	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7964660	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	261024	259848	0	0
T2	4381440	4379904	0	0
T3	42552	41664	0	0
T7	11253192	11252952	0	0
T8	564984	563592	0	0
T9	1586112	1581624	0	0
T10	455064	453288	0	0
T11	8682696	8680920	0	0
T12	2672928	2672856	0	0
T13	142464	141456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7964660	0	0
T1	261024	3942	0	0
T2	4381440	341	0	0
T3	42552	443	0	0
T7	11253192	491	0	0
T8	564984	1630	0	0
T9	1586112	30381	0	0
T10	455064	5891	0	0
T11	8682696	481	0	0
T12	2672928	3698	0	0
T13	142464	2817	0	0
T14	0	230	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7964660	0	0
T1	261024	3942	0	0
T2	4381440	341	0	0
T3	42552	443	0	0
T7	11253192	491	0	0
T8	564984	1630	0	0
T9	1586112	30381	0	0
T10	455064	5891	0	0
T11	8682696	481	0	0
T12	2672928	3698	0	0
T13	142464	2817	0	0
T14	0	230	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	261024	259848	0	0
T2	4381440	4379904	0	0
T3	42552	41664	0	0
T7	11253192	11252952	0	0
T8	564984	563592	0	0
T9	1586112	1581624	0	0
T10	455064	453288	0	0
T11	8682696	8680920	0	0
T12	2672928	2672856	0	0
T13	142464	141456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	261024	259848	0	0
T2	4381440	4379904	0	0
T3	42552	41664	0	0
T7	11253192	11252952	0	0
T8	564984	563592	0	0
T9	1586112	1581624	0	0
T10	455064	453288	0	0
T11	8682696	8680920	0	0
T12	2672928	2672856	0	0
T13	142464	141456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7964660	0	0
T1	261024	3942	0	0
T2	4381440	341	0	0
T3	42552	443	0	0
T7	11253192	491	0	0
T8	564984	1630	0	0
T9	1586112	30381	0	0
T10	455064	5891	0	0
T11	8682696	481	0	0
T12	2672928	3698	0	0
T13	142464	2817	0	0
T14	0	230	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	462298655	0	0
T1	261024	6101	0	0
T2	4381440	153467	0	0
T3	42552	422	0	0
T7	11253192	590470	0	0
T8	564984	33801	0	0
T9	1586112	48415	0	0
T10	455064	10549	0	0
T11	8682696	303818	0	0
T12	2672928	944501	0	0
T13	142464	449	0	0
T14	0	15117	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7964660	0	0
T1	261024	3942	0	0
T2	4381440	341	0	0
T3	42552	443	0	0
T7	11253192	491	0	0
T8	564984	1630	0	0
T9	1586112	30381	0	0
T10	455064	5891	0	0
T11	8682696	481	0	0
T12	2672928	3698	0	0
T13	142464	2817	0	0
T14	0	230	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7964660	0	0
T1	261024	3942	0	0
T2	4381440	341	0	0
T3	42552	443	0	0
T7	11253192	491	0	0
T8	564984	1630	0	0
T9	1586112	30381	0	0
T10	455064	5891	0	0
T11	8682696	481	0	0
T12	2672928	3698	0	0
T13	142464	2817	0	0
T14	0	230	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34895746	0	0
T1	261024	4476	0	0
T2	4381440	528	0	0
T3	42552	502	0	0
T7	11253192	32547	0	0
T8	564984	3601	0	0
T9	1586112	34784	0	0
T10	455064	6272	0	0
T11	8682696	872	0	0
T12	2672928	6284	0	0
T13	142464	6580	0	0
T14	0	4074	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38494	0	21600
T1	21752	14	0	2
T2	365120	0	0	2
T3	3546	0	0	2
T7	937766	0	0	2
T8	47082	0	0	2
T9	132176	87	0	2
T10	37922	18	0	2
T11	723558	0	0	2
T12	222744	0	0	2
T13	11872	0	0	2
T15	0	1	0	0
T16	0	6	0	0
T17	0	35	0	0
T18	0	37	0	0
T19	0	18	0	0
T20	0	28	0	0
T21	0	22	0	0
T22	0	1488	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	261024	259848	0	0
T2	4381440	4379904	0	0
T3	42552	41664	0	0
T7	11253192	11252952	0	0
T8	564984	563592	0	0
T9	1586112	1581624	0	0
T10	455064	453288	0	0
T11	8682696	8680920	0	0
T12	2672928	2672856	0	0
T13	142464	141456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7964660	0	0
T1	261024	3942	0	0
T2	4381440	341	0	0
T3	42552	443	0	0
T7	11253192	491	0	0
T8	564984	1630	0	0
T9	1586112	30381	0	0
T10	455064	5891	0	0
T11	8682696	481	0	0
T12	2672928	3698	0	0
T13	142464	2817	0	0
T14	0	230	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	877560	0	0
GntImpliesValid_A	421510055	877560	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	877560	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	12533498	0	0
ReadyAndValidImplyGrant_A	421510055	877560	0	0
ReqAndReadyImplyGrant_A	421510055	877560	0	0
ReqImpliesValid_A	421510055	2455459	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	877560	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877560	0	0
T1	10876	420	0	0
T2	182560	28	0	0
T3	1773	48	0	0
T7	468883	65	0	0
T8	23541	185	0	0
T9	66088	3254	0	0
T10	18961	679	0	0
T11	361779	56	0	0
T12	111372	436	0	0
T13	5936	248	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877560	0	0
T1	10876	420	0	0
T2	182560	28	0	0
T3	1773	48	0	0
T7	468883	65	0	0
T8	23541	185	0	0
T9	66088	3254	0	0
T10	18961	679	0	0
T11	361779	56	0	0
T12	111372	436	0	0
T13	5936	248	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877560	0	0
T1	10876	420	0	0
T2	182560	28	0	0
T3	1773	48	0	0
T7	468883	65	0	0
T8	23541	185	0	0
T9	66088	3254	0	0
T10	18961	679	0	0
T11	361779	56	0	0
T12	111372	436	0	0
T13	5936	248	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	12533498	0	0
T1	10876	355	0	0
T2	182560	142	0	0
T3	1773	37	0	0
T7	468883	19317	0	0
T8	23541	1346	0	0
T9	66088	2723	0	0
T10	18961	655	0	0
T11	361779	220	0	0
T12	111372	1776	0	0
T13	5936	175	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877560	0	0
T1	10876	420	0	0
T2	182560	28	0	0
T3	1773	48	0	0
T7	468883	65	0	0
T8	23541	185	0	0
T9	66088	3254	0	0
T10	18961	679	0	0
T11	361779	56	0	0
T12	111372	436	0	0
T13	5936	248	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877560	0	0
T1	10876	420	0	0
T2	182560	28	0	0
T3	1773	48	0	0
T7	468883	65	0	0
T8	23541	185	0	0
T9	66088	3254	0	0
T10	18961	679	0	0
T11	361779	56	0	0
T12	111372	436	0	0
T13	5936	248	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	2455459	0	0
T1	10876	486	0	0
T2	182560	28	0	0
T3	1773	60	0	0
T7	468883	3868	0	0
T8	23541	284	0	0
T9	66088	3786	0	0
T10	18961	704	0	0
T11	361779	74	0	0
T12	111372	647	0	0
T13	5936	322	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877560	0	0
T1	10876	420	0	0
T2	182560	28	0	0
T3	1773	48	0	0
T7	468883	65	0	0
T8	23541	185	0	0
T9	66088	3254	0	0
T10	18961	679	0	0
T11	361779	56	0	0
T12	111372	436	0	0
T13	5936	248	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	887637	0	0
GntImpliesValid_A	421510055	887637	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	887637	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	12610644	0	0
ReadyAndValidImplyGrant_A	421510055	887637	0	0
ReqAndReadyImplyGrant_A	421510055	887637	0	0
ReqImpliesValid_A	421510055	2520355	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	887637	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	887637	0	0
T1	10876	436	0	0
T2	182560	37	0	0
T3	1773	55	0	0
T7	468883	53	0	0
T8	23541	160	0	0
T9	66088	3259	0	0
T10	18961	660	0	0
T11	361779	56	0	0
T12	111372	418	0	0
T13	5936	234	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	887637	0	0
T1	10876	436	0	0
T2	182560	37	0	0
T3	1773	55	0	0
T7	468883	53	0	0
T8	23541	160	0	0
T9	66088	3259	0	0
T10	18961	660	0	0
T11	361779	56	0	0
T12	111372	418	0	0
T13	5936	234	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	887637	0	0
T1	10876	436	0	0
T2	182560	37	0	0
T3	1773	55	0	0
T7	468883	53	0	0
T8	23541	160	0	0
T9	66088	3259	0	0
T10	18961	660	0	0
T11	361779	56	0	0
T12	111372	418	0	0
T13	5936	234	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	12610644	0	0
T1	10876	375	0	0
T2	182560	169	0	0
T3	1773	46	0	0
T7	468883	16329	0	0
T8	23541	1242	0	0
T9	66088	2669	0	0
T10	18961	642	0	0
T11	361779	226	0	0
T12	111372	1859	0	0
T13	5936	176	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	887637	0	0
T1	10876	436	0	0
T2	182560	37	0	0
T3	1773	55	0	0
T7	468883	53	0	0
T8	23541	160	0	0
T9	66088	3259	0	0
T10	18961	660	0	0
T11	361779	56	0	0
T12	111372	418	0	0
T13	5936	234	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	887637	0	0
T1	10876	436	0	0
T2	182560	37	0	0
T3	1773	55	0	0
T7	468883	53	0	0
T8	23541	160	0	0
T9	66088	3259	0	0
T10	18961	660	0	0
T11	361779	56	0	0
T12	111372	418	0	0
T13	5936	234	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	2520355	0	0
T1	10876	498	0	0
T2	182560	45	0	0
T3	1773	65	0	0
T7	468883	1612	0	0
T8	23541	220	0	0
T9	66088	3851	0	0
T10	18961	679	0	0
T11	361779	72	0	0
T12	111372	534	0	0
T13	5936	293	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	887637	0	0
T1	10876	436	0	0
T2	182560	37	0	0
T3	1773	55	0	0
T7	468883	53	0	0
T8	23541	160	0	0
T9	66088	3259	0	0
T10	18961	660	0	0
T11	361779	56	0	0
T12	111372	418	0	0
T13	5936	234	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	218271	0	0
GntImpliesValid_A	421510055	218271	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	218271	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3204989	0	0
ReadyAndValidImplyGrant_A	421510055	218271	0	0
ReqAndReadyImplyGrant_A	421510055	218271	0	0
ReqImpliesValid_A	421510055	580845	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	218271	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218271	0	0
T1	10876	125	0	0
T2	182560	4	0	0
T3	1773	13	0	0
T7	468883	8	0	0
T8	23541	52	0	0
T9	66088	853	0	0
T10	18961	140	0	0
T11	361779	11	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218271	0	0
T1	10876	125	0	0
T2	182560	4	0	0
T3	1773	13	0	0
T7	468883	8	0	0
T8	23541	52	0	0
T9	66088	853	0	0
T10	18961	140	0	0
T11	361779	11	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218271	0	0
T1	10876	125	0	0
T2	182560	4	0	0
T3	1773	13	0	0
T7	468883	8	0	0
T8	23541	52	0	0
T9	66088	853	0	0
T10	18961	140	0	0
T11	361779	11	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3204989	0	0
T1	10876	121	0	0
T2	182560	14	0	0
T3	1773	13	0	0
T7	468883	2804	0	0
T8	23541	397	0	0
T9	66088	836	0	0
T10	18961	141	0	0
T11	361779	43	0	0
T12	111372	425	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218271	0	0
T1	10876	125	0	0
T2	182560	4	0	0
T3	1773	13	0	0
T7	468883	8	0	0
T8	23541	52	0	0
T9	66088	853	0	0
T10	18961	140	0	0
T11	361779	11	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218271	0	0
T1	10876	125	0	0
T2	182560	4	0	0
T3	1773	13	0	0
T7	468883	8	0	0
T8	23541	52	0	0
T9	66088	853	0	0
T10	18961	140	0	0
T11	361779	11	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	580845	0	0
T1	10876	130	0	0
T2	182560	4	0	0
T3	1773	14	0	0
T7	468883	8	0	0
T8	23541	57	0	0
T9	66088	872	0	0
T10	18961	140	0	0
T11	361779	11	0	0
T12	111372	137	0	0
T13	5936	0	0	0
T14	0	886	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218271	0	0
T1	10876	125	0	0
T2	182560	4	0	0
T3	1773	13	0	0
T7	468883	8	0	0
T8	23541	52	0	0
T9	66088	853	0	0
T10	18961	140	0	0
T11	361779	11	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	224624	0	0
GntImpliesValid_A	421510055	224624	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	224624	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3180308	0	0
ReadyAndValidImplyGrant_A	421510055	224624	0	0
ReqAndReadyImplyGrant_A	421510055	224624	0	0
ReqImpliesValid_A	421510055	629734	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	224624	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224624	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	57	0	0
T9	66088	824	0	0
T10	18961	149	0	0
T11	361779	17	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224624	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	57	0	0
T9	66088	824	0	0
T10	18961	149	0	0
T11	361779	17	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224624	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	57	0	0
T9	66088	824	0	0
T10	18961	149	0	0
T11	361779	17	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3180308	0	0
T1	10876	94	0	0
T2	182560	58	0	0
T3	1773	12	0	0
T7	468883	3731	0	0
T8	23541	381	0	0
T9	66088	803	0	0
T10	18961	150	0	0
T11	361779	62	0	0
T12	111372	380	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224624	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	57	0	0
T9	66088	824	0	0
T10	18961	149	0	0
T11	361779	17	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224624	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	57	0	0
T9	66088	824	0	0
T10	18961	149	0	0
T11	361779	17	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	629734	0	0
T1	10876	101	0	0
T2	182560	20	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	96	0	0
T9	66088	847	0	0
T10	18961	149	0	0
T11	361779	21	0	0
T12	111372	134	0	0
T13	5936	0	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224624	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	57	0	0
T9	66088	824	0	0
T10	18961	149	0	0
T11	361779	17	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	219777	0	0
GntImpliesValid_A	421510055	219777	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	219777	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	5073155	0	0
ReadyAndValidImplyGrant_A	421510055	219777	0	0
ReqAndReadyImplyGrant_A	421510055	219777	0	0
ReqImpliesValid_A	421510055	1180674	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	219777	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219777	0	0
T1	10876	101	0	0
T2	182560	9	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	51	0	0
T9	66088	835	0	0
T10	18961	166	0	0
T11	361779	18	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219777	0	0
T1	10876	101	0	0
T2	182560	9	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	51	0	0
T9	66088	835	0	0
T10	18961	166	0	0
T11	361779	18	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219777	0	0
T1	10876	101	0	0
T2	182560	9	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	51	0	0
T9	66088	835	0	0
T10	18961	166	0	0
T11	361779	18	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	5073155	0	0
T1	10876	1547	0	0
T2	182560	60	0	0
T3	1773	37	0	0
T7	468883	1990	0	0
T8	23541	1222	0	0
T9	66088	11933	0	0
T10	18961	1865	0	0
T11	361779	422	0	0
T12	111372	1798	0	0
T13	5936	0	0	0
T14	0	1296	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219777	0	0
T1	10876	101	0	0
T2	182560	9	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	51	0	0
T9	66088	835	0	0
T10	18961	166	0	0
T11	361779	18	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219777	0	0
T1	10876	101	0	0
T2	182560	9	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	51	0	0
T9	66088	835	0	0
T10	18961	166	0	0
T11	361779	18	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	1180674	0	0
T1	10876	214	0	0
T2	182560	13	0	0
T3	1773	13	0	0
T7	468883	10	0	0
T8	23541	170	0	0
T9	66088	2089	0	0
T10	18961	289	0	0
T11	361779	72	0	0
T12	111372	260	0	0
T13	5936	0	0	0
T14	0	339	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219777	0	0
T1	10876	101	0	0
T2	182560	9	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	51	0	0
T9	66088	835	0	0
T10	18961	166	0	0
T11	361779	18	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	222275	0	0
GntImpliesValid_A	421510055	222275	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	222275	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	4744483	0	0
ReadyAndValidImplyGrant_A	421510055	222275	0	0
ReqAndReadyImplyGrant_A	421510055	222275	0	0
ReqImpliesValid_A	421510055	1174468	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	222275	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222275	0	0
T1	10876	88	0	0
T2	182560	14	0	0
T3	1773	7	0	0
T7	468883	11	0	0
T8	23541	45	0	0
T9	66088	840	0	0
T10	18961	172	0	0
T11	361779	9	0	0
T12	111372	119	0	0
T13	5936	434	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222275	0	0
T1	10876	88	0	0
T2	182560	14	0	0
T3	1773	7	0	0
T7	468883	11	0	0
T8	23541	45	0	0
T9	66088	840	0	0
T10	18961	172	0	0
T11	361779	9	0	0
T12	111372	119	0	0
T13	5936	434	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222275	0	0
T1	10876	88	0	0
T2	182560	14	0	0
T3	1773	7	0	0
T7	468883	11	0	0
T8	23541	45	0	0
T9	66088	840	0	0
T10	18961	172	0	0
T11	361779	9	0	0
T12	111372	119	0	0
T13	5936	434	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	4744483	0	0
T1	10876	706	0	0
T2	182560	158	0	0
T3	1773	24	0	0
T7	468883	7347	0	0
T8	23541	1104	0	0
T9	66088	9085	0	0
T10	18961	2023	0	0
T11	361779	185	0	0
T12	111372	690	0	0
T13	5936	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222275	0	0
T1	10876	88	0	0
T2	182560	14	0	0
T3	1773	7	0	0
T7	468883	11	0	0
T8	23541	45	0	0
T9	66088	840	0	0
T10	18961	172	0	0
T11	361779	9	0	0
T12	111372	119	0	0
T13	5936	434	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222275	0	0
T1	10876	88	0	0
T2	182560	14	0	0
T3	1773	7	0	0
T7	468883	11	0	0
T8	23541	45	0	0
T9	66088	840	0	0
T10	18961	172	0	0
T11	361779	9	0	0
T12	111372	119	0	0
T13	5936	434	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	1174468	0	0
T1	10876	179	0	0
T2	182560	14	0	0
T3	1773	14	0	0
T7	468883	1078	0	0
T8	23541	79	0	0
T9	66088	1799	0	0
T10	18961	257	0	0
T11	361779	22	0	0
T12	111372	178	0	0
T13	5936	2696	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222275	0	0
T1	10876	88	0	0
T2	182560	14	0	0
T3	1773	7	0	0
T7	468883	11	0	0
T8	23541	45	0	0
T9	66088	840	0	0
T10	18961	172	0	0
T11	361779	9	0	0
T12	111372	119	0	0
T13	5936	434	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	218996	0	0
GntImpliesValid_A	421510055	218996	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	218996	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	5015009	0	0
ReadyAndValidImplyGrant_A	421510055	218996	0	0
ReqAndReadyImplyGrant_A	421510055	218996	0	0
ReqImpliesValid_A	421510055	1133461	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	218996	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218996	0	0
T1	10876	119	0	0
T2	182560	12	0	0
T3	1773	9	0	0
T7	468883	14	0	0
T8	23541	39	0	0
T9	66088	812	0	0
T10	18961	172	0	0
T11	361779	10	0	0
T12	111372	105	0	0
T13	5936	0	0	0
T14	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218996	0	0
T1	10876	119	0	0
T2	182560	12	0	0
T3	1773	9	0	0
T7	468883	14	0	0
T8	23541	39	0	0
T9	66088	812	0	0
T10	18961	172	0	0
T11	361779	10	0	0
T12	111372	105	0	0
T13	5936	0	0	0
T14	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218996	0	0
T1	10876	119	0	0
T2	182560	12	0	0
T3	1773	9	0	0
T7	468883	14	0	0
T8	23541	39	0	0
T9	66088	812	0	0
T10	18961	172	0	0
T11	361779	10	0	0
T12	111372	105	0	0
T13	5936	0	0	0
T14	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	5015009	0	0
T1	10876	693	0	0
T2	182560	146	0	0
T3	1773	53	0	0
T7	468883	1162	0	0
T8	23541	804	0	0
T9	66088	4121	0	0
T10	18961	1891	0	0
T11	361779	273	0	0
T12	111372	3132	0	0
T13	5936	0	0	0
T14	0	4376	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218996	0	0
T1	10876	119	0	0
T2	182560	12	0	0
T3	1773	9	0	0
T7	468883	14	0	0
T8	23541	39	0	0
T9	66088	812	0	0
T10	18961	172	0	0
T11	361779	10	0	0
T12	111372	105	0	0
T13	5936	0	0	0
T14	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218996	0	0
T1	10876	119	0	0
T2	182560	12	0	0
T3	1773	9	0	0
T7	468883	14	0	0
T8	23541	39	0	0
T9	66088	812	0	0
T10	18961	172	0	0
T11	361779	10	0	0
T12	111372	105	0	0
T13	5936	0	0	0
T14	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	1133461	0	0
T1	10876	193	0	0
T2	182560	13	0	0
T3	1773	14	0	0
T7	468883	35	0	0
T8	23541	85	0	0
T9	66088	1070	0	0
T10	18961	262	0	0
T11	361779	10	0	0
T12	111372	206	0	0
T13	5936	0	0	0
T14	0	224	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	218996	0	0
T1	10876	119	0	0
T2	182560	12	0	0
T3	1773	9	0	0
T7	468883	14	0	0
T8	23541	39	0	0
T9	66088	812	0	0
T10	18961	172	0	0
T11	361779	10	0	0
T12	111372	105	0	0
T13	5936	0	0	0
T14	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	222256	0	0
GntImpliesValid_A	421510055	222256	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	222256	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	4902036	0	0
ReadyAndValidImplyGrant_A	421510055	222256	0	0
ReqAndReadyImplyGrant_A	421510055	222256	0	0
ReqImpliesValid_A	421510055	1060887	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	222256	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222256	0	0
T1	10876	95	0	0
T2	182560	5	0	0
T3	1773	14	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	869	0	0
T10	18961	155	0	0
T11	361779	10	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222256	0	0
T1	10876	95	0	0
T2	182560	5	0	0
T3	1773	14	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	869	0	0
T10	18961	155	0	0
T11	361779	10	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222256	0	0
T1	10876	95	0	0
T2	182560	5	0	0
T3	1773	14	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	869	0	0
T10	18961	155	0	0
T11	361779	10	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	4902036	0	0
T1	10876	704	0	0
T2	182560	46	0	0
T3	1773	48	0	0
T7	468883	756	0	0
T8	23541	888	0	0
T9	66088	4442	0	0
T10	18961	874	0	0
T11	361779	89	0	0
T12	111372	908	0	0
T13	5936	0	0	0
T14	0	9445	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222256	0	0
T1	10876	95	0	0
T2	182560	5	0	0
T3	1773	14	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	869	0	0
T10	18961	155	0	0
T11	361779	10	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222256	0	0
T1	10876	95	0	0
T2	182560	5	0	0
T3	1773	14	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	869	0	0
T10	18961	155	0	0
T11	361779	10	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	1060887	0	0
T1	10876	153	0	0
T2	182560	5	0	0
T3	1773	26	0	0
T7	468883	14	0	0
T8	23541	139	0	0
T9	66088	1208	0	0
T10	18961	171	0	0
T11	361779	10	0	0
T12	111372	229	0	0
T13	5936	0	0	0
T14	0	490	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222256	0	0
T1	10876	95	0	0
T2	182560	5	0	0
T3	1773	14	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	869	0	0
T10	18961	155	0	0
T11	361779	10	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	224447	0	0
GntImpliesValid_A	421510055	224447	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	224447	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3232920	0	0
ReadyAndValidImplyGrant_A	421510055	224447	0	0
ReqAndReadyImplyGrant_A	421510055	224447	0	0
ReqImpliesValid_A	421510055	602927	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	224447	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224447	0	0
T1	10876	96	0	0
T2	182560	7	0	0
T3	1773	7	0	0
T7	468883	9	0	0
T8	23541	45	0	0
T9	66088	852	0	0
T10	18961	168	0	0
T11	361779	12	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224447	0	0
T1	10876	96	0	0
T2	182560	7	0	0
T3	1773	7	0	0
T7	468883	9	0	0
T8	23541	45	0	0
T9	66088	852	0	0
T10	18961	168	0	0
T11	361779	12	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224447	0	0
T1	10876	96	0	0
T2	182560	7	0	0
T3	1773	7	0	0
T7	468883	9	0	0
T8	23541	45	0	0
T9	66088	852	0	0
T10	18961	168	0	0
T11	361779	12	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3232920	0	0
T1	10876	95	0	0
T2	182560	36	0	0
T3	1773	8	0	0
T7	468883	3571	0	0
T8	23541	385	0	0
T9	66088	830	0	0
T10	18961	165	0	0
T11	361779	64	0	0
T12	111372	375	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224447	0	0
T1	10876	96	0	0
T2	182560	7	0	0
T3	1773	7	0	0
T7	468883	9	0	0
T8	23541	45	0	0
T9	66088	852	0	0
T10	18961	168	0	0
T11	361779	12	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224447	0	0
T1	10876	96	0	0
T2	182560	7	0	0
T3	1773	7	0	0
T7	468883	9	0	0
T8	23541	45	0	0
T9	66088	852	0	0
T10	18961	168	0	0
T11	361779	12	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	602927	0	0
T1	10876	98	0	0
T2	182560	7	0	0
T3	1773	7	0	0
T7	468883	9	0	0
T8	23541	82	0	0
T9	66088	876	0	0
T10	18961	172	0	0
T11	361779	14	0	0
T12	111372	114	0	0
T13	5936	0	0	0
T14	0	342	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	224447	0	0
T1	10876	96	0	0
T2	182560	7	0	0
T3	1773	7	0	0
T7	468883	9	0	0
T8	23541	45	0	0
T9	66088	852	0	0
T10	18961	168	0	0
T11	361779	12	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	227522	0	0
GntImpliesValid_A	421510055	227522	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	227522	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3234151	0	0
ReadyAndValidImplyGrant_A	421510055	227522	0	0
ReqAndReadyImplyGrant_A	421510055	227522	0	0
ReqImpliesValid_A	421510055	623067	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	227522	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	227522	0	0
T1	10876	93	0	0
T2	182560	13	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	54	0	0
T9	66088	860	0	0
T10	18961	183	0	0
T11	361779	17	0	0
T12	111372	118	0	0
T13	5936	0	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	227522	0	0
T1	10876	93	0	0
T2	182560	13	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	54	0	0
T9	66088	860	0	0
T10	18961	183	0	0
T11	361779	17	0	0
T12	111372	118	0	0
T13	5936	0	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	227522	0	0
T1	10876	93	0	0
T2	182560	13	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	54	0	0
T9	66088	860	0	0
T10	18961	183	0	0
T11	361779	17	0	0
T12	111372	118	0	0
T13	5936	0	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3234151	0	0
T1	10876	91	0	0
T2	182560	61	0	0
T3	1773	11	0	0
T7	468883	2647	0	0
T8	23541	463	0	0
T9	66088	832	0	0
T10	18961	183	0	0
T11	361779	64	0	0
T12	111372	466	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	227522	0	0
T1	10876	93	0	0
T2	182560	13	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	54	0	0
T9	66088	860	0	0
T10	18961	183	0	0
T11	361779	17	0	0
T12	111372	118	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	227522	0	0
T1	10876	93	0	0
T2	182560	13	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	54	0	0
T9	66088	860	0	0
T10	18961	183	0	0
T11	361779	17	0	0
T12	111372	118	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	623067	0	0
T1	10876	96	0	0
T2	182560	14	0	0
T3	1773	10	0	0
T7	468883	405	0	0
T8	23541	76	0	0
T9	66088	890	0	0
T10	18961	184	0	0
T11	361779	17	0	0
T12	111372	164	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	227522	0	0
T1	10876	93	0	0
T2	182560	13	0	0
T3	1773	10	0	0
T7	468883	10	0	0
T8	23541	54	0	0
T9	66088	860	0	0
T10	18961	183	0	0
T11	361779	17	0	0
T12	111372	118	0	0
T13	5936	0	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	213577	0	0
GntImpliesValid_A	421510055	213577	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	213577	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3143736	0	0
ReadyAndValidImplyGrant_A	421510055	213577	0	0
ReqAndReadyImplyGrant_A	421510055	213577	0	0
ReqImpliesValid_A	421510055	532244	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	213577	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	213577	0	0
T1	10876	100	0	0
T2	182560	5	0	0
T3	1773	13	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	865	0	0
T10	18961	170	0	0
T11	361779	7	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	213577	0	0
T1	10876	100	0	0
T2	182560	5	0	0
T3	1773	13	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	865	0	0
T10	18961	170	0	0
T11	361779	7	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	213577	0	0
T1	10876	100	0	0
T2	182560	5	0	0
T3	1773	13	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	865	0	0
T10	18961	170	0	0
T11	361779	7	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3143736	0	0
T1	10876	98	0	0
T2	182560	21	0	0
T3	1773	11	0	0
T7	468883	4871	0	0
T8	23541	410	0	0
T9	66088	833	0	0
T10	18961	169	0	0
T11	361779	27	0	0
T12	111372	427	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	213577	0	0
T1	10876	100	0	0
T2	182560	5	0	0
T3	1773	13	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	865	0	0
T10	18961	170	0	0
T11	361779	7	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	213577	0	0
T1	10876	100	0	0
T2	182560	5	0	0
T3	1773	13	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	865	0	0
T10	18961	170	0	0
T11	361779	7	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	532244	0	0
T1	10876	103	0	0
T2	182560	5	0	0
T3	1773	16	0	0
T7	468883	639	0	0
T8	23541	85	0	0
T9	66088	899	0	0
T10	18961	172	0	0
T11	361779	7	0	0
T12	111372	129	0	0
T13	5936	0	0	0
T14	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	213577	0	0
T1	10876	100	0	0
T2	182560	5	0	0
T3	1773	13	0	0
T7	468883	14	0	0
T8	23541	53	0	0
T9	66088	865	0	0
T10	18961	170	0	0
T11	361779	7	0	0
T12	111372	99	0	0
T13	5936	0	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	209198	0	0
GntImpliesValid_A	421510055	209198	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	209198	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3134928	0	0
ReadyAndValidImplyGrant_A	421510055	209198	0	0
ReqAndReadyImplyGrant_A	421510055	209198	0	0
ReqImpliesValid_A	421510055	532052	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	209198	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	209198	0	0
T1	10876	95	0	0
T2	182560	10	0	0
T3	1773	19	0	0
T7	468883	19	0	0
T8	23541	41	0	0
T9	66088	880	0	0
T10	18961	167	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	444	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	209198	0	0
T1	10876	95	0	0
T2	182560	10	0	0
T3	1773	19	0	0
T7	468883	19	0	0
T8	23541	41	0	0
T9	66088	880	0	0
T10	18961	167	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	444	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	209198	0	0
T1	10876	95	0	0
T2	182560	10	0	0
T3	1773	19	0	0
T7	468883	19	0	0
T8	23541	41	0	0
T9	66088	880	0	0
T10	18961	167	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	444	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3134928	0	0
T1	10876	91	0	0
T2	182560	38	0	0
T3	1773	20	0	0
T7	468883	5734	0	0
T8	23541	346	0	0
T9	66088	847	0	0
T10	18961	168	0	0
T11	361779	46	0	0
T12	111372	392	0	0
T13	5936	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	209198	0	0
T1	10876	95	0	0
T2	182560	10	0	0
T3	1773	19	0	0
T7	468883	19	0	0
T8	23541	41	0	0
T9	66088	880	0	0
T10	18961	167	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	444	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	209198	0	0
T1	10876	95	0	0
T2	182560	10	0	0
T3	1773	19	0	0
T7	468883	19	0	0
T8	23541	41	0	0
T9	66088	880	0	0
T10	18961	167	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	444	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	532052	0	0
T1	10876	100	0	0
T2	182560	10	0	0
T3	1773	19	0	0
T7	468883	691	0	0
T8	23541	50	0	0
T9	66088	915	0	0
T10	18961	167	0	0
T11	361779	21	0	0
T12	111372	105	0	0
T13	5936	887	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	209198	0	0
T1	10876	95	0	0
T2	182560	10	0	0
T3	1773	19	0	0
T7	468883	19	0	0
T8	23541	41	0	0
T9	66088	880	0	0
T10	18961	167	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	444	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	223637	0	0
GntImpliesValid_A	421510055	223637	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	223637	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3167513	0	0
ReadyAndValidImplyGrant_A	421510055	223637	0	0
ReqAndReadyImplyGrant_A	421510055	223637	0	0
ReqImpliesValid_A	421510055	583217	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	223637	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	223637	0	0
T1	10876	102	0	0
T2	182560	6	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	33	0	0
T9	66088	881	0	0
T10	18961	138	0	0
T11	361779	10	0	0
T12	111372	98	0	0
T13	5936	0	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	223637	0	0
T1	10876	102	0	0
T2	182560	6	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	33	0	0
T9	66088	881	0	0
T10	18961	138	0	0
T11	361779	10	0	0
T12	111372	98	0	0
T13	5936	0	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	223637	0	0
T1	10876	102	0	0
T2	182560	6	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	33	0	0
T9	66088	881	0	0
T10	18961	138	0	0
T11	361779	10	0	0
T12	111372	98	0	0
T13	5936	0	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3167513	0	0
T1	10876	97	0	0
T2	182560	23	0	0
T3	1773	12	0	0
T7	468883	4071	0	0
T8	23541	283	0	0
T9	66088	860	0	0
T10	18961	137	0	0
T11	361779	43	0	0
T12	111372	395	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	223637	0	0
T1	10876	102	0	0
T2	182560	6	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	33	0	0
T9	66088	881	0	0
T10	18961	138	0	0
T11	361779	10	0	0
T12	111372	98	0	0
T13	5936	0	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	223637	0	0
T1	10876	102	0	0
T2	182560	6	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	33	0	0
T9	66088	881	0	0
T10	18961	138	0	0
T11	361779	10	0	0
T12	111372	98	0	0
T13	5936	0	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	583217	0	0
T1	10876	108	0	0
T2	182560	6	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	42	0	0
T9	66088	904	0	0
T10	18961	140	0	0
T11	361779	10	0	0
T12	111372	107	0	0
T13	5936	0	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	223637	0	0
T1	10876	102	0	0
T2	182560	6	0	0
T3	1773	11	0	0
T7	468883	13	0	0
T8	23541	33	0	0
T9	66088	881	0	0
T10	18961	138	0	0
T11	361779	10	0	0
T12	111372	98	0	0
T13	5936	0	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	210093	0	0
GntImpliesValid_A	421510055	210093	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	210093	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3121240	0	0
ReadyAndValidImplyGrant_A	421510055	210093	0	0
ReqAndReadyImplyGrant_A	421510055	210093	0	0
ReqImpliesValid_A	421510055	532263	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	210093	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	210093	0	0
T1	10876	114	0	0
T2	182560	8	0	0
T3	1773	7	0	0
T7	468883	16	0	0
T8	23541	45	0	0
T9	66088	853	0	0
T10	18961	136	0	0
T11	361779	10	0	0
T12	111372	89	0	0
T13	5936	0	0	0
T14	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	210093	0	0
T1	10876	114	0	0
T2	182560	8	0	0
T3	1773	7	0	0
T7	468883	16	0	0
T8	23541	45	0	0
T9	66088	853	0	0
T10	18961	136	0	0
T11	361779	10	0	0
T12	111372	89	0	0
T13	5936	0	0	0
T14	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	210093	0	0
T1	10876	114	0	0
T2	182560	8	0	0
T3	1773	7	0	0
T7	468883	16	0	0
T8	23541	45	0	0
T9	66088	853	0	0
T10	18961	136	0	0
T11	361779	10	0	0
T12	111372	89	0	0
T13	5936	0	0	0
T14	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3121240	0	0
T1	10876	110	0	0
T2	182560	36	0	0
T3	1773	7	0	0
T7	468883	7464	0	0
T8	23541	310	0	0
T9	66088	835	0	0
T10	18961	136	0	0
T11	361779	38	0	0
T12	111372	364	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	210093	0	0
T1	10876	114	0	0
T2	182560	8	0	0
T3	1773	7	0	0
T7	468883	16	0	0
T8	23541	45	0	0
T9	66088	853	0	0
T10	18961	136	0	0
T11	361779	10	0	0
T12	111372	89	0	0
T13	5936	0	0	0
T14	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	210093	0	0
T1	10876	114	0	0
T2	182560	8	0	0
T3	1773	7	0	0
T7	468883	16	0	0
T8	23541	45	0	0
T9	66088	853	0	0
T10	18961	136	0	0
T11	361779	10	0	0
T12	111372	89	0	0
T13	5936	0	0	0
T14	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	532263	0	0
T1	10876	119	0	0
T2	182560	8	0	0
T3	1773	8	0	0
T7	468883	16	0	0
T8	23541	61	0	0
T9	66088	873	0	0
T10	18961	137	0	0
T11	361779	10	0	0
T12	111372	106	0	0
T13	5936	0	0	0
T14	0	70	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	210093	0	0
T1	10876	114	0	0
T2	182560	8	0	0
T3	1773	7	0	0
T7	468883	16	0	0
T8	23541	45	0	0
T9	66088	853	0	0
T10	18961	136	0	0
T11	361779	10	0	0
T12	111372	89	0	0
T13	5936	0	0	0
T14	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	216458	0	0
GntImpliesValid_A	421510055	216458	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	216458	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3190338	0	0
ReadyAndValidImplyGrant_A	421510055	216458	0	0
ReqAndReadyImplyGrant_A	421510055	216458	0	0
ReqImpliesValid_A	421510055	559438	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	216458	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	216458	0	0
T1	10876	114	0	0
T2	182560	14	0	0
T3	1773	10	0	0
T7	468883	15	0	0
T8	23541	48	0	0
T9	66088	844	0	0
T10	18961	189	0	0
T11	361779	14	0	0
T12	111372	82	0	0
T13	5936	0	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	216458	0	0
T1	10876	114	0	0
T2	182560	14	0	0
T3	1773	10	0	0
T7	468883	15	0	0
T8	23541	48	0	0
T9	66088	844	0	0
T10	18961	189	0	0
T11	361779	14	0	0
T12	111372	82	0	0
T13	5936	0	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	216458	0	0
T1	10876	114	0	0
T2	182560	14	0	0
T3	1773	10	0	0
T7	468883	15	0	0
T8	23541	48	0	0
T9	66088	844	0	0
T10	18961	189	0	0
T11	361779	14	0	0
T12	111372	82	0	0
T13	5936	0	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3190338	0	0
T1	10876	113	0	0
T2	182560	54	0	0
T3	1773	11	0	0
T7	468883	4163	0	0
T8	23541	366	0	0
T9	66088	815	0	0
T10	18961	189	0	0
T11	361779	45	0	0
T12	111372	356	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	216458	0	0
T1	10876	114	0	0
T2	182560	14	0	0
T3	1773	10	0	0
T7	468883	15	0	0
T8	23541	48	0	0
T9	66088	844	0	0
T10	18961	189	0	0
T11	361779	14	0	0
T12	111372	82	0	0
T13	5936	0	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	216458	0	0
T1	10876	114	0	0
T2	182560	14	0	0
T3	1773	10	0	0
T7	468883	15	0	0
T8	23541	48	0	0
T9	66088	844	0	0
T10	18961	189	0	0
T11	361779	14	0	0
T12	111372	82	0	0
T13	5936	0	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	559438	0	0
T1	10876	116	0	0
T2	182560	15	0	0
T3	1773	10	0	0
T7	468883	887	0	0
T8	23541	66	0	0
T9	66088	875	0	0
T10	18961	190	0	0
T11	361779	21	0	0
T12	111372	102	0	0
T13	5936	0	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	216458	0	0
T1	10876	114	0	0
T2	182560	14	0	0
T3	1773	10	0	0
T7	468883	15	0	0
T8	23541	48	0	0
T9	66088	844	0	0
T10	18961	189	0	0
T11	361779	14	0	0
T12	111372	82	0	0
T13	5936	0	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	221625	0	0
GntImpliesValid_A	421510055	221625	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	221625	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3144110	0	0
ReadyAndValidImplyGrant_A	421510055	221625	0	0
ReqAndReadyImplyGrant_A	421510055	221625	0	0
ReqImpliesValid_A	421510055	589285	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	221625	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	221625	0	0
T1	10876	115	0	0
T2	182560	11	0	0
T3	1773	5	0	0
T7	468883	17	0	0
T8	23541	47	0	0
T9	66088	844	0	0
T10	18961	187	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	0	0	0
T14	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	221625	0	0
T1	10876	115	0	0
T2	182560	11	0	0
T3	1773	5	0	0
T7	468883	17	0	0
T8	23541	47	0	0
T9	66088	844	0	0
T10	18961	187	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	0	0	0
T14	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	221625	0	0
T1	10876	115	0	0
T2	182560	11	0	0
T3	1773	5	0	0
T7	468883	17	0	0
T8	23541	47	0	0
T9	66088	844	0	0
T10	18961	187	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	0	0	0
T14	0	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3144110	0	0
T1	10876	113	0	0
T2	182560	50	0	0
T3	1773	6	0	0
T7	468883	6056	0	0
T8	23541	387	0	0
T9	66088	812	0	0
T10	18961	185	0	0
T11	361779	69	0	0
T12	111372	397	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	221625	0	0
T1	10876	115	0	0
T2	182560	11	0	0
T3	1773	5	0	0
T7	468883	17	0	0
T8	23541	47	0	0
T9	66088	844	0	0
T10	18961	187	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	0	0	0
T14	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	221625	0	0
T1	10876	115	0	0
T2	182560	11	0	0
T3	1773	5	0	0
T7	468883	17	0	0
T8	23541	47	0	0
T9	66088	844	0	0
T10	18961	187	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	0	0	0
T14	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	589285	0	0
T1	10876	118	0	0
T2	182560	21	0	0
T3	1773	5	0	0
T7	468883	30	0	0
T8	23541	49	0	0
T9	66088	878	0	0
T10	18961	190	0	0
T11	361779	13	0	0
T12	111372	128	0	0
T13	5936	0	0	0
T14	0	299	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	221625	0	0
T1	10876	115	0	0
T2	182560	11	0	0
T3	1773	5	0	0
T7	468883	17	0	0
T8	23541	47	0	0
T9	66088	844	0	0
T10	18961	187	0	0
T11	361779	13	0	0
T12	111372	97	0	0
T13	5936	0	0	0
T14	0	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	246286	0	0
GntImpliesValid_A	421510055	246286	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	246286	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3327069	0	0
ReadyAndValidImplyGrant_A	421510055	246286	0	0
ReqAndReadyImplyGrant_A	421510055	246286	0	0
ReqImpliesValid_A	421510055	626102	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	246286	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	246286	0	0
T1	10876	184	0	0
T2	182560	12	0	0
T3	1773	11	0	0
T7	468883	21	0	0
T8	23541	84	0	0
T9	66088	944	0	0
T10	18961	164	0	0
T11	361779	12	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	246286	0	0
T1	10876	184	0	0
T2	182560	12	0	0
T3	1773	11	0	0
T7	468883	21	0	0
T8	23541	84	0	0
T9	66088	944	0	0
T10	18961	164	0	0
T11	361779	12	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	246286	0	0
T1	10876	184	0	0
T2	182560	12	0	0
T3	1773	11	0	0
T7	468883	21	0	0
T8	23541	84	0	0
T9	66088	944	0	0
T10	18961	164	0	0
T11	361779	12	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3327069	0	0
T1	10876	175	0	0
T2	182560	51	0	0
T3	1773	10	0	0
T7	468883	5850	0	0
T8	23541	623	0	0
T9	66088	899	0	0
T10	18961	165	0	0
T11	361779	59	0	0
T12	111372	468	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	246286	0	0
T1	10876	184	0	0
T2	182560	12	0	0
T3	1773	11	0	0
T7	468883	21	0	0
T8	23541	84	0	0
T9	66088	944	0	0
T10	18961	164	0	0
T11	361779	12	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	246286	0	0
T1	10876	184	0	0
T2	182560	12	0	0
T3	1773	11	0	0
T7	468883	21	0	0
T8	23541	84	0	0
T9	66088	944	0	0
T10	18961	164	0	0
T11	361779	12	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	626102	0	0
T1	10876	194	0	0
T2	182560	12	0	0
T3	1773	13	0	0
T7	468883	1314	0	0
T8	23541	109	0	0
T9	66088	991	0	0
T10	18961	164	0	0
T11	361779	12	0	0
T12	111372	118	0	0
T13	5936	0	0	0
T14	0	589	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	246286	0	0
T1	10876	184	0	0
T2	182560	12	0	0
T3	1773	11	0	0
T7	468883	21	0	0
T8	23541	84	0	0
T9	66088	944	0	0
T10	18961	164	0	0
T11	361779	12	0	0
T12	111372	103	0	0
T13	5936	0	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	215995	0	0
GntImpliesValid_A	421510055	215995	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	215995	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3152369	0	0
ReadyAndValidImplyGrant_A	421510055	215995	0	0
ReqAndReadyImplyGrant_A	421510055	215995	0	0
ReqImpliesValid_A	421510055	569128	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	215995	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	215995	0	0
T1	10876	111	0	0
T2	182560	12	0	0
T3	1773	13	0	0
T7	468883	10	0	0
T8	23541	63	0	0
T9	66088	882	0	0
T10	18961	175	0	0
T11	361779	5	0	0
T12	111372	93	0	0
T13	5936	0	0	0
T14	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	215995	0	0
T1	10876	111	0	0
T2	182560	12	0	0
T3	1773	13	0	0
T7	468883	10	0	0
T8	23541	63	0	0
T9	66088	882	0	0
T10	18961	175	0	0
T11	361779	5	0	0
T12	111372	93	0	0
T13	5936	0	0	0
T14	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	215995	0	0
T1	10876	111	0	0
T2	182560	12	0	0
T3	1773	13	0	0
T7	468883	10	0	0
T8	23541	63	0	0
T9	66088	882	0	0
T10	18961	175	0	0
T11	361779	5	0	0
T12	111372	93	0	0
T13	5936	0	0	0
T14	0	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3152369	0	0
T1	10876	108	0	0
T2	182560	52	0	0
T3	1773	12	0	0
T7	468883	2789	0	0
T8	23541	476	0	0
T9	66088	858	0	0
T10	18961	173	0	0
T11	361779	17	0	0
T12	111372	400	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	215995	0	0
T1	10876	111	0	0
T2	182560	12	0	0
T3	1773	13	0	0
T7	468883	10	0	0
T8	23541	63	0	0
T9	66088	882	0	0
T10	18961	175	0	0
T11	361779	5	0	0
T12	111372	93	0	0
T13	5936	0	0	0
T14	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	215995	0	0
T1	10876	111	0	0
T2	182560	12	0	0
T3	1773	13	0	0
T7	468883	10	0	0
T8	23541	63	0	0
T9	66088	882	0	0
T10	18961	175	0	0
T11	361779	5	0	0
T12	111372	93	0	0
T13	5936	0	0	0
T14	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	569128	0	0
T1	10876	115	0	0
T2	182560	14	0	0
T3	1773	15	0	0
T7	468883	1672	0	0
T8	23541	66	0	0
T9	66088	908	0	0
T10	18961	178	0	0
T11	361779	5	0	0
T12	111372	94	0	0
T13	5936	0	0	0
T14	0	624	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	215995	0	0
T1	10876	111	0	0
T2	182560	12	0	0
T3	1773	13	0	0
T7	468883	10	0	0
T8	23541	63	0	0
T9	66088	882	0	0
T10	18961	175	0	0
T11	361779	5	0	0
T12	111372	93	0	0
T13	5936	0	0	0
T14	0	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	219634	0	0
GntImpliesValid_A	421510055	219634	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	219634	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3194303	0	0
ReadyAndValidImplyGrant_A	421510055	219634	0	0
ReqAndReadyImplyGrant_A	421510055	219634	0	0
ReqImpliesValid_A	421510055	596089	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	219634	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219634	0	0
T1	10876	131	0	0
T2	182560	9	0	0
T3	1773	13	0	0
T7	468883	11	0	0
T8	23541	44	0	0
T9	66088	841	0	0
T10	18961	162	0	0
T11	361779	16	0	0
T12	111372	106	0	0
T13	5936	0	0	0
T14	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219634	0	0
T1	10876	131	0	0
T2	182560	9	0	0
T3	1773	13	0	0
T7	468883	11	0	0
T8	23541	44	0	0
T9	66088	841	0	0
T10	18961	162	0	0
T11	361779	16	0	0
T12	111372	106	0	0
T13	5936	0	0	0
T14	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219634	0	0
T1	10876	131	0	0
T2	182560	9	0	0
T3	1773	13	0	0
T7	468883	11	0	0
T8	23541	44	0	0
T9	66088	841	0	0
T10	18961	162	0	0
T11	361779	16	0	0
T12	111372	106	0	0
T13	5936	0	0	0
T14	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3194303	0	0
T1	10876	125	0	0
T2	182560	43	0	0
T3	1773	14	0	0
T7	468883	3999	0	0
T8	23541	307	0	0
T9	66088	819	0	0
T10	18961	163	0	0
T11	361779	63	0	0
T12	111372	440	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219634	0	0
T1	10876	131	0	0
T2	182560	9	0	0
T3	1773	13	0	0
T7	468883	11	0	0
T8	23541	44	0	0
T9	66088	841	0	0
T10	18961	162	0	0
T11	361779	16	0	0
T12	111372	106	0	0
T13	5936	0	0	0
T14	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219634	0	0
T1	10876	131	0	0
T2	182560	9	0	0
T3	1773	13	0	0
T7	468883	11	0	0
T8	23541	44	0	0
T9	66088	841	0	0
T10	18961	162	0	0
T11	361779	16	0	0
T12	111372	106	0	0
T13	5936	0	0	0
T14	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	596089	0	0
T1	10876	138	0	0
T2	182560	9	0	0
T3	1773	13	0	0
T7	468883	11	0	0
T8	23541	61	0	0
T9	66088	865	0	0
T10	18961	162	0	0
T11	361779	16	0	0
T12	111372	123	0	0
T13	5936	0	0	0
T14	0	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	219634	0	0
T1	10876	131	0	0
T2	182560	9	0	0
T3	1773	13	0	0
T7	468883	11	0	0
T8	23541	44	0	0
T9	66088	841	0	0
T10	18961	162	0	0
T11	361779	16	0	0
T12	111372	106	0	0
T13	5936	0	0	0
T14	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	222495	0	0
GntImpliesValid_A	421510055	222495	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	222495	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3158604	0	0
ReadyAndValidImplyGrant_A	421510055	222495	0	0
ReqAndReadyImplyGrant_A	421510055	222495	0	0
ReqImpliesValid_A	421510055	574634	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	222495	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222495	0	0
T1	10876	94	0	0
T2	182560	8	0	0
T3	1773	6	0	0
T7	468883	14	0	0
T8	23541	40	0	0
T9	66088	901	0	0
T10	18961	152	0	0
T11	361779	16	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222495	0	0
T1	10876	94	0	0
T2	182560	8	0	0
T3	1773	6	0	0
T7	468883	14	0	0
T8	23541	40	0	0
T9	66088	901	0	0
T10	18961	152	0	0
T11	361779	16	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222495	0	0
T1	10876	94	0	0
T2	182560	8	0	0
T3	1773	6	0	0
T7	468883	14	0	0
T8	23541	40	0	0
T9	66088	901	0	0
T10	18961	152	0	0
T11	361779	16	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3158604	0	0
T1	10876	92	0	0
T2	182560	35	0	0
T3	1773	6	0	0
T7	468883	5320	0	0
T8	23541	275	0	0
T9	66088	873	0	0
T10	18961	153	0	0
T11	361779	72	0	0
T12	111372	408	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222495	0	0
T1	10876	94	0	0
T2	182560	8	0	0
T3	1773	6	0	0
T7	468883	14	0	0
T8	23541	40	0	0
T9	66088	901	0	0
T10	18961	152	0	0
T11	361779	16	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222495	0	0
T1	10876	94	0	0
T2	182560	8	0	0
T3	1773	6	0	0
T7	468883	14	0	0
T8	23541	40	0	0
T9	66088	901	0	0
T10	18961	152	0	0
T11	361779	16	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	574634	0	0
T1	10876	97	0	0
T2	182560	9	0	0
T3	1773	7	0	0
T7	468883	14	0	0
T8	23541	60	0	0
T9	66088	931	0	0
T10	18961	152	0	0
T11	361779	22	0	0
T12	111372	118	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	222495	0	0
T1	10876	94	0	0
T2	182560	8	0	0
T3	1773	6	0	0
T7	468883	14	0	0
T8	23541	40	0	0
T9	66088	901	0	0
T10	18961	152	0	0
T11	361779	16	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	212446	0	0
GntImpliesValid_A	421510055	212446	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	212446	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3135238	0	0
ReadyAndValidImplyGrant_A	421510055	212446	0	0
ReqAndReadyImplyGrant_A	421510055	212446	0	0
ReqImpliesValid_A	421510055	525820	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	212446	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	212446	0	0
T1	10876	105	0	0
T2	182560	7	0	0
T3	1773	8	0	0
T7	468883	13	0	0
T8	23541	43	0	0
T9	66088	881	0	0
T10	18961	168	0	0
T11	361779	13	0	0
T12	111372	83	0	0
T13	5936	970	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	212446	0	0
T1	10876	105	0	0
T2	182560	7	0	0
T3	1773	8	0	0
T7	468883	13	0	0
T8	23541	43	0	0
T9	66088	881	0	0
T10	18961	168	0	0
T11	361779	13	0	0
T12	111372	83	0	0
T13	5936	970	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	212446	0	0
T1	10876	105	0	0
T2	182560	7	0	0
T3	1773	8	0	0
T7	468883	13	0	0
T8	23541	43	0	0
T9	66088	881	0	0
T10	18961	168	0	0
T11	361779	13	0	0
T12	111372	83	0	0
T13	5936	970	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3135238	0	0
T1	10876	102	0	0
T2	182560	32	0	0
T3	1773	9	0	0
T7	468883	4069	0	0
T8	23541	392	0	0
T9	66088	840	0	0
T10	18961	166	0	0
T11	361779	55	0	0
T12	111372	303	0	0
T13	5936	46	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	212446	0	0
T1	10876	105	0	0
T2	182560	7	0	0
T3	1773	8	0	0
T7	468883	13	0	0
T8	23541	43	0	0
T9	66088	881	0	0
T10	18961	168	0	0
T11	361779	13	0	0
T12	111372	83	0	0
T13	5936	970	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	212446	0	0
T1	10876	105	0	0
T2	182560	7	0	0
T3	1773	8	0	0
T7	468883	13	0	0
T8	23541	43	0	0
T9	66088	881	0	0
T10	18961	168	0	0
T11	361779	13	0	0
T12	111372	83	0	0
T13	5936	970	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	525820	0	0
T1	10876	109	0	0
T2	182560	11	0	0
T3	1773	8	0	0
T7	468883	13	0	0
T8	23541	43	0	0
T9	66088	924	0	0
T10	18961	171	0	0
T11	361779	13	0	0
T12	111372	98	0	0
T13	5936	1895	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	212446	0	0
T1	10876	105	0	0
T2	182560	7	0	0
T3	1773	8	0	0
T7	468883	13	0	0
T8	23541	43	0	0
T9	66088	881	0	0
T10	18961	168	0	0
T11	361779	13	0	0
T12	111372	83	0	0
T13	5936	970	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	226873	0	0
GntImpliesValid_A	421510055	226873	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	226873	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	3168414	0	0
ReadyAndValidImplyGrant_A	421510055	226873	0	0
ReqAndReadyImplyGrant_A	421510055	226873	0	0
ReqImpliesValid_A	421510055	630577	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	0	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	226873	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	226873	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	12	0	0
T7	468883	19	0	0
T8	23541	33	0	0
T9	66088	871	0	0
T10	18961	156	0	0
T11	361779	11	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	226873	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	12	0	0
T7	468883	19	0	0
T8	23541	33	0	0
T9	66088	871	0	0
T10	18961	156	0	0
T11	361779	11	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	226873	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	12	0	0
T7	468883	19	0	0
T8	23541	33	0	0
T9	66088	871	0	0
T10	18961	156	0	0
T11	361779	11	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	3168414	0	0
T1	10876	94	0	0
T2	182560	58	0	0
T3	1773	13	0	0
T7	468883	6035	0	0
T8	23541	236	0	0
T9	66088	847	0	0
T10	18961	154	0	0
T11	361779	54	0	0
T12	111372	393	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	226873	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	12	0	0
T7	468883	19	0	0
T8	23541	33	0	0
T9	66088	871	0	0
T10	18961	156	0	0
T11	361779	11	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	226873	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	12	0	0
T7	468883	19	0	0
T8	23541	33	0	0
T9	66088	871	0	0
T10	18961	156	0	0
T11	361779	11	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	630577	0	0
T1	10876	101	0	0
T2	182560	14	0	0
T3	1773	12	0	0
T7	468883	19	0	0
T8	23541	33	0	0
T9	66088	897	0	0
T10	18961	159	0	0
T11	361779	14	0	0
T12	111372	113	0	0
T13	5936	0	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	226873	0	0
T1	10876	97	0	0
T2	182560	14	0	0
T3	1773	12	0	0
T7	468883	19	0	0
T8	23541	33	0	0
T9	66088	871	0	0
T10	18961	156	0	0
T11	361779	11	0	0
T12	111372	100	0	0
T13	5936	0	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	905011	0	0
GntImpliesValid_A	421510055	905011	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	905011	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	11839978	0	0
ReadyAndValidImplyGrant_A	421510055	905011	0	0
ReqAndReadyImplyGrant_A	421510055	905011	0	0
ReqImpliesValid_A	421510055	2368902	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	16586	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	905011	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	905011	0	0
T1	10876	445	0	0
T2	182560	45	0	0
T3	1773	65	0	0
T7	468883	58	0	0
T8	23541	159	0	0
T9	66088	3256	0	0
T10	18961	627	0	0
T11	361779	65	0	0
T12	111372	428	0	0
T13	5936	231	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	905011	0	0
T1	10876	445	0	0
T2	182560	45	0	0
T3	1773	65	0	0
T7	468883	58	0	0
T8	23541	159	0	0
T9	66088	3256	0	0
T10	18961	627	0	0
T11	361779	65	0	0
T12	111372	428	0	0
T13	5936	231	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	905011	0	0
T1	10876	445	0	0
T2	182560	45	0	0
T3	1773	65	0	0
T7	468883	58	0	0
T8	23541	159	0	0
T9	66088	3256	0	0
T10	18961	627	0	0
T11	361779	65	0	0
T12	111372	428	0	0
T13	5936	231	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	11839978	0	0
T1	10876	1	0	0
T2	182560	123	0	0
T3	1773	1	0	0
T7	468883	21042	0	0
T8	23541	1057	0	0
T9	66088	2	0	0
T10	18961	1	0	0
T11	361779	212	0	0
T12	111372	1392	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	905011	0	0
T1	10876	445	0	0
T2	182560	45	0	0
T3	1773	65	0	0
T7	468883	58	0	0
T8	23541	159	0	0
T9	66088	3256	0	0
T10	18961	627	0	0
T11	361779	65	0	0
T12	111372	428	0	0
T13	5936	231	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	905011	0	0
T1	10876	445	0	0
T2	182560	45	0	0
T3	1773	65	0	0
T7	468883	58	0	0
T8	23541	159	0	0
T9	66088	3256	0	0
T10	18961	627	0	0
T11	361779	65	0	0
T12	111372	428	0	0
T13	5936	231	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	2368902	0	0
T1	10876	445	0	0
T2	182560	61	0	0
T3	1773	65	0	0
T7	468883	1532	0	0
T8	23541	202	0	0
T9	66088	3256	0	0
T10	18961	627	0	0
T11	361779	103	0	0
T12	111372	580	0	0
T13	5936	231	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	16586	0	900
T1	10876	8	0	1
T2	182560	0	0	1
T3	1773	0	0	1
T7	468883	0	0	1
T8	23541	0	0	1
T9	66088	34	0	1
T10	18961	8	0	1
T11	361779	0	0	1
T12	111372	0	0	1
T13	5936	0	0	1
T15	0	1	0	0
T16	0	4	0	0
T17	0	27	0	0
T18	0	19	0	0
T19	0	1	0	0
T20	0	14	0	0
T21	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	905011	0	0
T1	10876	445	0	0
T2	182560	45	0	0
T3	1773	65	0	0
T7	468883	58	0	0
T8	23541	159	0	0
T9	66088	3256	0	0
T10	18961	627	0	0
T11	361779	65	0	0
T12	111372	428	0	0
T13	5936	231	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421510055	421382314	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421510055	877967	0	0
GntImpliesValid_A	421510055	877967	0	0
GrantKnown_A	421510055	421382314	0	0
IdxKnown_A	421510055	421382314	0	0
IndexIsCorrect_A	421510055	877967	0	0
LockArbDecision_A	421510055	0	0	0
NoReadyValidNoGrant_A	421510055	354689622	0	0
ReadyAndValidImplyGrant_A	421510055	877967	0	0
ReqAndReadyImplyGrant_A	421510055	877967	0	0
ReqImpliesValid_A	421510055	13714118	0	0
ReqStaysHighUntilGranted0_M	421510055	0	0	0
RoundRobin_A	421510055	21908	0	900
ValidKnown_A	421510055	421382314	0	0
gen_data_port_assertion.DataFlow_A	421510055	877967	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877967	0	0
T1	10876	465	0	0
T2	182560	37	0	0
T3	1773	66	0	0
T7	468883	44	0	0
T8	23541	156	0	0
T9	66088	3380	0	0
T10	18961	656	0	0
T11	361779	60	0	0
T12	111372	411	0	0
T13	5936	256	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877967	0	0
T1	10876	465	0	0
T2	182560	37	0	0
T3	1773	66	0	0
T7	468883	44	0	0
T8	23541	156	0	0
T9	66088	3380	0	0
T10	18961	656	0	0
T11	361779	60	0	0
T12	111372	411	0	0
T13	5936	256	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877967	0	0
T1	10876	465	0	0
T2	182560	37	0	0
T3	1773	66	0	0
T7	468883	44	0	0
T8	23541	156	0	0
T9	66088	3380	0	0
T10	18961	656	0	0
T11	361779	60	0	0
T12	111372	411	0	0
T13	5936	256	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	354689622	0	0
T1	10876	1	0	0
T2	182560	151961	0	0
T3	1773	1	0	0
T7	468883	449353	0	0
T8	23541	20101	0	0
T9	66088	1	0	0
T10	18961	1	0	0
T11	361779	301370	0	0
T12	111372	926557	0	0
T13	5936	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877967	0	0
T1	10876	465	0	0
T2	182560	37	0	0
T3	1773	66	0	0
T7	468883	44	0	0
T8	23541	156	0	0
T9	66088	3380	0	0
T10	18961	656	0	0
T11	361779	60	0	0
T12	111372	411	0	0
T13	5936	256	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877967	0	0
T1	10876	465	0	0
T2	182560	37	0	0
T3	1773	66	0	0
T7	468883	44	0	0
T8	23541	156	0	0
T9	66088	3380	0	0
T10	18961	656	0	0
T11	361779	60	0	0
T12	111372	411	0	0
T13	5936	256	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	13714118	0	0
T1	10876	465	0	0
T2	182560	170	0	0
T3	1773	66	0	0
T7	468883	18644	0	0
T8	23541	1386	0	0
T9	66088	3380	0	0
T10	18961	656	0	0
T11	361779	282	0	0
T12	111372	1760	0	0
T13	5936	256	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	21908	0	900
T1	10876	6	0	1
T2	182560	0	0	1
T3	1773	0	0	1
T7	468883	0	0	1
T8	23541	0	0	1
T9	66088	53	0	1
T10	18961	10	0	1
T11	361779	0	0	1
T12	111372	0	0	1
T13	5936	0	0	1
T16	0	2	0	0
T17	0	8	0	0
T18	0	18	0	0
T19	0	17	0	0
T20	0	14	0	0
T21	0	10	0	0
T22	0	1488	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	421382314	0	0
T1	10876	10827	0	0
T2	182560	182496	0	0
T3	1773	1736	0	0
T7	468883	468873	0	0
T8	23541	23483	0	0
T9	66088	65901	0	0
T10	18961	18887	0	0
T11	361779	361705	0	0
T12	111372	111369	0	0
T13	5936	5894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421510055	877967	0	0
T1	10876	465	0	0
T2	182560	37	0	0
T3	1773	66	0	0
T7	468883	44	0	0
T8	23541	156	0	0
T9	66088	3380	0	0
T10	18961	656	0	0
T11	361779	60	0	0
T12	111372	411	0	0
T13	5936	256	0	0