Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1530703	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

243084

1

T1

9

T2

474

T3

447

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	603515	1			T1	42		T2	1116		T3	1061
values[0x0]	568715	1			T1	10		T2	1148		T3	1054
values[0x1]	601557	1			T1	45		T2	1176		T3	1027

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1181970	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

591817

1

T1

38

T2

1122

T3

1038

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27147	1			T2	48		T3	50		T8	8
valid_sources[0x01]	27751	1			T2	57		T3	78		T8	12
valid_sources[0x02]	27739	1			T1	5		T2	54		T3	34
valid_sources[0x03]	28110	1			T1	1		T2	65		T3	32
valid_sources[0x04]	28090	1			T1	2		T2	64		T3	13
valid_sources[0x05]	27693	1			T1	1		T2	56		T3	55
valid_sources[0x06]	27523	1			T1	1		T2	60		T3	90
valid_sources[0x07]	28140	1			T1	1		T2	52		T3	51
valid_sources[0x08]	28255	1			T2	51		T3	12		T8	9
valid_sources[0x09]	26948	1			T1	1		T2	56		T3	3
valid_sources[0x0a]	28154	1			T2	49		T3	28		T8	12
valid_sources[0x0b]	28168	1			T1	1		T2	55		T3	31
valid_sources[0x0c]	27826	1			T1	2		T2	57		T3	24
valid_sources[0x0d]	28515	1			T1	1		T2	56		T3	64
valid_sources[0x0e]	27944	1			T1	2		T2	48		T3	73
valid_sources[0x0f]	27062	1			T1	2		T2	42		T3	20
valid_sources[0x10]	27764	1			T1	2		T2	53		T3	25
valid_sources[0x11]	28875	1			T2	47		T3	75		T8	17
valid_sources[0x12]	27807	1			T1	1		T2	49		T3	22
valid_sources[0x13]	27293	1			T1	2		T2	60		T3	136
valid_sources[0x14]	27942	1			T1	4		T2	55		T8	2
valid_sources[0x15]	26753	1			T1	2		T2	58		T3	35
valid_sources[0x16]	27728	1			T1	4		T2	45		T3	41
valid_sources[0x17]	27556	1			T1	2		T2	60		T3	2
valid_sources[0x18]	28350	1			T1	1		T2	48		T3	59
valid_sources[0x19]	28851	1			T1	3		T2	51		T3	107
valid_sources[0x1a]	28373	1			T1	3		T2	44		T3	22
valid_sources[0x1b]	27836	1			T2	48		T3	58		T8	29
valid_sources[0x1c]	27143	1			T1	3		T2	36		T3	16
valid_sources[0x1d]	27482	1			T1	1		T2	56		T3	72
valid_sources[0x1e]	27502	1			T1	1		T2	50		T3	75
valid_sources[0x1f]	27447	1			T1	2		T2	46		T3	94
valid_sources[0x20]	27646	1			T1	1		T2	58		T3	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25566

1

T1

1

T2

56

T3

52

values[0x0]

all_enables

biggest_size

192016

1

T1

4

T2

384

T3

344

values[0x1]

all_enables

biggest_size

25502

1

T1

4

T2

34

T3

51

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1541121	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

250984

1

T1

10

T2

479

T3

446

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	614713	1			T1	63		T2	1132		T3	1022
values[0x0]	563039	1			T1	9		T2	1129		T3	968
values[0x1]	614353	1			T1	49		T2	1118		T3	1030

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1182038	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

610067

1

T1

43

T2

1150

T3

1067

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28510	1			T1	1		T2	59		T3	47
valid_sources[0x01]	28330	1			T2	67		T3	42		T4	7
valid_sources[0x02]	27626	1			T1	1		T2	47		T3	59
valid_sources[0x03]	27963	1			T2	52		T3	48		T8	24
valid_sources[0x04]	27819	1			T1	4		T2	50		T3	43
valid_sources[0x05]	28216	1			T1	1		T2	70		T3	46
valid_sources[0x06]	27431	1			T1	3		T2	48		T3	47
valid_sources[0x07]	28678	1			T1	1		T2	45		T3	44
valid_sources[0x08]	28274	1			T1	1		T2	46		T3	48
valid_sources[0x09]	27215	1			T1	2		T2	45		T3	42
valid_sources[0x0a]	29013	1			T1	3		T2	56		T3	47
valid_sources[0x0b]	28086	1			T1	1		T2	42		T3	44
valid_sources[0x0c]	28362	1			T1	5		T2	50		T3	38
valid_sources[0x0d]	28203	1			T1	3		T2	49		T3	52
valid_sources[0x0e]	27904	1			T1	1		T2	50		T3	43
valid_sources[0x0f]	27737	1			T1	1		T2	59		T3	44
valid_sources[0x10]	28747	1			T1	3		T2	51		T3	43
valid_sources[0x11]	28499	1			T2	58		T3	53		T8	10
valid_sources[0x12]	28081	1			T1	3		T2	51		T3	58
valid_sources[0x13]	27786	1			T1	1		T2	61		T3	45
valid_sources[0x14]	28382	1			T1	2		T2	39		T3	46
valid_sources[0x15]	27657	1			T1	2		T2	50		T3	62
valid_sources[0x16]	28173	1			T1	2		T2	49		T3	51
valid_sources[0x17]	27650	1			T2	60		T3	47		T7	4
valid_sources[0x18]	28551	1			T1	1		T2	60		T3	45
valid_sources[0x19]	28341	1			T1	1		T2	39		T3	51
valid_sources[0x1a]	28303	1			T1	1		T2	55		T3	43
valid_sources[0x1b]	27774	1			T1	2		T2	58		T3	63
valid_sources[0x1c]	27683	1			T1	3		T2	46		T3	51
valid_sources[0x1d]	27376	1			T1	2		T2	53		T3	55
valid_sources[0x1e]	28044	1			T1	1		T2	53		T3	41
valid_sources[0x1f]	28265	1			T1	2		T2	41		T3	52
valid_sources[0x20]	27717	1			T1	2		T2	48		T3	50

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26474

1

T1

3

T2

51

T3

48

values[0x0]

all_enables

biggest_size

198211

1

T1

2

T2

382

T3

356

values[0x1]

all_enables

biggest_size

26299

1

T1

5

T2

46

T3

42

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1541426	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246438

1

T1

10

T2

523

T3

395

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	607074	1			T1	31		T2	1218		T3	966
values[0x0]	573959	1			T1	12		T2	1178		T3	989
values[0x1]	606831	1			T1	39		T2	1196		T3	898

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1190916	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

596948

1

T1

28

T2

1225

T3

928

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27021	1			T1	1		T2	49		T3	40
valid_sources[0x01]	27770	1			T2	58		T3	43		T8	14
valid_sources[0x02]	27934	1			T1	2		T2	54		T3	44
valid_sources[0x03]	28464	1			T2	51		T3	33		T8	6
valid_sources[0x04]	28103	1			T1	3		T2	58		T3	44
valid_sources[0x05]	27710	1			T2	60		T3	32		T8	8
valid_sources[0x06]	26981	1			T1	1		T2	70		T3	25
valid_sources[0x07]	27538	1			T1	2		T2	41		T3	48
valid_sources[0x08]	28807	1			T1	3		T2	61		T3	54
valid_sources[0x09]	27758	1			T1	2		T2	61		T3	58
valid_sources[0x0a]	28388	1			T2	61		T3	40		T8	14
valid_sources[0x0b]	27195	1			T1	2		T2	51		T3	39
valid_sources[0x0c]	26519	1			T1	4		T2	63		T3	32
valid_sources[0x0d]	28102	1			T1	1		T2	53		T3	58
valid_sources[0x0e]	27545	1			T2	59		T3	61		T8	1
valid_sources[0x0f]	27921	1			T1	1		T2	63		T3	36
valid_sources[0x10]	26503	1			T2	66		T3	49		T8	5
valid_sources[0x11]	28241	1			T1	1		T2	60		T3	47
valid_sources[0x12]	27689	1			T2	54		T3	31		T8	15
valid_sources[0x13]	27499	1			T2	48		T3	61		T8	11
valid_sources[0x14]	28731	1			T1	4		T2	57		T3	67
valid_sources[0x15]	28043	1			T2	54		T3	49		T8	8
valid_sources[0x16]	28256	1			T1	2		T2	53		T3	52
valid_sources[0x17]	27613	1			T1	1		T2	62		T3	32
valid_sources[0x18]	27568	1			T1	1		T2	53		T3	49
valid_sources[0x19]	28027	1			T1	1		T2	50		T3	45
valid_sources[0x1a]	28157	1			T1	2		T2	61		T3	41
valid_sources[0x1b]	28197	1			T1	3		T2	55		T3	36
valid_sources[0x1c]	27572	1			T1	2		T2	58		T3	49
valid_sources[0x1d]	27727	1			T2	40		T3	39		T8	11
valid_sources[0x1e]	27328	1			T2	53		T3	35		T8	12
valid_sources[0x1f]	27857	1			T1	1		T2	61		T3	51
valid_sources[0x20]	27374	1			T1	1		T2	60		T3	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26024

1

T1

4

T2

62

T3

35

values[0x0]

all_enables

biggest_size

194533

1

T1

4

T2

411

T3

321

values[0x1]

all_enables

biggest_size

25881

1

T1

2

T2

50

T3

39