Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7885620	0	0
GntImpliesValid_A	2147483647	7885620	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7885620	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	467182500	0	0
ReadyAndValidImplyGrant_A	2147483647	7885620	0	0
ReqAndReadyImplyGrant_A	2147483647	7885620	0	0
ReqImpliesValid_A	2147483647	35316563	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	44697	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7885620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	296904	286320	0	0
T2	12342384	12342264	0	0
T3	330504	330312	0	0
T4	1194984	1193688	0	0
T7	1170816	1170408	0	0
T8	150768	148680	0	0
T9	124344	123744	0	0
T10	1797840	1797624	0	0
T11	96456	96072	0	0
T12	12947112	12945408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7885620	0	0
T1	296904	6384	0	0
T2	12342384	10407	0	0
T3	330504	9007	0	0
T4	1194984	2346	0	0
T7	1170816	5775	0	0
T8	150768	2246	0	0
T9	124344	2185	0	0
T10	1797840	9280	0	0
T11	96456	2445	0	0
T12	12947112	1632	0	0
T13	0	1883	0	0
T14	0	863	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7885620	0	0
T1	296904	6384	0	0
T2	12342384	10407	0	0
T3	330504	9007	0	0
T4	1194984	2346	0	0
T7	1170816	5775	0	0
T8	150768	2246	0	0
T9	124344	2185	0	0
T10	1797840	9280	0	0
T11	96456	2445	0	0
T12	12947112	1632	0	0
T13	0	1883	0	0
T14	0	863	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	296904	286320	0	0
T2	12342384	12342264	0	0
T3	330504	330312	0	0
T4	1194984	1193688	0	0
T7	1170816	1170408	0	0
T8	150768	148680	0	0
T9	124344	123744	0	0
T10	1797840	1797624	0	0
T11	96456	96072	0	0
T12	12947112	12945408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	296904	286320	0	0
T2	12342384	12342264	0	0
T3	330504	330312	0	0
T4	1194984	1193688	0	0
T7	1170816	1170408	0	0
T8	150768	148680	0	0
T9	124344	123744	0	0
T10	1797840	1797624	0	0
T11	96456	96072	0	0
T12	12947112	12945408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7885620	0	0
T1	296904	6384	0	0
T2	12342384	10407	0	0
T3	330504	9007	0	0
T4	1194984	2346	0	0
T7	1170816	5775	0	0
T8	150768	2246	0	0
T9	124344	2185	0	0
T10	1797840	9280	0	0
T11	96456	2445	0	0
T12	12947112	1632	0	0
T13	0	1883	0	0
T14	0	863	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	467182500	0	0
T1	296904	6313	0	0
T2	12342384	473316	0	0
T3	330504	8688	0	0
T4	1194984	66979	0	0
T7	1170816	75113	0	0
T8	150768	4315	0	0
T9	124344	2437	0	0
T10	1797840	92503	0	0
T11	96456	2641	0	0
T12	12947112	456001	0	0
T13	0	3245	0	0
T14	0	6518	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7885620	0	0
T1	296904	6384	0	0
T2	12342384	10407	0	0
T3	330504	9007	0	0
T4	1194984	2346	0	0
T7	1170816	5775	0	0
T8	150768	2246	0	0
T9	124344	2185	0	0
T10	1797840	9280	0	0
T11	96456	2445	0	0
T12	12947112	1632	0	0
T13	0	1883	0	0
T14	0	863	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7885620	0	0
T1	296904	6384	0	0
T2	12342384	10407	0	0
T3	330504	9007	0	0
T4	1194984	2346	0	0
T7	1170816	5775	0	0
T8	150768	2246	0	0
T9	124344	2185	0	0
T10	1797840	9280	0	0
T11	96456	2445	0	0
T12	12947112	1632	0	0
T13	0	1883	0	0
T14	0	863	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35316563	0	0
T1	296904	7579	0	0
T2	12342384	29272	0	0
T3	330504	10257	0	0
T4	1194984	4495	0	0
T7	1170816	13155	0	0
T8	150768	2935	0	0
T9	124344	2387	0	0
T10	1797840	49571	0	0
T11	96456	2848	0	0
T12	12947112	2785	0	0
T13	0	2388	0	0
T14	0	1447	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44697	0	21600
T1	24742	116	0	2
T2	1028532	5	0	2
T3	27542	46	0	2
T4	99582	0	0	2
T7	97568	3	0	2
T8	12564	6	0	2
T9	10362	10	0	2
T10	149820	0	0	2
T11	8038	7	0	2
T12	1078926	0	0	2
T13	0	9	0	0
T14	0	3	0	0
T15	0	27	0	0
T16	0	482	0	0
T17	0	35	0	0
T18	0	5	0	0
T19	0	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	296904	286320	0	0
T2	12342384	12342264	0	0
T3	330504	330312	0	0
T4	1194984	1193688	0	0
T7	1170816	1170408	0	0
T8	150768	148680	0	0
T9	124344	123744	0	0
T10	1797840	1797624	0	0
T11	96456	96072	0	0
T12	12947112	12945408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7885620	0	0
T1	296904	6384	0	0
T2	12342384	10407	0	0
T3	330504	9007	0	0
T4	1194984	2346	0	0
T7	1170816	5775	0	0
T8	150768	2246	0	0
T9	124344	2185	0	0
T10	1797840	9280	0	0
T11	96456	2445	0	0
T12	12947112	1632	0	0
T13	0	1883	0	0
T14	0	863	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	867381	0	0
GntImpliesValid_A	430116088	867381	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	867381	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	12289379	0	0
ReadyAndValidImplyGrant_A	430116088	867381	0	0
ReqAndReadyImplyGrant_A	430116088	867381	0	0
ReqImpliesValid_A	430116088	2499864	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	867381	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	867381	0	0
T1	12371	676	0	0
T2	514266	2302	0	0
T3	13771	1033	0	0
T4	49791	263	0	0
T7	48784	625	0	0
T8	6282	241	0	0
T9	5181	236	0	0
T10	74910	801	0	0
T11	4019	267	0	0
T12	539463	162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	867381	0	0
T1	12371	676	0	0
T2	514266	2302	0	0
T3	13771	1033	0	0
T4	49791	263	0	0
T7	48784	625	0	0
T8	6282	241	0	0
T9	5181	236	0	0
T10	74910	801	0	0
T11	4019	267	0	0
T12	539463	162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	867381	0	0
T1	12371	676	0	0
T2	514266	2302	0	0
T3	13771	1033	0	0
T4	49791	263	0	0
T7	48784	625	0	0
T8	6282	241	0	0
T9	5181	236	0	0
T10	74910	801	0	0
T11	4019	267	0	0
T12	539463	162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	12289379	0	0
T1	12371	533	0	0
T2	514266	8103	0	0
T3	13771	744	0	0
T4	49791	2045	0	0
T7	48784	4586	0	0
T8	6282	181	0	0
T9	5181	195	0	0
T10	74910	6049	0	0
T11	4019	186	0	0
T12	539463	684	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	867381	0	0
T1	12371	676	0	0
T2	514266	2302	0	0
T3	13771	1033	0	0
T4	49791	263	0	0
T7	48784	625	0	0
T8	6282	241	0	0
T9	5181	236	0	0
T10	74910	801	0	0
T11	4019	267	0	0
T12	539463	162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	867381	0	0
T1	12371	676	0	0
T2	514266	2302	0	0
T3	13771	1033	0	0
T4	49791	263	0	0
T7	48784	625	0	0
T8	6282	241	0	0
T9	5181	236	0	0
T10	74910	801	0	0
T11	4019	267	0	0
T12	539463	162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	2499864	0	0
T1	12371	826	0	0
T2	514266	4911	0	0
T3	13771	1323	0	0
T4	49791	294	0	0
T7	48784	1220	0	0
T8	6282	302	0	0
T9	5181	278	0	0
T10	74910	1305	0	0
T11	4019	349	0	0
T12	539463	242	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	867381	0	0
T1	12371	676	0	0
T2	514266	2302	0	0
T3	13771	1033	0	0
T4	49791	263	0	0
T7	48784	625	0	0
T8	6282	241	0	0
T9	5181	236	0	0
T10	74910	801	0	0
T11	4019	267	0	0
T12	539463	162	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	889441	0	0
GntImpliesValid_A	430116088	889441	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	889441	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	12157313	0	0
ReadyAndValidImplyGrant_A	430116088	889441	0	0
ReqAndReadyImplyGrant_A	430116088	889441	0	0
ReqImpliesValid_A	430116088	2584576	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	889441	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	889441	0	0
T1	12371	725	0	0
T2	514266	628	0	0
T3	13771	992	0	0
T4	49791	271	0	0
T7	48784	663	0	0
T8	6282	243	0	0
T9	5181	219	0	0
T10	74910	781	0	0
T11	4019	246	0	0
T12	539463	196	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	889441	0	0
T1	12371	725	0	0
T2	514266	628	0	0
T3	13771	992	0	0
T4	49791	271	0	0
T7	48784	663	0	0
T8	6282	243	0	0
T9	5181	219	0	0
T10	74910	781	0	0
T11	4019	246	0	0
T12	539463	196	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	889441	0	0
T1	12371	725	0	0
T2	514266	628	0	0
T3	13771	992	0	0
T4	49791	271	0	0
T7	48784	663	0	0
T8	6282	243	0	0
T9	5181	219	0	0
T10	74910	781	0	0
T11	4019	246	0	0
T12	539463	196	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	12157313	0	0
T1	12371	587	0	0
T2	514266	2562	0	0
T3	13771	725	0	0
T4	49791	2144	0	0
T7	48784	4406	0	0
T8	6282	185	0	0
T9	5181	183	0	0
T10	74910	5748	0	0
T11	4019	181	0	0
T12	539463	787	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	889441	0	0
T1	12371	725	0	0
T2	514266	628	0	0
T3	13771	992	0	0
T4	49791	271	0	0
T7	48784	663	0	0
T8	6282	243	0	0
T9	5181	219	0	0
T10	74910	781	0	0
T11	4019	246	0	0
T12	539463	196	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	889441	0	0
T1	12371	725	0	0
T2	514266	628	0	0
T3	13771	992	0	0
T4	49791	271	0	0
T7	48784	663	0	0
T8	6282	243	0	0
T9	5181	219	0	0
T10	74910	781	0	0
T11	4019	246	0	0
T12	539463	196	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	2584576	0	0
T1	12371	869	0	0
T2	514266	839	0	0
T3	13771	1260	0	0
T4	49791	299	0	0
T7	48784	1320	0	0
T8	6282	302	0	0
T9	5181	256	0	0
T10	74910	1227	0	0
T11	4019	312	0	0
T12	539463	276	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	889441	0	0
T1	12371	725	0	0
T2	514266	628	0	0
T3	13771	992	0	0
T4	49791	271	0	0
T7	48784	663	0	0
T8	6282	243	0	0
T9	5181	219	0	0
T10	74910	781	0	0
T11	4019	246	0	0
T12	539463	196	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	226479	0	0
GntImpliesValid_A	430116088	226479	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	226479	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3061278	0	0
ReadyAndValidImplyGrant_A	430116088	226479	0	0
ReqAndReadyImplyGrant_A	430116088	226479	0	0
ReqImpliesValid_A	430116088	589139	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	226479	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	226479	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	71	0	0
T7	48784	164	0	0
T8	6282	68	0	0
T9	5181	71	0	0
T10	74910	553	0	0
T11	4019	78	0	0
T12	539463	51	0	0
T13	0	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	226479	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	71	0	0
T7	48784	164	0	0
T8	6282	68	0	0
T9	5181	71	0	0
T10	74910	553	0	0
T11	4019	78	0	0
T12	539463	51	0	0
T13	0	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	226479	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	71	0	0
T7	48784	164	0	0
T8	6282	68	0	0
T9	5181	71	0	0
T10	74910	553	0	0
T11	4019	78	0	0
T12	539463	51	0	0
T13	0	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3061278	0	0
T1	12371	103	0	0
T2	514266	1	0	0
T3	13771	224	0	0
T4	49791	562	0	0
T7	48784	1262	0	0
T8	6282	66	0	0
T9	5181	72	0	0
T10	74910	1290	0	0
T11	4019	77	0	0
T12	539463	236	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	226479	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	71	0	0
T7	48784	164	0	0
T8	6282	68	0	0
T9	5181	71	0	0
T10	74910	553	0	0
T11	4019	78	0	0
T12	539463	51	0	0
T13	0	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	226479	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	71	0	0
T7	48784	164	0	0
T8	6282	68	0	0
T9	5181	71	0	0
T10	74910	553	0	0
T11	4019	78	0	0
T12	539463	51	0	0
T13	0	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	589139	0	0
T1	12371	98	0	0
T2	514266	0	0	0
T3	13771	251	0	0
T4	49791	98	0	0
T7	48784	239	0	0
T8	6282	71	0	0
T9	5181	71	0	0
T10	74910	2157	0	0
T11	4019	80	0	0
T12	539463	59	0	0
T13	0	132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	226479	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	71	0	0
T7	48784	164	0	0
T8	6282	68	0	0
T9	5181	71	0	0
T10	74910	553	0	0
T11	4019	78	0	0
T12	539463	51	0	0
T13	0	120	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T7
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T3,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	203115	0	0
GntImpliesValid_A	430116088	203115	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	203115	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	2943255	0	0
ReadyAndValidImplyGrant_A	430116088	203115	0	0
ReqAndReadyImplyGrant_A	430116088	203115	0	0
ReqImpliesValid_A	430116088	522250	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	203115	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	203115	0	0
T1	12371	89	0	0
T2	514266	0	0	0
T3	13771	219	0	0
T4	49791	70	0	0
T7	48784	139	0	0
T8	6282	56	0	0
T9	5181	61	0	0
T10	74910	495	0	0
T11	4019	70	0	0
T12	539463	45	0	0
T13	0	111	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	203115	0	0
T1	12371	89	0	0
T2	514266	0	0	0
T3	13771	219	0	0
T4	49791	70	0	0
T7	48784	139	0	0
T8	6282	56	0	0
T9	5181	61	0	0
T10	74910	495	0	0
T11	4019	70	0	0
T12	539463	45	0	0
T13	0	111	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	203115	0	0
T1	12371	89	0	0
T2	514266	0	0	0
T3	13771	219	0	0
T4	49791	70	0	0
T7	48784	139	0	0
T8	6282	56	0	0
T9	5181	61	0	0
T10	74910	495	0	0
T11	4019	70	0	0
T12	539463	45	0	0
T13	0	111	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	2943255	0	0
T1	12371	96	0	0
T2	514266	1	0	0
T3	13771	213	0	0
T4	49791	549	0	0
T7	48784	998	0	0
T8	6282	56	0	0
T9	5181	57	0	0
T10	74910	1181	0	0
T11	4019	65	0	0
T12	539463	209	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	203115	0	0
T1	12371	89	0	0
T2	514266	0	0	0
T3	13771	219	0	0
T4	49791	70	0	0
T7	48784	139	0	0
T8	6282	56	0	0
T9	5181	61	0	0
T10	74910	495	0	0
T11	4019	70	0	0
T12	539463	45	0	0
T13	0	111	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	203115	0	0
T1	12371	89	0	0
T2	514266	0	0	0
T3	13771	219	0	0
T4	49791	70	0	0
T7	48784	139	0	0
T8	6282	56	0	0
T9	5181	61	0	0
T10	74910	495	0	0
T11	4019	70	0	0
T12	539463	45	0	0
T13	0	111	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	522250	0	0
T1	12371	89	0	0
T2	514266	0	0	0
T3	13771	226	0	0
T4	49791	92	0	0
T7	48784	193	0	0
T8	6282	57	0	0
T9	5181	66	0	0
T10	74910	2208	0	0
T11	4019	76	0	0
T12	539463	48	0	0
T13	0	115	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	203115	0	0
T1	12371	89	0	0
T2	514266	0	0	0
T3	13771	219	0	0
T4	49791	70	0	0
T7	48784	139	0	0
T8	6282	56	0	0
T9	5181	61	0	0
T10	74910	495	0	0
T11	4019	70	0	0
T12	539463	45	0	0
T13	0	111	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	217855	0	0
GntImpliesValid_A	430116088	217855	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	217855	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	4923044	0	0
ReadyAndValidImplyGrant_A	430116088	217855	0	0
ReqAndReadyImplyGrant_A	430116088	217855	0	0
ReqImpliesValid_A	430116088	1189447	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	217855	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217855	0	0
T1	12371	312	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	61	0	0
T7	48784	174	0	0
T8	6282	56	0	0
T9	5181	54	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	41	0	0
T13	0	101	0	0
T14	0	168	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217855	0	0
T1	12371	312	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	61	0	0
T7	48784	174	0	0
T8	6282	56	0	0
T9	5181	54	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	41	0	0
T13	0	101	0	0
T14	0	168	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217855	0	0
T1	12371	312	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	61	0	0
T7	48784	174	0	0
T8	6282	56	0	0
T9	5181	54	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	41	0	0
T13	0	101	0	0
T14	0	168	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	4923044	0	0
T1	12371	1595	0	0
T2	514266	0	0	0
T3	13771	1045	0	0
T4	49791	1290	0	0
T7	48784	1854	0	0
T8	6282	345	0	0
T9	5181	201	0	0
T10	74910	0	0	0
T11	4019	276	0	0
T12	539463	712	0	0
T13	0	598	0	0
T14	0	2112	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217855	0	0
T1	12371	312	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	61	0	0
T7	48784	174	0	0
T8	6282	56	0	0
T9	5181	54	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	41	0	0
T13	0	101	0	0
T14	0	168	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217855	0	0
T1	12371	312	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	61	0	0
T7	48784	174	0	0
T8	6282	56	0	0
T9	5181	54	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	41	0	0
T13	0	101	0	0
T14	0	168	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	1189447	0	0
T1	12371	564	0	0
T2	514266	0	0	0
T3	13771	400	0	0
T4	49791	61	0	0
T7	48784	276	0	0
T8	6282	88	0	0
T9	5181	64	0	0
T10	74910	0	0	0
T11	4019	144	0	0
T12	539463	60	0	0
T13	0	179	0	0
T14	0	269	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217855	0	0
T1	12371	312	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	61	0	0
T7	48784	174	0	0
T8	6282	56	0	0
T9	5181	54	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	41	0	0
T13	0	101	0	0
T14	0	168	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	214375	0	0
GntImpliesValid_A	430116088	214375	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	214375	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	4925171	0	0
ReadyAndValidImplyGrant_A	430116088	214375	0	0
ReqAndReadyImplyGrant_A	430116088	214375	0	0
ReqImpliesValid_A	430116088	1161254	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	214375	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	214375	0	0
T1	12371	91	0	0
T2	514266	0	0	0
T3	13771	234	0	0
T4	49791	61	0	0
T7	48784	147	0	0
T8	6282	78	0	0
T9	5181	86	0	0
T10	74910	0	0	0
T11	4019	82	0	0
T12	539463	36	0	0
T13	0	99	0	0
T14	0	184	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	214375	0	0
T1	12371	91	0	0
T2	514266	0	0	0
T3	13771	234	0	0
T4	49791	61	0	0
T7	48784	147	0	0
T8	6282	78	0	0
T9	5181	86	0	0
T10	74910	0	0	0
T11	4019	82	0	0
T12	539463	36	0	0
T13	0	99	0	0
T14	0	184	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	214375	0	0
T1	12371	91	0	0
T2	514266	0	0	0
T3	13771	234	0	0
T4	49791	61	0	0
T7	48784	147	0	0
T8	6282	78	0	0
T9	5181	86	0	0
T10	74910	0	0	0
T11	4019	82	0	0
T12	539463	36	0	0
T13	0	99	0	0
T14	0	184	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	4925171	0	0
T1	12371	394	0	0
T2	514266	0	0	0
T3	13771	894	0	0
T4	49791	1214	0	0
T7	48784	1416	0	0
T8	6282	1067	0	0
T9	5181	291	0	0
T10	74910	0	0	0
T11	4019	493	0	0
T12	539463	274	0	0
T13	0	2647	0	0
T14	0	4406	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	214375	0	0
T1	12371	91	0	0
T2	514266	0	0	0
T3	13771	234	0	0
T4	49791	61	0	0
T7	48784	147	0	0
T8	6282	78	0	0
T9	5181	86	0	0
T10	74910	0	0	0
T11	4019	82	0	0
T12	539463	36	0	0
T13	0	99	0	0
T14	0	184	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	214375	0	0
T1	12371	91	0	0
T2	514266	0	0	0
T3	13771	234	0	0
T4	49791	61	0	0
T7	48784	147	0	0
T8	6282	78	0	0
T9	5181	86	0	0
T10	74910	0	0	0
T11	4019	82	0	0
T12	539463	36	0	0
T13	0	99	0	0
T14	0	184	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	1161254	0	0
T1	12371	103	0	0
T2	514266	0	0	0
T3	13771	331	0	0
T4	49791	68	0	0
T7	48784	281	0	0
T8	6282	336	0	0
T9	5181	135	0	0
T10	74910	0	0	0
T11	4019	167	0	0
T12	539463	56	0	0
T13	0	439	0	0
T14	0	472	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	214375	0	0
T1	12371	91	0	0
T2	514266	0	0	0
T3	13771	234	0	0
T4	49791	61	0	0
T7	48784	147	0	0
T8	6282	78	0	0
T9	5181	86	0	0
T10	74910	0	0	0
T11	4019	82	0	0
T12	539463	36	0	0
T13	0	99	0	0
T14	0	184	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	220842	0	0
GntImpliesValid_A	430116088	220842	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	220842	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	5883499	0	0
ReadyAndValidImplyGrant_A	430116088	220842	0	0
ReqAndReadyImplyGrant_A	430116088	220842	0	0
ReqImpliesValid_A	430116088	1377515	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	220842	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220842	0	0
T1	12371	95	0	0
T2	514266	1053	0	0
T3	13771	227	0	0
T4	49791	65	0	0
T7	48784	183	0	0
T8	6282	65	0	0
T9	5181	58	0	0
T10	74910	1036	0	0
T11	4019	60	0	0
T12	539463	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220842	0	0
T1	12371	95	0	0
T2	514266	1053	0	0
T3	13771	227	0	0
T4	49791	65	0	0
T7	48784	183	0	0
T8	6282	65	0	0
T9	5181	58	0	0
T10	74910	1036	0	0
T11	4019	60	0	0
T12	539463	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220842	0	0
T1	12371	95	0	0
T2	514266	1053	0	0
T3	13771	227	0	0
T4	49791	65	0	0
T7	48784	183	0	0
T8	6282	65	0	0
T9	5181	58	0	0
T10	74910	1036	0	0
T11	4019	60	0	0
T12	539463	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	5883499	0	0
T1	12371	415	0	0
T2	514266	5712	0	0
T3	13771	711	0	0
T4	49791	1399	0	0
T7	48784	1209	0	0
T8	6282	1182	0	0
T9	5181	300	0	0
T10	74910	2109	0	0
T11	4019	214	0	0
T12	539463	343	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220842	0	0
T1	12371	95	0	0
T2	514266	1053	0	0
T3	13771	227	0	0
T4	49791	65	0	0
T7	48784	183	0	0
T8	6282	65	0	0
T9	5181	58	0	0
T10	74910	1036	0	0
T11	4019	60	0	0
T12	539463	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220842	0	0
T1	12371	95	0	0
T2	514266	1053	0	0
T3	13771	227	0	0
T4	49791	65	0	0
T7	48784	183	0	0
T8	6282	65	0	0
T9	5181	58	0	0
T10	74910	1036	0	0
T11	4019	60	0	0
T12	539463	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	1377515	0	0
T1	12371	104	0	0
T2	514266	3212	0	0
T3	13771	306	0	0
T4	49791	65	0	0
T7	48784	253	0	0
T8	6282	256	0	0
T9	5181	80	0	0
T10	74910	4681	0	0
T11	4019	70	0	0
T12	539463	91	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220842	0	0
T1	12371	95	0	0
T2	514266	1053	0	0
T3	13771	227	0	0
T4	49791	65	0	0
T7	48784	183	0	0
T8	6282	65	0	0
T9	5181	58	0	0
T10	74910	1036	0	0
T11	4019	60	0	0
T12	539463	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	206005	0	0
GntImpliesValid_A	430116088	206005	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	206005	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	5449965	0	0
ReadyAndValidImplyGrant_A	430116088	206005	0	0
ReqAndReadyImplyGrant_A	430116088	206005	0	0
ReqImpliesValid_A	430116088	1164205	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	206005	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	206005	0	0
T1	12371	95	0	0
T2	514266	484	0	0
T3	13771	261	0	0
T4	49791	68	0	0
T7	48784	155	0	0
T8	6282	73	0	0
T9	5181	56	0	0
T10	74910	449	0	0
T11	4019	73	0	0
T12	539463	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	206005	0	0
T1	12371	95	0	0
T2	514266	484	0	0
T3	13771	261	0	0
T4	49791	68	0	0
T7	48784	155	0	0
T8	6282	73	0	0
T9	5181	56	0	0
T10	74910	449	0	0
T11	4019	73	0	0
T12	539463	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	206005	0	0
T1	12371	95	0	0
T2	514266	484	0	0
T3	13771	261	0	0
T4	49791	68	0	0
T7	48784	155	0	0
T8	6282	73	0	0
T9	5181	56	0	0
T10	74910	449	0	0
T11	4019	73	0	0
T12	539463	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	5449965	0	0
T1	12371	409	0	0
T2	514266	12025	0	0
T3	13771	794	0	0
T4	49791	5597	0	0
T7	48784	1298	0	0
T8	6282	385	0	0
T9	5181	271	0	0
T10	74910	1094	0	0
T11	4019	227	0	0
T12	539463	599	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	206005	0	0
T1	12371	95	0	0
T2	514266	484	0	0
T3	13771	261	0	0
T4	49791	68	0	0
T7	48784	155	0	0
T8	6282	73	0	0
T9	5181	56	0	0
T10	74910	449	0	0
T11	4019	73	0	0
T12	539463	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	206005	0	0
T1	12371	95	0	0
T2	514266	484	0	0
T3	13771	261	0	0
T4	49791	68	0	0
T7	48784	155	0	0
T8	6282	73	0	0
T9	5181	56	0	0
T10	74910	449	0	0
T11	4019	73	0	0
T12	539463	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	1164205	0	0
T1	12371	110	0	0
T2	514266	5341	0	0
T3	13771	376	0	0
T4	49791	352	0	0
T7	48784	216	0	0
T8	6282	111	0	0
T9	5181	61	0	0
T10	74910	1736	0	0
T11	4019	99	0	0
T12	539463	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	206005	0	0
T1	12371	95	0	0
T2	514266	484	0	0
T3	13771	261	0	0
T4	49791	68	0	0
T7	48784	155	0	0
T8	6282	73	0	0
T9	5181	56	0	0
T10	74910	449	0	0
T11	4019	73	0	0
T12	539463	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	219906	0	0
GntImpliesValid_A	430116088	219906	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	219906	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3046547	0	0
ReadyAndValidImplyGrant_A	430116088	219906	0	0
ReqAndReadyImplyGrant_A	430116088	219906	0	0
ReqImpliesValid_A	430116088	600121	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	219906	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219906	0	0
T1	12371	94	0	0
T2	514266	0	0	0
T3	13771	231	0	0
T4	49791	68	0	0
T7	48784	123	0	0
T8	6282	63	0	0
T9	5181	48	0	0
T10	74910	511	0	0
T11	4019	63	0	0
T12	539463	42	0	0
T13	0	104	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219906	0	0
T1	12371	94	0	0
T2	514266	0	0	0
T3	13771	231	0	0
T4	49791	68	0	0
T7	48784	123	0	0
T8	6282	63	0	0
T9	5181	48	0	0
T10	74910	511	0	0
T11	4019	63	0	0
T12	539463	42	0	0
T13	0	104	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219906	0	0
T1	12371	94	0	0
T2	514266	0	0	0
T3	13771	231	0	0
T4	49791	68	0	0
T7	48784	123	0	0
T8	6282	63	0	0
T9	5181	48	0	0
T10	74910	511	0	0
T11	4019	63	0	0
T12	539463	42	0	0
T13	0	104	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3046547	0	0
T1	12371	97	0	0
T2	514266	1	0	0
T3	13771	224	0	0
T4	49791	459	0	0
T7	48784	869	0	0
T8	6282	58	0	0
T9	5181	48	0	0
T10	74910	1099	0	0
T11	4019	61	0	0
T12	539463	168	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219906	0	0
T1	12371	94	0	0
T2	514266	0	0	0
T3	13771	231	0	0
T4	49791	68	0	0
T7	48784	123	0	0
T8	6282	63	0	0
T9	5181	48	0	0
T10	74910	511	0	0
T11	4019	63	0	0
T12	539463	42	0	0
T13	0	104	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219906	0	0
T1	12371	94	0	0
T2	514266	0	0	0
T3	13771	231	0	0
T4	49791	68	0	0
T7	48784	123	0	0
T8	6282	63	0	0
T9	5181	48	0	0
T10	74910	511	0	0
T11	4019	63	0	0
T12	539463	42	0	0
T13	0	104	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	600121	0	0
T1	12371	98	0	0
T2	514266	0	0	0
T3	13771	239	0	0
T4	49791	71	0	0
T7	48784	166	0	0
T8	6282	69	0	0
T9	5181	49	0	0
T10	74910	2142	0	0
T11	4019	66	0	0
T12	539463	46	0	0
T13	0	104	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219906	0	0
T1	12371	94	0	0
T2	514266	0	0	0
T3	13771	231	0	0
T4	49791	68	0	0
T7	48784	123	0	0
T8	6282	63	0	0
T9	5181	48	0	0
T10	74910	511	0	0
T11	4019	63	0	0
T12	539463	42	0	0
T13	0	104	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	231324	0	0
GntImpliesValid_A	430116088	231324	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	231324	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3123962	0	0
ReadyAndValidImplyGrant_A	430116088	231324	0	0
ReqAndReadyImplyGrant_A	430116088	231324	0	0
ReqImpliesValid_A	430116088	642440	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	231324	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	231324	0	0
T1	12371	91	0	0
T2	514266	528	0	0
T3	13771	263	0	0
T4	49791	80	0	0
T7	48784	154	0	0
T8	6282	71	0	0
T9	5181	56	0	0
T10	74910	0	0	0
T11	4019	69	0	0
T12	539463	52	0	0
T13	0	126	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	231324	0	0
T1	12371	91	0	0
T2	514266	528	0	0
T3	13771	263	0	0
T4	49791	80	0	0
T7	48784	154	0	0
T8	6282	71	0	0
T9	5181	56	0	0
T10	74910	0	0	0
T11	4019	69	0	0
T12	539463	52	0	0
T13	0	126	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	231324	0	0
T1	12371	91	0	0
T2	514266	528	0	0
T3	13771	263	0	0
T4	49791	80	0	0
T7	48784	154	0	0
T8	6282	71	0	0
T9	5181	56	0	0
T10	74910	0	0	0
T11	4019	69	0	0
T12	539463	52	0	0
T13	0	126	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3123962	0	0
T1	12371	95	0	0
T2	514266	1737	0	0
T3	13771	249	0	0
T4	49791	621	0	0
T7	48784	1094	0	0
T8	6282	71	0	0
T9	5181	57	0	0
T10	74910	1	0	0
T11	4019	66	0	0
T12	539463	212	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	231324	0	0
T1	12371	91	0	0
T2	514266	528	0	0
T3	13771	263	0	0
T4	49791	80	0	0
T7	48784	154	0	0
T8	6282	71	0	0
T9	5181	56	0	0
T10	74910	0	0	0
T11	4019	69	0	0
T12	539463	52	0	0
T13	0	126	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	231324	0	0
T1	12371	91	0	0
T2	514266	528	0	0
T3	13771	263	0	0
T4	49791	80	0	0
T7	48784	154	0	0
T8	6282	71	0	0
T9	5181	56	0	0
T10	74910	0	0	0
T11	4019	69	0	0
T12	539463	52	0	0
T13	0	126	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	642440	0	0
T1	12371	94	0	0
T2	514266	1181	0	0
T3	13771	278	0	0
T4	49791	80	0	0
T7	48784	201	0	0
T8	6282	72	0	0
T9	5181	56	0	0
T10	74910	0	0	0
T11	4019	73	0	0
T12	539463	65	0	0
T13	0	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	231324	0	0
T1	12371	91	0	0
T2	514266	528	0	0
T3	13771	263	0	0
T4	49791	80	0	0
T7	48784	154	0	0
T8	6282	71	0	0
T9	5181	56	0	0
T10	74910	0	0	0
T11	4019	69	0	0
T12	539463	52	0	0
T13	0	126	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	220051	0	0
GntImpliesValid_A	430116088	220051	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	220051	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3078218	0	0
ReadyAndValidImplyGrant_A	430116088	220051	0	0
ReqAndReadyImplyGrant_A	430116088	220051	0	0
ReqImpliesValid_A	430116088	560205	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	220051	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220051	0	0
T1	12371	107	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	72	0	0
T7	48784	165	0	0
T8	6282	62	0	0
T9	5181	68	0	0
T10	74910	557	0	0
T11	4019	78	0	0
T12	539463	32	0	0
T13	0	129	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220051	0	0
T1	12371	107	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	72	0	0
T7	48784	165	0	0
T8	6282	62	0	0
T9	5181	68	0	0
T10	74910	557	0	0
T11	4019	78	0	0
T12	539463	32	0	0
T13	0	129	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220051	0	0
T1	12371	107	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	72	0	0
T7	48784	165	0	0
T8	6282	62	0	0
T9	5181	68	0	0
T10	74910	557	0	0
T11	4019	78	0	0
T12	539463	32	0	0
T13	0	129	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3078218	0	0
T1	12371	109	0	0
T2	514266	1	0	0
T3	13771	223	0	0
T4	49791	537	0	0
T7	48784	1095	0	0
T8	6282	61	0	0
T9	5181	65	0	0
T10	74910	1180	0	0
T11	4019	73	0	0
T12	539463	150	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220051	0	0
T1	12371	107	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	72	0	0
T7	48784	165	0	0
T8	6282	62	0	0
T9	5181	68	0	0
T10	74910	557	0	0
T11	4019	78	0	0
T12	539463	32	0	0
T13	0	129	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220051	0	0
T1	12371	107	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	72	0	0
T7	48784	165	0	0
T8	6282	62	0	0
T9	5181	68	0	0
T10	74910	557	0	0
T11	4019	78	0	0
T12	539463	32	0	0
T13	0	129	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	560205	0	0
T1	12371	112	0	0
T2	514266	0	0	0
T3	13771	252	0	0
T4	49791	72	0	0
T7	48784	202	0	0
T8	6282	64	0	0
T9	5181	72	0	0
T10	74910	5056	0	0
T11	4019	84	0	0
T12	539463	34	0	0
T13	0	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	220051	0	0
T1	12371	107	0	0
T2	514266	0	0	0
T3	13771	237	0	0
T4	49791	72	0	0
T7	48784	165	0	0
T8	6282	62	0	0
T9	5181	68	0	0
T10	74910	557	0	0
T11	4019	78	0	0
T12	539463	32	0	0
T13	0	129	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	227746	0	0
GntImpliesValid_A	430116088	227746	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	227746	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3026096	0	0
ReadyAndValidImplyGrant_A	430116088	227746	0	0
ReqAndReadyImplyGrant_A	430116088	227746	0	0
ReqImpliesValid_A	430116088	619831	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	227746	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	227746	0	0
T1	12371	101	0	0
T2	514266	910	0	0
T3	13771	244	0	0
T4	49791	68	0	0
T7	48784	158	0	0
T8	6282	56	0	0
T9	5181	69	0	0
T10	74910	487	0	0
T11	4019	71	0	0
T12	539463	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	227746	0	0
T1	12371	101	0	0
T2	514266	910	0	0
T3	13771	244	0	0
T4	49791	68	0	0
T7	48784	158	0	0
T8	6282	56	0	0
T9	5181	69	0	0
T10	74910	487	0	0
T11	4019	71	0	0
T12	539463	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	227746	0	0
T1	12371	101	0	0
T2	514266	910	0	0
T3	13771	244	0	0
T4	49791	68	0	0
T7	48784	158	0	0
T8	6282	56	0	0
T9	5181	69	0	0
T10	74910	487	0	0
T11	4019	71	0	0
T12	539463	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3026096	0	0
T1	12371	106	0	0
T2	514266	2907	0	0
T3	13771	230	0	0
T4	49791	541	0	0
T7	48784	1191	0	0
T8	6282	55	0	0
T9	5181	69	0	0
T10	74910	1174	0	0
T11	4019	68	0	0
T12	539463	176	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	227746	0	0
T1	12371	101	0	0
T2	514266	910	0	0
T3	13771	244	0	0
T4	49791	68	0	0
T7	48784	158	0	0
T8	6282	56	0	0
T9	5181	69	0	0
T10	74910	487	0	0
T11	4019	71	0	0
T12	539463	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	227746	0	0
T1	12371	101	0	0
T2	514266	910	0	0
T3	13771	244	0	0
T4	49791	68	0	0
T7	48784	158	0	0
T8	6282	56	0	0
T9	5181	69	0	0
T10	74910	487	0	0
T11	4019	71	0	0
T12	539463	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	619831	0	0
T1	12371	103	0	0
T2	514266	2359	0	0
T3	13771	259	0	0
T4	49791	68	0	0
T7	48784	185	0	0
T8	6282	58	0	0
T9	5181	70	0	0
T10	74910	4194	0	0
T11	4019	75	0	0
T12	539463	47	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	227746	0	0
T1	12371	101	0	0
T2	514266	910	0	0
T3	13771	244	0	0
T4	49791	68	0	0
T7	48784	158	0	0
T8	6282	56	0	0
T9	5181	69	0	0
T10	74910	487	0	0
T11	4019	71	0	0
T12	539463	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	208261	0	0
GntImpliesValid_A	430116088	208261	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	208261	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	2990840	0	0
ReadyAndValidImplyGrant_A	430116088	208261	0	0
ReqAndReadyImplyGrant_A	430116088	208261	0	0
ReqImpliesValid_A	430116088	549076	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	208261	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	208261	0	0
T1	12371	475	0	0
T2	514266	0	0	0
T3	13771	270	0	0
T4	49791	80	0	0
T7	48784	168	0	0
T8	6282	64	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	41	0	0
T13	0	108	0	0
T14	0	182	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	208261	0	0
T1	12371	475	0	0
T2	514266	0	0	0
T3	13771	270	0	0
T4	49791	80	0	0
T7	48784	168	0	0
T8	6282	64	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	41	0	0
T13	0	108	0	0
T14	0	182	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	208261	0	0
T1	12371	475	0	0
T2	514266	0	0	0
T3	13771	270	0	0
T4	49791	80	0	0
T7	48784	168	0	0
T8	6282	64	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	41	0	0
T13	0	108	0	0
T14	0	182	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	2990840	0	0
T1	12371	240	0	0
T2	514266	1	0	0
T3	13771	250	0	0
T4	49791	592	0	0
T7	48784	1230	0	0
T8	6282	60	0	0
T9	5181	59	0	0
T10	74910	1	0	0
T11	4019	66	0	0
T12	539463	158	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	208261	0	0
T1	12371	475	0	0
T2	514266	0	0	0
T3	13771	270	0	0
T4	49791	80	0	0
T7	48784	168	0	0
T8	6282	64	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	41	0	0
T13	0	108	0	0
T14	0	182	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	208261	0	0
T1	12371	475	0	0
T2	514266	0	0	0
T3	13771	270	0	0
T4	49791	80	0	0
T7	48784	168	0	0
T8	6282	64	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	41	0	0
T13	0	108	0	0
T14	0	182	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	549076	0	0
T1	12371	716	0	0
T2	514266	0	0	0
T3	13771	291	0	0
T4	49791	80	0	0
T7	48784	234	0	0
T8	6282	69	0	0
T9	5181	66	0	0
T10	74910	0	0	0
T11	4019	71	0	0
T12	539463	51	0	0
T13	0	113	0	0
T14	0	261	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	208261	0	0
T1	12371	475	0	0
T2	514266	0	0	0
T3	13771	270	0	0
T4	49791	80	0	0
T7	48784	168	0	0
T8	6282	64	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	41	0	0
T13	0	108	0	0
T14	0	182	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	224182	0	0
GntImpliesValid_A	430116088	224182	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	224182	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3083451	0	0
ReadyAndValidImplyGrant_A	430116088	224182	0	0
ReqAndReadyImplyGrant_A	430116088	224182	0	0
ReqImpliesValid_A	430116088	616979	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	224182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	224182	0	0
T1	12371	488	0	0
T2	514266	0	0	0
T3	13771	250	0	0
T4	49791	63	0	0
T7	48784	159	0	0
T8	6282	62	0	0
T9	5181	63	0	0
T10	74910	490	0	0
T11	4019	55	0	0
T12	539463	49	0	0
T13	0	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	224182	0	0
T1	12371	488	0	0
T2	514266	0	0	0
T3	13771	250	0	0
T4	49791	63	0	0
T7	48784	159	0	0
T8	6282	62	0	0
T9	5181	63	0	0
T10	74910	490	0	0
T11	4019	55	0	0
T12	539463	49	0	0
T13	0	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	224182	0	0
T1	12371	488	0	0
T2	514266	0	0	0
T3	13771	250	0	0
T4	49791	63	0	0
T7	48784	159	0	0
T8	6282	62	0	0
T9	5181	63	0	0
T10	74910	490	0	0
T11	4019	55	0	0
T12	539463	49	0	0
T13	0	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3083451	0	0
T1	12371	361	0	0
T2	514266	1	0	0
T3	13771	239	0	0
T4	49791	429	0	0
T7	48784	1249	0	0
T8	6282	62	0	0
T9	5181	63	0	0
T10	74910	1293	0	0
T11	4019	51	0	0
T12	539463	190	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	224182	0	0
T1	12371	488	0	0
T2	514266	0	0	0
T3	13771	250	0	0
T4	49791	63	0	0
T7	48784	159	0	0
T8	6282	62	0	0
T9	5181	63	0	0
T10	74910	490	0	0
T11	4019	55	0	0
T12	539463	49	0	0
T13	0	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	224182	0	0
T1	12371	488	0	0
T2	514266	0	0	0
T3	13771	250	0	0
T4	49791	63	0	0
T7	48784	159	0	0
T8	6282	62	0	0
T9	5181	63	0	0
T10	74910	490	0	0
T11	4019	55	0	0
T12	539463	49	0	0
T13	0	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	616979	0	0
T1	12371	621	0	0
T2	514266	0	0	0
T3	13771	262	0	0
T4	49791	63	0	0
T7	48784	256	0	0
T8	6282	63	0	0
T9	5181	64	0	0
T10	74910	4132	0	0
T11	4019	60	0	0
T12	539463	55	0	0
T13	0	120	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	224182	0	0
T1	12371	488	0	0
T2	514266	0	0	0
T3	13771	250	0	0
T4	49791	63	0	0
T7	48784	159	0	0
T8	6282	62	0	0
T9	5181	63	0	0
T10	74910	490	0	0
T11	4019	55	0	0
T12	539463	49	0	0
T13	0	116	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	222531	0	0
GntImpliesValid_A	430116088	222531	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	222531	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	2973963	0	0
ReadyAndValidImplyGrant_A	430116088	222531	0	0
ReqAndReadyImplyGrant_A	430116088	222531	0	0
ReqImpliesValid_A	430116088	574190	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	222531	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	222531	0	0
T1	12371	649	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	62	0	0
T7	48784	154	0	0
T8	6282	60	0	0
T9	5181	68	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	38	0	0
T13	0	113	0	0
T14	0	170	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	222531	0	0
T1	12371	649	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	62	0	0
T7	48784	154	0	0
T8	6282	60	0	0
T9	5181	68	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	38	0	0
T13	0	113	0	0
T14	0	170	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	222531	0	0
T1	12371	649	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	62	0	0
T7	48784	154	0	0
T8	6282	60	0	0
T9	5181	68	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	38	0	0
T13	0	113	0	0
T14	0	170	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	2973963	0	0
T1	12371	443	0	0
T2	514266	1	0	0
T3	13771	228	0	0
T4	49791	516	0	0
T7	48784	1177	0	0
T8	6282	57	0	0
T9	5181	66	0	0
T10	74910	1	0	0
T11	4019	72	0	0
T12	539463	157	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	222531	0	0
T1	12371	649	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	62	0	0
T7	48784	154	0	0
T8	6282	60	0	0
T9	5181	68	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	38	0	0
T13	0	113	0	0
T14	0	170	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	222531	0	0
T1	12371	649	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	62	0	0
T7	48784	154	0	0
T8	6282	60	0	0
T9	5181	68	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	38	0	0
T13	0	113	0	0
T14	0	170	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	574190	0	0
T1	12371	862	0	0
T2	514266	0	0	0
T3	13771	259	0	0
T4	49791	62	0	0
T7	48784	243	0	0
T8	6282	64	0	0
T9	5181	71	0	0
T10	74910	0	0	0
T11	4019	83	0	0
T12	539463	52	0	0
T13	0	121	0	0
T14	0	246	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	222531	0	0
T1	12371	649	0	0
T2	514266	0	0	0
T3	13771	243	0	0
T4	49791	62	0	0
T7	48784	154	0	0
T8	6282	60	0	0
T9	5181	68	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	38	0	0
T13	0	113	0	0
T14	0	170	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	219337	0	0
GntImpliesValid_A	430116088	219337	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	219337	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3018068	0	0
ReadyAndValidImplyGrant_A	430116088	219337	0	0
ReqAndReadyImplyGrant_A	430116088	219337	0	0
ReqImpliesValid_A	430116088	585569	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	219337	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219337	0	0
T1	12371	105	0	0
T2	514266	518	0	0
T3	13771	253	0	0
T4	49791	66	0	0
T7	48784	193	0	0
T8	6282	53	0	0
T9	5181	49	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	49	0	0
T13	0	117	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219337	0	0
T1	12371	105	0	0
T2	514266	518	0	0
T3	13771	253	0	0
T4	49791	66	0	0
T7	48784	193	0	0
T8	6282	53	0	0
T9	5181	49	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	49	0	0
T13	0	117	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219337	0	0
T1	12371	105	0	0
T2	514266	518	0	0
T3	13771	253	0	0
T4	49791	66	0	0
T7	48784	193	0	0
T8	6282	53	0	0
T9	5181	49	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	49	0	0
T13	0	117	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3018068	0	0
T1	12371	109	0	0
T2	514266	1791	0	0
T3	13771	240	0	0
T4	49791	487	0	0
T7	48784	1460	0	0
T8	6282	54	0	0
T9	5181	48	0	0
T10	74910	1	0	0
T11	4019	67	0	0
T12	539463	228	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219337	0	0
T1	12371	105	0	0
T2	514266	518	0	0
T3	13771	253	0	0
T4	49791	66	0	0
T7	48784	193	0	0
T8	6282	53	0	0
T9	5181	49	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	49	0	0
T13	0	117	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219337	0	0
T1	12371	105	0	0
T2	514266	518	0	0
T3	13771	253	0	0
T4	49791	66	0	0
T7	48784	193	0	0
T8	6282	53	0	0
T9	5181	49	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	49	0	0
T13	0	117	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	585569	0	0
T1	12371	108	0	0
T2	514266	1144	0	0
T3	13771	267	0	0
T4	49791	68	0	0
T7	48784	287	0	0
T8	6282	53	0	0
T9	5181	51	0	0
T10	74910	0	0	0
T11	4019	70	0	0
T12	539463	55	0	0
T13	0	123	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219337	0	0
T1	12371	105	0	0
T2	514266	518	0	0
T3	13771	253	0	0
T4	49791	66	0	0
T7	48784	193	0	0
T8	6282	53	0	0
T9	5181	49	0	0
T10	74910	0	0	0
T11	4019	68	0	0
T12	539463	49	0	0
T13	0	117	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	228787	0	0
GntImpliesValid_A	430116088	228787	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	228787	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3098734	0	0
ReadyAndValidImplyGrant_A	430116088	228787	0	0
ReqAndReadyImplyGrant_A	430116088	228787	0	0
ReqImpliesValid_A	430116088	591379	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	228787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	228787	0	0
T1	12371	106	0	0
T2	514266	571	0	0
T3	13771	232	0	0
T4	49791	67	0	0
T7	48784	154	0	0
T8	6282	70	0	0
T9	5181	96	0	0
T10	74910	0	0	0
T11	4019	64	0	0
T12	539463	55	0	0
T13	0	102	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	228787	0	0
T1	12371	106	0	0
T2	514266	571	0	0
T3	13771	232	0	0
T4	49791	67	0	0
T7	48784	154	0	0
T8	6282	70	0	0
T9	5181	96	0	0
T10	74910	0	0	0
T11	4019	64	0	0
T12	539463	55	0	0
T13	0	102	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	228787	0	0
T1	12371	106	0	0
T2	514266	571	0	0
T3	13771	232	0	0
T4	49791	67	0	0
T7	48784	154	0	0
T8	6282	70	0	0
T9	5181	96	0	0
T10	74910	0	0	0
T11	4019	64	0	0
T12	539463	55	0	0
T13	0	102	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3098734	0	0
T1	12371	112	0	0
T2	514266	1797	0	0
T3	13771	215	0	0
T4	49791	527	0	0
T7	48784	1095	0	0
T8	6282	64	0	0
T9	5181	93	0	0
T10	74910	1	0	0
T11	4019	59	0	0
T12	539463	207	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	228787	0	0
T1	12371	106	0	0
T2	514266	571	0	0
T3	13771	232	0	0
T4	49791	67	0	0
T7	48784	154	0	0
T8	6282	70	0	0
T9	5181	96	0	0
T10	74910	0	0	0
T11	4019	64	0	0
T12	539463	55	0	0
T13	0	102	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	228787	0	0
T1	12371	106	0	0
T2	514266	571	0	0
T3	13771	232	0	0
T4	49791	67	0	0
T7	48784	154	0	0
T8	6282	70	0	0
T9	5181	96	0	0
T10	74910	0	0	0
T11	4019	64	0	0
T12	539463	55	0	0
T13	0	102	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	591379	0	0
T1	12371	107	0	0
T2	514266	1327	0	0
T3	13771	250	0	0
T4	49791	73	0	0
T7	48784	232	0	0
T8	6282	77	0	0
T9	5181	100	0	0
T10	74910	0	0	0
T11	4019	70	0	0
T12	539463	63	0	0
T13	0	105	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	228787	0	0
T1	12371	106	0	0
T2	514266	571	0	0
T3	13771	232	0	0
T4	49791	67	0	0
T7	48784	154	0	0
T8	6282	70	0	0
T9	5181	96	0	0
T10	74910	0	0	0
T11	4019	64	0	0
T12	539463	55	0	0
T13	0	102	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	219257	0	0
GntImpliesValid_A	430116088	219257	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	219257	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	2995606	0	0
ReadyAndValidImplyGrant_A	430116088	219257	0	0
ReqAndReadyImplyGrant_A	430116088	219257	0	0
ReqImpliesValid_A	430116088	585857	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	219257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219257	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	271	0	0
T4	49791	67	0	0
T7	48784	133	0	0
T8	6282	68	0	0
T9	5181	59	0	0
T10	74910	1579	0	0
T11	4019	73	0	0
T12	539463	44	0	0
T13	0	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219257	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	271	0	0
T4	49791	67	0	0
T7	48784	133	0	0
T8	6282	68	0	0
T9	5181	59	0	0
T10	74910	1579	0	0
T11	4019	73	0	0
T12	539463	44	0	0
T13	0	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219257	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	271	0	0
T4	49791	67	0	0
T7	48784	133	0	0
T8	6282	68	0	0
T9	5181	59	0	0
T10	74910	1579	0	0
T11	4019	73	0	0
T12	539463	44	0	0
T13	0	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	2995606	0	0
T1	12371	103	0	0
T2	514266	1	0	0
T3	13771	247	0	0
T4	49791	498	0	0
T7	48784	1097	0	0
T8	6282	64	0	0
T9	5181	55	0	0
T10	74910	3714	0	0
T11	4019	73	0	0
T12	539463	162	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219257	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	271	0	0
T4	49791	67	0	0
T7	48784	133	0	0
T8	6282	68	0	0
T9	5181	59	0	0
T10	74910	1579	0	0
T11	4019	73	0	0
T12	539463	44	0	0
T13	0	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219257	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	271	0	0
T4	49791	67	0	0
T7	48784	133	0	0
T8	6282	68	0	0
T9	5181	59	0	0
T10	74910	1579	0	0
T11	4019	73	0	0
T12	539463	44	0	0
T13	0	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	585857	0	0
T1	12371	98	0	0
T2	514266	0	0	0
T3	13771	296	0	0
T4	49791	67	0	0
T7	48784	178	0	0
T8	6282	73	0	0
T9	5181	64	0	0
T10	74910	13969	0	0
T11	4019	74	0	0
T12	539463	47	0	0
T13	0	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	219257	0	0
T1	12371	97	0	0
T2	514266	0	0	0
T3	13771	271	0	0
T4	49791	67	0	0
T7	48784	133	0	0
T8	6282	68	0	0
T9	5181	59	0	0
T10	74910	1579	0	0
T11	4019	73	0	0
T12	539463	44	0	0
T13	0	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	209849	0	0
GntImpliesValid_A	430116088	209849	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	209849	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	2962242	0	0
ReadyAndValidImplyGrant_A	430116088	209849	0	0
ReqAndReadyImplyGrant_A	430116088	209849	0	0
ReqImpliesValid_A	430116088	539786	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	209849	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	209849	0	0
T1	12371	86	0	0
T2	514266	456	0	0
T3	13771	319	0	0
T4	49791	64	0	0
T7	48784	131	0	0
T8	6282	74	0	0
T9	5181	59	0	0
T10	74910	0	0	0
T11	4019	52	0	0
T12	539463	54	0	0
T13	0	125	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	209849	0	0
T1	12371	86	0	0
T2	514266	456	0	0
T3	13771	319	0	0
T4	49791	64	0	0
T7	48784	131	0	0
T8	6282	74	0	0
T9	5181	59	0	0
T10	74910	0	0	0
T11	4019	52	0	0
T12	539463	54	0	0
T13	0	125	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	209849	0	0
T1	12371	86	0	0
T2	514266	456	0	0
T3	13771	319	0	0
T4	49791	64	0	0
T7	48784	131	0	0
T8	6282	74	0	0
T9	5181	59	0	0
T10	74910	0	0	0
T11	4019	52	0	0
T12	539463	54	0	0
T13	0	125	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	2962242	0	0
T1	12371	91	0	0
T2	514266	1482	0	0
T3	13771	295	0	0
T4	49791	530	0	0
T7	48784	1022	0	0
T8	6282	69	0	0
T9	5181	56	0	0
T10	74910	1	0	0
T11	4019	49	0	0
T12	539463	199	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	209849	0	0
T1	12371	86	0	0
T2	514266	456	0	0
T3	13771	319	0	0
T4	49791	64	0	0
T7	48784	131	0	0
T8	6282	74	0	0
T9	5181	59	0	0
T10	74910	0	0	0
T11	4019	52	0	0
T12	539463	54	0	0
T13	0	125	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	209849	0	0
T1	12371	86	0	0
T2	514266	456	0	0
T3	13771	319	0	0
T4	49791	64	0	0
T7	48784	131	0	0
T8	6282	74	0	0
T9	5181	59	0	0
T10	74910	0	0	0
T11	4019	52	0	0
T12	539463	54	0	0
T13	0	125	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	539786	0	0
T1	12371	88	0	0
T2	514266	1198	0	0
T3	13771	344	0	0
T4	49791	64	0	0
T7	48784	187	0	0
T8	6282	80	0	0
T9	5181	63	0	0
T10	74910	0	0	0
T11	4019	56	0	0
T12	539463	74	0	0
T13	0	130	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	209849	0	0
T1	12371	86	0	0
T2	514266	456	0	0
T3	13771	319	0	0
T4	49791	64	0	0
T7	48784	131	0	0
T8	6282	74	0	0
T9	5181	59	0	0
T10	74910	0	0	0
T11	4019	52	0	0
T12	539463	54	0	0
T13	0	125	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	211686	0	0
GntImpliesValid_A	430116088	211686	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	211686	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3029263	0	0
ReadyAndValidImplyGrant_A	430116088	211686	0	0
ReqAndReadyImplyGrant_A	430116088	211686	0	0
ReqImpliesValid_A	430116088	577912	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	211686	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	211686	0	0
T1	12371	84	0	0
T2	514266	512	0	0
T3	13771	258	0	0
T4	49791	75	0	0
T7	48784	137	0	0
T8	6282	59	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	79	0	0
T12	539463	46	0	0
T13	0	114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	211686	0	0
T1	12371	84	0	0
T2	514266	512	0	0
T3	13771	258	0	0
T4	49791	75	0	0
T7	48784	137	0	0
T8	6282	59	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	79	0	0
T12	539463	46	0	0
T13	0	114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	211686	0	0
T1	12371	84	0	0
T2	514266	512	0	0
T3	13771	258	0	0
T4	49791	75	0	0
T7	48784	137	0	0
T8	6282	59	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	79	0	0
T12	539463	46	0	0
T13	0	114	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3029263	0	0
T1	12371	89	0	0
T2	514266	1699	0	0
T3	13771	244	0	0
T4	49791	581	0	0
T7	48784	983	0	0
T8	6282	57	0	0
T9	5181	62	0	0
T10	74910	1	0	0
T11	4019	72	0	0
T12	539463	151	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	211686	0	0
T1	12371	84	0	0
T2	514266	512	0	0
T3	13771	258	0	0
T4	49791	75	0	0
T7	48784	137	0	0
T8	6282	59	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	79	0	0
T12	539463	46	0	0
T13	0	114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	211686	0	0
T1	12371	84	0	0
T2	514266	512	0	0
T3	13771	258	0	0
T4	49791	75	0	0
T7	48784	137	0	0
T8	6282	59	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	79	0	0
T12	539463	46	0	0
T13	0	114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	577912	0	0
T1	12371	86	0	0
T2	514266	1234	0	0
T3	13771	273	0	0
T4	49791	75	0	0
T7	48784	187	0	0
T8	6282	62	0	0
T9	5181	63	0	0
T10	74910	0	0	0
T11	4019	87	0	0
T12	539463	51	0	0
T13	0	121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	211686	0	0
T1	12371	84	0	0
T2	514266	512	0	0
T3	13771	258	0	0
T4	49791	75	0	0
T7	48784	137	0	0
T8	6282	59	0	0
T9	5181	62	0	0
T10	74910	0	0	0
T11	4019	79	0	0
T12	539463	46	0	0
T13	0	114	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	223651	0	0
GntImpliesValid_A	430116088	223651	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	223651	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3057471	0	0
ReadyAndValidImplyGrant_A	430116088	223651	0	0
ReqAndReadyImplyGrant_A	430116088	223651	0	0
ReqImpliesValid_A	430116088	583488	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	223651	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	223651	0	0
T1	12371	113	0	0
T2	514266	444	0	0
T3	13771	239	0	0
T4	49791	53	0	0
T7	48784	152	0	0
T8	6282	53	0	0
T9	5181	61	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	45	0	0
T13	0	93	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	223651	0	0
T1	12371	113	0	0
T2	514266	444	0	0
T3	13771	239	0	0
T4	49791	53	0	0
T7	48784	152	0	0
T8	6282	53	0	0
T9	5181	61	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	45	0	0
T13	0	93	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	223651	0	0
T1	12371	113	0	0
T2	514266	444	0	0
T3	13771	239	0	0
T4	49791	53	0	0
T7	48784	152	0	0
T8	6282	53	0	0
T9	5181	61	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	45	0	0
T13	0	93	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3057471	0	0
T1	12371	119	0	0
T2	514266	1449	0	0
T3	13771	226	0	0
T4	49791	396	0	0
T7	48784	1170	0	0
T8	6282	53	0	0
T9	5181	62	0	0
T10	74910	1	0	0
T11	4019	75	0	0
T12	539463	156	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	223651	0	0
T1	12371	113	0	0
T2	514266	444	0	0
T3	13771	239	0	0
T4	49791	53	0	0
T7	48784	152	0	0
T8	6282	53	0	0
T9	5181	61	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	45	0	0
T13	0	93	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	223651	0	0
T1	12371	113	0	0
T2	514266	444	0	0
T3	13771	239	0	0
T4	49791	53	0	0
T7	48784	152	0	0
T8	6282	53	0	0
T9	5181	61	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	45	0	0
T13	0	93	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	583488	0	0
T1	12371	114	0	0
T2	514266	1155	0	0
T3	13771	253	0	0
T4	49791	53	0	0
T7	48784	235	0	0
T8	6282	54	0	0
T9	5181	61	0	0
T10	74910	0	0	0
T11	4019	80	0	0
T12	539463	55	0	0
T13	0	94	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	223651	0	0
T1	12371	113	0	0
T2	514266	444	0	0
T3	13771	239	0	0
T4	49791	53	0	0
T7	48784	152	0	0
T8	6282	53	0	0
T9	5181	61	0	0
T10	74910	0	0	0
T11	4019	77	0	0
T12	539463	45	0	0
T13	0	93	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	217271	0	0
GntImpliesValid_A	430116088	217271	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	217271	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	3027527	0	0
ReadyAndValidImplyGrant_A	430116088	217271	0	0
ReqAndReadyImplyGrant_A	430116088	217271	0	0
ReqImpliesValid_A	430116088	594896	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	0	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	217271	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217271	0	0
T1	12371	93	0	0
T2	514266	0	0	0
T3	13771	235	0	0
T4	49791	57	0	0
T7	48784	152	0	0
T8	6282	63	0	0
T9	5181	63	0	0
T10	74910	0	0	0
T11	4019	71	0	0
T12	539463	57	0	0
T13	0	100	0	0
T14	0	159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217271	0	0
T1	12371	93	0	0
T2	514266	0	0	0
T3	13771	235	0	0
T4	49791	57	0	0
T7	48784	152	0	0
T8	6282	63	0	0
T9	5181	63	0	0
T10	74910	0	0	0
T11	4019	71	0	0
T12	539463	57	0	0
T13	0	100	0	0
T14	0	159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217271	0	0
T1	12371	93	0	0
T2	514266	0	0	0
T3	13771	235	0	0
T4	49791	57	0	0
T7	48784	152	0	0
T8	6282	63	0	0
T9	5181	63	0	0
T10	74910	0	0	0
T11	4019	71	0	0
T12	539463	57	0	0
T13	0	100	0	0
T14	0	159	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	3027527	0	0
T1	12371	99	0	0
T2	514266	1	0	0
T3	13771	226	0	0
T4	49791	454	0	0
T7	48784	1106	0	0
T8	6282	61	0	0
T9	5181	62	0	0
T10	74910	1	0	0
T11	4019	68	0	0
T12	539463	235	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217271	0	0
T1	12371	93	0	0
T2	514266	0	0	0
T3	13771	235	0	0
T4	49791	57	0	0
T7	48784	152	0	0
T8	6282	63	0	0
T9	5181	63	0	0
T10	74910	0	0	0
T11	4019	71	0	0
T12	539463	57	0	0
T13	0	100	0	0
T14	0	159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217271	0	0
T1	12371	93	0	0
T2	514266	0	0	0
T3	13771	235	0	0
T4	49791	57	0	0
T7	48784	152	0	0
T8	6282	63	0	0
T9	5181	63	0	0
T10	74910	0	0	0
T11	4019	71	0	0
T12	539463	57	0	0
T13	0	100	0	0
T14	0	159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	594896	0	0
T1	12371	94	0	0
T2	514266	0	0	0
T3	13771	245	0	0
T4	49791	57	0	0
T7	48784	199	0	0
T8	6282	66	0	0
T9	5181	65	0	0
T10	74910	0	0	0
T11	4019	75	0	0
T12	539463	73	0	0
T13	0	107	0	0
T14	0	199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	217271	0	0
T1	12371	93	0	0
T2	514266	0	0	0
T3	13771	235	0	0
T4	49791	57	0	0
T7	48784	152	0	0
T8	6282	63	0	0
T9	5181	63	0	0
T10	74910	0	0	0
T11	4019	71	0	0
T12	539463	57	0	0
T13	0	100	0	0
T14	0	159	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	883577	0	0
GntImpliesValid_A	430116088	883577	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	883577	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	11772468	0	0
ReadyAndValidImplyGrant_A	430116088	883577	0	0
ReqAndReadyImplyGrant_A	430116088	883577	0	0
ReqImpliesValid_A	430116088	2390855	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	17625	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	883577	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	883577	0	0
T1	12371	860	0	0
T2	514266	1339	0	0
T3	13771	1055	0	0
T4	49791	230	0	0
T7	48784	699	0	0
T8	6282	244	0	0
T9	5181	222	0	0
T10	74910	780	0	0
T11	4019	251	0	0
T12	539463	183	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	883577	0	0
T1	12371	860	0	0
T2	514266	1339	0	0
T3	13771	1055	0	0
T4	49791	230	0	0
T7	48784	699	0	0
T8	6282	244	0	0
T9	5181	222	0	0
T10	74910	780	0	0
T11	4019	251	0	0
T12	539463	183	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	883577	0	0
T1	12371	860	0	0
T2	514266	1339	0	0
T3	13771	1055	0	0
T4	49791	230	0	0
T7	48784	699	0	0
T8	6282	244	0	0
T9	5181	222	0	0
T10	74910	780	0	0
T11	4019	251	0	0
T12	539463	183	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	11772468	0	0
T1	12371	7	0	0
T2	514266	3764	0	0
T3	13771	1	0	0
T4	49791	1545	0	0
T7	48784	4092	0	0
T8	6282	1	0	0
T9	5181	1	0	0
T10	74910	5214	0	0
T11	4019	1	0	0
T12	539463	605	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	883577	0	0
T1	12371	860	0	0
T2	514266	1339	0	0
T3	13771	1055	0	0
T4	49791	230	0	0
T7	48784	699	0	0
T8	6282	244	0	0
T9	5181	222	0	0
T10	74910	780	0	0
T11	4019	251	0	0
T12	539463	183	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	883577	0	0
T1	12371	860	0	0
T2	514266	1339	0	0
T3	13771	1055	0	0
T4	49791	230	0	0
T7	48784	699	0	0
T8	6282	244	0	0
T9	5181	222	0	0
T10	74910	780	0	0
T11	4019	251	0	0
T12	539463	183	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	2390855	0	0
T1	12371	860	0	0
T2	514266	2555	0	0
T3	13771	1055	0	0
T4	49791	244	0	0
T7	48784	1224	0	0
T8	6282	244	0	0
T9	5181	222	0	0
T10	74910	1263	0	0
T11	4019	251	0	0
T12	539463	239	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	17625	0	900
T1	12371	107	0	1
T2	514266	5	0	1
T3	13771	23	0	1
T4	49791	0	0	1
T7	48784	0	0	1
T8	6282	2	0	1
T9	5181	1	0	1
T10	74910	0	0	1
T11	4019	2	0	1
T12	539463	0	0	1
T13	0	3	0	0
T17	0	35	0	0
T18	0	5	0	0
T19	0	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	883577	0	0
T1	12371	860	0	0
T2	514266	1339	0	0
T3	13771	1055	0	0
T4	49791	230	0	0
T7	48784	699	0	0
T8	6282	244	0	0
T9	5181	222	0	0
T10	74910	780	0	0
T11	4019	251	0	0
T12	539463	183	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430116088	429995823	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430116088	872711	0	0
GntImpliesValid_A	430116088	872711	0	0
GrantKnown_A	430116088	429995823	0	0
IdxKnown_A	430116088	429995823	0	0
IndexIsCorrect_A	430116088	872711	0	0
LockArbDecision_A	430116088	0	0	0
NoReadyValidNoGrant_A	430116088	361265140	0	0
ReadyAndValidImplyGrant_A	430116088	872711	0	0
ReqAndReadyImplyGrant_A	430116088	872711	0	0
ReqImpliesValid_A	430116088	13615729	0	0
ReqStaysHighUntilGranted0_M	430116088	0	0	0
RoundRobin_A	430116088	27072	0	900
ValidKnown_A	430116088	429995823	0	0
gen_data_port_assertion.DataFlow_A	430116088	872711	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	872711	0	0
T1	12371	655	0	0
T2	514266	662	0	0
T3	13771	961	0	0
T4	49791	244	0	0
T7	48784	693	0	0
T8	6282	244	0	0
T9	5181	239	0	0
T10	74910	761	0	0
T11	4019	276	0	0
T12	539463	187	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	872711	0	0
T1	12371	655	0	0
T2	514266	662	0	0
T3	13771	961	0	0
T4	49791	244	0	0
T7	48784	693	0	0
T8	6282	244	0	0
T9	5181	239	0	0
T10	74910	761	0	0
T11	4019	276	0	0
T12	539463	187	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	872711	0	0
T1	12371	655	0	0
T2	514266	662	0	0
T3	13771	961	0	0
T4	49791	244	0	0
T7	48784	693	0	0
T8	6282	244	0	0
T9	5181	239	0	0
T10	74910	761	0	0
T11	4019	276	0	0
T12	539463	187	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	361265140	0	0
T1	12371	1	0	0
T2	514266	428279	0	0
T3	13771	1	0	0
T4	49791	43466	0	0
T7	48784	38154	0	0
T8	6282	1	0	0
T9	5181	1	0	0
T10	74910	61349	0	0
T11	4019	1	0	0
T12	539463	449003	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	872711	0	0
T1	12371	655	0	0
T2	514266	662	0	0
T3	13771	961	0	0
T4	49791	244	0	0
T7	48784	693	0	0
T8	6282	244	0	0
T9	5181	239	0	0
T10	74910	761	0	0
T11	4019	276	0	0
T12	539463	187	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	872711	0	0
T1	12371	655	0	0
T2	514266	662	0	0
T3	13771	961	0	0
T4	49791	244	0	0
T7	48784	693	0	0
T8	6282	244	0	0
T9	5181	239	0	0
T10	74910	761	0	0
T11	4019	276	0	0
T12	539463	187	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	13615729	0	0
T1	12371	655	0	0
T2	514266	2816	0	0
T3	13771	961	0	0
T4	49791	1969	0	0
T7	48784	4941	0	0
T8	6282	244	0	0
T9	5181	239	0	0
T10	74910	5501	0	0
T11	4019	276	0	0
T12	539463	810	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	27072	0	900
T1	12371	9	0	1
T2	514266	0	0	1
T3	13771	23	0	1
T4	49791	0	0	1
T7	48784	3	0	1
T8	6282	4	0	1
T9	5181	9	0	1
T10	74910	0	0	1
T11	4019	5	0	1
T12	539463	0	0	1
T13	0	6	0	0
T14	0	3	0	0
T15	0	27	0	0
T16	0	482	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	429995823	0	0
T1	12371	11930	0	0
T2	514266	514261	0	0
T3	13771	13763	0	0
T4	49791	49737	0	0
T7	48784	48767	0	0
T8	6282	6195	0	0
T9	5181	5156	0	0
T10	74910	74901	0	0
T11	4019	4003	0	0
T12	539463	539392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430116088	872711	0	0
T1	12371	655	0	0
T2	514266	662	0	0
T3	13771	961	0	0
T4	49791	244	0	0
T7	48784	693	0	0
T8	6282	244	0	0
T9	5181	239	0	0
T10	74910	761	0	0
T11	4019	276	0	0
T12	539463	187	0	0