Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1405611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

223909

1

T1

16

T2

29

T3

98

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	554417	1			T1	39		T2	66		T3	248
values[0x0]	520295	1			T1	28		T2	60		T3	251
values[0x1]	554808	1			T1	33		T2	67		T3	247

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1085376	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

544144

1

T1

29

T2

72

T3

239

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24681	1			T1	3		T2	10		T3	8
valid_sources[0x01]	26258	1			T1	1		T3	13		T7	3
valid_sources[0x02]	25548	1			T3	17		T7	5		T8	30
valid_sources[0x03]	25456	1			T2	11		T3	10		T7	2
valid_sources[0x04]	25625	1			T1	4		T2	2		T3	8
valid_sources[0x05]	26177	1			T2	2		T3	18		T7	1
valid_sources[0x06]	25813	1			T1	1		T3	19		T8	12
valid_sources[0x07]	25396	1			T1	4		T2	1		T3	14
valid_sources[0x08]	25848	1			T1	3		T3	17		T7	5
valid_sources[0x09]	24680	1			T1	1		T2	8		T3	12
valid_sources[0x0a]	25281	1			T1	2		T2	3		T3	11
valid_sources[0x0b]	24306	1			T1	4		T2	8		T3	14
valid_sources[0x0c]	25679	1			T1	1		T2	1		T3	10
valid_sources[0x0d]	25287	1			T2	3		T3	6		T7	4
valid_sources[0x0e]	25831	1			T1	1		T2	2		T3	13
valid_sources[0x0f]	25197	1			T1	4		T3	18		T8	30
valid_sources[0x10]	25452	1			T2	8		T3	8		T7	3
valid_sources[0x11]	25500	1			T1	4		T2	1		T3	16
valid_sources[0x12]	25467	1			T2	6		T3	9		T8	36
valid_sources[0x13]	26262	1			T2	11		T3	11		T8	58
valid_sources[0x14]	25888	1			T2	6		T3	13		T7	3
valid_sources[0x15]	25782	1			T3	15		T8	71		T9	21
valid_sources[0x16]	25485	1			T2	2		T3	9		T7	2
valid_sources[0x17]	25296	1			T2	9		T3	7		T8	28
valid_sources[0x18]	25905	1			T1	4		T3	9		T7	1
valid_sources[0x19]	25435	1			T3	19		T8	29		T11	218
valid_sources[0x1a]	24937	1			T1	1		T3	13		T8	47
valid_sources[0x1b]	25398	1			T1	3		T2	1		T3	9
valid_sources[0x1c]	25680	1			T1	3		T2	1		T3	6
valid_sources[0x1d]	24954	1			T1	2		T3	17		T7	3
valid_sources[0x1e]	24891	1			T3	13		T7	2		T8	35
valid_sources[0x1f]	24941	1			T1	3		T3	17		T8	20
valid_sources[0x20]	26521	1			T1	1		T2	12		T3	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23779

1

T1

2

T2

2

T3

9

values[0x0]

all_enables

biggest_size

176220

1

T1

12

T2

25

T3

81

values[0x1]

all_enables

biggest_size

23910

1

T1

2

T2

2

T3

8

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1421271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

230318

1

T1

28

T2

21

T3

91

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	567170	1			T1	48		T2	58		T3	238
values[0x0]	516908	1			T1	53		T2	54		T3	211
values[0x1]	567511	1			T1	61		T2	52		T3	227

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1089309	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

562280

1

T1

64

T2

56

T3

228

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25265	1			T1	5		T3	13		T7	1
valid_sources[0x01]	25941	1			T1	6		T3	21		T7	2
valid_sources[0x02]	26146	1			T3	3		T7	1		T8	20
valid_sources[0x03]	25667	1			T1	3		T2	7		T7	3
valid_sources[0x04]	25891	1			T3	4		T7	5		T8	25
valid_sources[0x05]	25861	1			T3	18		T7	1		T8	24
valid_sources[0x06]	25814	1			T1	3		T2	1		T3	22
valid_sources[0x07]	24826	1			T2	2		T3	14		T7	1
valid_sources[0x08]	25536	1			T3	15		T7	4		T8	19
valid_sources[0x09]	25360	1			T1	3		T2	2		T3	4
valid_sources[0x0a]	26083	1			T2	3		T3	11		T7	3
valid_sources[0x0b]	25731	1			T1	2		T2	5		T3	7
valid_sources[0x0c]	26036	1			T1	7		T2	2		T3	26
valid_sources[0x0d]	25499	1			T1	1		T2	9		T3	3
valid_sources[0x0e]	26145	1			T1	7		T2	8		T3	40
valid_sources[0x0f]	26125	1			T1	9		T2	2		T3	3
valid_sources[0x10]	26171	1			T2	4		T3	1		T7	2
valid_sources[0x11]	26151	1			T1	1		T3	7		T7	2
valid_sources[0x12]	25394	1			T1	1		T2	12		T3	43
valid_sources[0x13]	25818	1			T2	3		T7	2		T8	25
valid_sources[0x14]	26235	1			T1	3		T2	2		T3	8
valid_sources[0x15]	25807	1			T3	3		T8	33		T9	1
valid_sources[0x16]	25599	1			T2	8		T7	5		T8	35
valid_sources[0x17]	25899	1			T3	2		T8	23		T9	2
valid_sources[0x18]	26403	1			T1	8		T2	2		T3	25
valid_sources[0x19]	26235	1			T1	6		T3	21		T7	4
valid_sources[0x1a]	26121	1			T2	3		T3	10		T7	5
valid_sources[0x1b]	26174	1			T2	1		T7	3		T8	23
valid_sources[0x1c]	25939	1			T3	4		T7	2		T8	29
valid_sources[0x1d]	25803	1			T2	8		T3	1		T7	4
valid_sources[0x1e]	25082	1			T1	8		T3	3		T7	3
valid_sources[0x1f]	25211	1			T1	8		T2	3		T3	14
valid_sources[0x20]	26456	1			T1	1		T3	17		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24539

1

T1

3

T2

1

T3

8

values[0x0]

all_enables

biggest_size

181090

1

T1

22

T2

18

T3

74

values[0x1]

all_enables

biggest_size

24689

1

T1

3

T2

2

T3

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1417468	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

224850

1

T1

24

T2

20

T3

105

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	559062	1			T1	62		T2	50		T3	281
values[0x0]	524117	1			T1	55		T2	52		T3	248
values[0x1]	559139	1			T1	56		T2	48		T3	275

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1094499	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

547819

1

T1

55

T2

44

T3

250

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25164	1			T1	2		T2	3		T3	18
valid_sources[0x01]	25512	1			T1	8		T2	5		T3	9
valid_sources[0x02]	25892	1			T1	2		T2	3		T3	15
valid_sources[0x03]	25782	1			T1	1		T2	1		T3	9
valid_sources[0x04]	25790	1			T1	4		T2	2		T3	9
valid_sources[0x05]	25429	1			T1	1		T2	1		T3	12
valid_sources[0x06]	25716	1			T1	2		T2	3		T3	14
valid_sources[0x07]	26106	1			T1	3		T2	1		T3	11
valid_sources[0x08]	25874	1			T2	2		T3	12		T7	1
valid_sources[0x09]	25347	1			T1	2		T2	2		T3	20
valid_sources[0x0a]	25075	1			T1	10		T2	3		T3	10
valid_sources[0x0b]	26195	1			T1	6		T3	15		T7	6
valid_sources[0x0c]	24791	1			T1	3		T2	1		T3	15
valid_sources[0x0d]	24871	1			T1	4		T2	4		T3	12
valid_sources[0x0e]	25628	1			T1	3		T2	1		T3	10
valid_sources[0x0f]	26574	1			T1	1		T2	5		T3	11
valid_sources[0x10]	25908	1			T1	2		T2	5		T3	13
valid_sources[0x11]	25883	1			T2	1		T3	9		T7	1
valid_sources[0x12]	25971	1			T1	1		T2	3		T3	16
valid_sources[0x13]	25205	1			T2	2		T3	7		T7	1
valid_sources[0x14]	25772	1			T1	1		T2	1		T3	11
valid_sources[0x15]	25706	1			T1	3		T2	2		T3	14
valid_sources[0x16]	25819	1			T1	2		T2	4		T3	10
valid_sources[0x17]	25624	1			T2	6		T3	22		T7	3
valid_sources[0x18]	27001	1			T1	4		T2	2		T3	12
valid_sources[0x19]	25837	1			T1	4		T2	2		T3	11
valid_sources[0x1a]	26137	1			T1	9		T2	4		T3	7
valid_sources[0x1b]	25788	1			T2	1		T3	13		T7	3
valid_sources[0x1c]	26105	1			T1	1		T2	1		T3	18
valid_sources[0x1d]	25176	1			T1	2		T2	1		T3	7
valid_sources[0x1e]	25044	1			T1	4		T2	1		T3	13
valid_sources[0x1f]	24551	1			T2	3		T3	12		T8	27
valid_sources[0x20]	25925	1			T2	4		T3	13		T8	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23873

1

T1

3

T2

2

T3

9

values[0x0]

all_enables

biggest_size

177014

1

T1

18

T2

17

T3

81

values[0x1]

all_enables

biggest_size

23963

1

T1

3

T2

1

T3

15