Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21576	21576	0	0
GntImpliesReady_A	2147483647	7890065	0	0
GntImpliesValid_A	2147483647	7890065	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7890065	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	430072378	0	0
ReadyAndValidImplyGrant_A	2147483647	7890065	0	0
ReqAndReadyImplyGrant_A	2147483647	7890065	0	0
ReqImpliesValid_A	2147483647	32944518	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46954	0	21576
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7890065	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10660152	10659360	0	0
T2	7689168	7688232	0	0
T3	2530248	2530176	0	0
T7	48600	47544	0	0
T8	258120	256920	0	0
T9	57504	56592	0	0
T10	143544	143328	0	0
T11	6520920	6510120	0	0
T12	8321664	8319696	0	0
T13	18348576	18346992	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21576	21576	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7890065	0	0
T1	10660152	435	0	0
T2	7689168	507	0	0
T3	2530248	2226	0	0
T7	48600	452	0	0
T8	258120	4981	0	0
T9	57504	453	0	0
T10	143544	3904	0	0
T11	6520920	31380	0	0
T12	8321664	529	0	0
T13	18348576	2347	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7890065	0	0
T1	10660152	435	0	0
T2	7689168	507	0	0
T3	2530248	2226	0	0
T7	48600	452	0	0
T8	258120	4981	0	0
T9	57504	453	0	0
T10	143544	3904	0	0
T11	6520920	31380	0	0
T12	8321664	529	0	0
T13	18348576	2347	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10660152	10659360	0	0
T2	7689168	7688232	0	0
T3	2530248	2530176	0	0
T7	48600	47544	0	0
T8	258120	256920	0	0
T9	57504	56592	0	0
T10	143544	143328	0	0
T11	6520920	6510120	0	0
T12	8321664	8319696	0	0
T13	18348576	18346992	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10660152	10659360	0	0
T2	7689168	7688232	0	0
T3	2530248	2530176	0	0
T7	48600	47544	0	0
T8	258120	256920	0	0
T9	57504	56592	0	0
T10	143544	143328	0	0
T11	6520920	6510120	0	0
T12	8321664	8319696	0	0
T13	18348576	18346992	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7890065	0	0
T1	10660152	435	0	0
T2	7689168	507	0	0
T3	2530248	2226	0	0
T7	48600	452	0	0
T8	258120	4981	0	0
T9	57504	453	0	0
T10	143544	3904	0	0
T11	6520920	31380	0	0
T12	8321664	529	0	0
T13	18348576	2347	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	430072378	0	0
T1	10660152	544328	0	0
T2	7689168	268693	0	0
T3	2530248	1710541	0	0
T7	48600	544	0	0
T8	258120	7763	0	0
T9	57504	769	0	0
T10	143544	3951	0	0
T11	6520920	380739	0	0
T12	8321664	291273	0	0
T13	18348576	647003	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7890065	0	0
T1	10660152	435	0	0
T2	7689168	507	0	0
T3	2530248	2226	0	0
T7	48600	452	0	0
T8	258120	4981	0	0
T9	57504	453	0	0
T10	143544	3904	0	0
T11	6520920	31380	0	0
T12	8321664	529	0	0
T13	18348576	2347	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7890065	0	0
T1	10660152	435	0	0
T2	7689168	507	0	0
T3	2530248	2226	0	0
T7	48600	452	0	0
T8	258120	4981	0	0
T9	57504	453	0	0
T10	143544	3904	0	0
T11	6520920	31380	0	0
T12	8321664	529	0	0
T13	18348576	2347	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32944518	0	0
T1	10660152	23821	0	0
T2	7689168	880	0	0
T3	2530248	150008	0	0
T7	48600	500	0	0
T8	258120	5859	0	0
T9	57504	529	0	0
T10	143544	4426	0	0
T11	6520920	125726	0	0
T12	8321664	920	0	0
T13	18348576	4048	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46954	0	21576
T4	0	576	0	0
T5	0	6	0	0
T8	21510	12	0	2
T9	4792	0	0	2
T10	11962	21	0	2
T11	543410	16	0	2
T12	693472	0	0	2
T13	1529048	0	0	2
T14	656076	20	0	2
T15	91886	2	0	2
T16	0	10	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	0	229	0	0
T20	0	13	0	0
T21	126274	0	0	2
T22	572182	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10660152	10659360	0	0
T2	7689168	7688232	0	0
T3	2530248	2530176	0	0
T7	48600	47544	0	0
T8	258120	256920	0	0
T9	57504	56592	0	0
T10	143544	143328	0	0
T11	6520920	6510120	0	0
T12	8321664	8319696	0	0
T13	18348576	18346992	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7890065	0	0
T1	10660152	435	0	0
T2	7689168	507	0	0
T3	2530248	2226	0	0
T7	48600	452	0	0
T8	258120	4981	0	0
T9	57504	453	0	0
T10	143544	3904	0	0
T11	6520920	31380	0	0
T12	8321664	529	0	0
T13	18348576	2347	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	873368	0	0
GntImpliesValid_A	394935464	873368	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	873368	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	11555449	0	0
ReadyAndValidImplyGrant_A	394935464	873368	0	0
ReqAndReadyImplyGrant_A	394935464	873368	0	0
ReqImpliesValid_A	394935464	2366423	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	873368	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	873368	0	0
T1	444173	51	0	0
T2	320382	49	0	0
T3	105427	221	0	0
T7	2025	45	0	0
T8	10755	551	0	0
T9	2396	41	0	0
T10	5981	431	0	0
T11	271705	3117	0	0
T12	346736	55	0	0
T13	764524	293	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	873368	0	0
T1	444173	51	0	0
T2	320382	49	0	0
T3	105427	221	0	0
T7	2025	45	0	0
T8	10755	551	0	0
T9	2396	41	0	0
T10	5981	431	0	0
T11	271705	3117	0	0
T12	346736	55	0	0
T13	764524	293	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	873368	0	0
T1	444173	51	0	0
T2	320382	49	0	0
T3	105427	221	0	0
T7	2025	45	0	0
T8	10755	551	0	0
T9	2396	41	0	0
T10	5981	431	0	0
T11	271705	3117	0	0
T12	346736	55	0	0
T13	764524	293	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	11555449	0	0
T1	444173	13901	0	0
T2	320382	204	0	0
T3	105427	73029	0	0
T7	2025	37	0	0
T8	10755	415	0	0
T9	2396	33	0	0
T10	5981	323	0	0
T11	271705	23161	0	0
T12	346736	243	0	0
T13	764524	1152	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	873368	0	0
T1	444173	51	0	0
T2	320382	49	0	0
T3	105427	221	0	0
T7	2025	45	0	0
T8	10755	551	0	0
T9	2396	41	0	0
T10	5981	431	0	0
T11	271705	3117	0	0
T12	346736	55	0	0
T13	764524	293	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	873368	0	0
T1	444173	51	0	0
T2	320382	49	0	0
T3	105427	221	0	0
T7	2025	45	0	0
T8	10755	551	0	0
T9	2396	41	0	0
T10	5981	431	0	0
T11	271705	3117	0	0
T12	346736	55	0	0
T13	764524	293	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2366423	0	0
T1	444173	517	0	0
T2	320382	77	0	0
T3	105427	7442	0	0
T7	2025	54	0	0
T8	10755	688	0	0
T9	2396	50	0	0
T10	5981	540	0	0
T11	271705	5516	0	0
T12	346736	76	0	0
T13	764524	430	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	873368	0	0
T1	444173	51	0	0
T2	320382	49	0	0
T3	105427	221	0	0
T7	2025	45	0	0
T8	10755	551	0	0
T9	2396	41	0	0
T10	5981	431	0	0
T11	271705	3117	0	0
T12	346736	55	0	0
T13	764524	293	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	865340	0	0
GntImpliesValid_A	394935464	865340	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	865340	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	11451794	0	0
ReadyAndValidImplyGrant_A	394935464	865340	0	0
ReqAndReadyImplyGrant_A	394935464	865340	0	0
ReqImpliesValid_A	394935464	2301227	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	865340	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	865340	0	0
T1	444173	48	0	0
T2	320382	66	0	0
T3	105427	225	0	0
T7	2025	55	0	0
T8	10755	508	0	0
T9	2396	50	0	0
T10	5981	395	0	0
T11	271705	3656	0	0
T12	346736	59	0	0
T13	764524	234	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	865340	0	0
T1	444173	48	0	0
T2	320382	66	0	0
T3	105427	225	0	0
T7	2025	55	0	0
T8	10755	508	0	0
T9	2396	50	0	0
T10	5981	395	0	0
T11	271705	3656	0	0
T12	346736	59	0	0
T13	764524	234	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	865340	0	0
T1	444173	48	0	0
T2	320382	66	0	0
T3	105427	225	0	0
T7	2025	55	0	0
T8	10755	508	0	0
T9	2396	50	0	0
T10	5981	395	0	0
T11	271705	3656	0	0
T12	346736	59	0	0
T13	764524	234	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	11451794	0	0
T1	444173	15475	0	0
T2	320382	247	0	0
T3	105427	72543	0	0
T7	2025	45	0	0
T8	10755	376	0	0
T9	2396	44	0	0
T10	5981	309	0	0
T11	271705	21366	0	0
T12	346736	213	0	0
T13	764524	984	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	865340	0	0
T1	444173	48	0	0
T2	320382	66	0	0
T3	105427	225	0	0
T7	2025	55	0	0
T8	10755	508	0	0
T9	2396	50	0	0
T10	5981	395	0	0
T11	271705	3656	0	0
T12	346736	59	0	0
T13	764524	234	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	865340	0	0
T1	444173	48	0	0
T2	320382	66	0	0
T3	105427	225	0	0
T7	2025	55	0	0
T8	10755	508	0	0
T9	2396	50	0	0
T10	5981	395	0	0
T11	271705	3656	0	0
T12	346736	59	0	0
T13	764524	234	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2301227	0	0
T1	444173	255	0	0
T2	320382	91	0	0
T3	105427	6229	0	0
T7	2025	66	0	0
T8	10755	641	0	0
T9	2396	57	0	0
T10	5981	482	0	0
T11	271705	7943	0	0
T12	346736	83	0	0
T13	764524	297	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	865340	0	0
T1	444173	48	0	0
T2	320382	66	0	0
T3	105427	225	0	0
T7	2025	55	0	0
T8	10755	508	0	0
T9	2396	50	0	0
T10	5981	395	0	0
T11	271705	3656	0	0
T12	346736	59	0	0
T13	764524	234	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	219339	0	0
GntImpliesValid_A	394935464	219339	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	219339	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2873091	0	0
ReadyAndValidImplyGrant_A	394935464	219339	0	0
ReqAndReadyImplyGrant_A	394935464	219339	0	0
ReqImpliesValid_A	394935464	549090	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	219339	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	219339	0	0
T1	444173	8	0	0
T2	320382	13	0	0
T3	105427	62	0	0
T7	2025	21	0	0
T8	10755	169	0	0
T9	2396	16	0	0
T10	5981	107	0	0
T11	271705	482	0	0
T12	346736	16	0	0
T13	764524	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	219339	0	0
T1	444173	8	0	0
T2	320382	13	0	0
T3	105427	62	0	0
T7	2025	21	0	0
T8	10755	169	0	0
T9	2396	16	0	0
T10	5981	107	0	0
T11	271705	482	0	0
T12	346736	16	0	0
T13	764524	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	219339	0	0
T1	444173	8	0	0
T2	320382	13	0	0
T3	105427	62	0	0
T7	2025	21	0	0
T8	10755	169	0	0
T9	2396	16	0	0
T10	5981	107	0	0
T11	271705	482	0	0
T12	346736	16	0	0
T13	764524	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2873091	0	0
T1	444173	2762	0	0
T2	320382	35	0	0
T3	105427	22030	0	0
T7	2025	22	0	0
T8	10755	166	0	0
T9	2396	16	0	0
T10	5981	101	0	0
T11	271705	3521	0	0
T12	346736	79	0	0
T13	764524	285	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	219339	0	0
T1	444173	8	0	0
T2	320382	13	0	0
T3	105427	62	0	0
T7	2025	21	0	0
T8	10755	169	0	0
T9	2396	16	0	0
T10	5981	107	0	0
T11	271705	482	0	0
T12	346736	16	0	0
T13	764524	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	219339	0	0
T1	444173	8	0	0
T2	320382	13	0	0
T3	105427	62	0	0
T7	2025	21	0	0
T8	10755	169	0	0
T9	2396	16	0	0
T10	5981	107	0	0
T11	271705	482	0	0
T12	346736	16	0	0
T13	764524	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	549090	0	0
T1	444173	8	0	0
T2	320382	13	0	0
T3	105427	2406	0	0
T7	2025	21	0	0
T8	10755	173	0	0
T9	2396	17	0	0
T10	5981	114	0	0
T11	271705	641	0	0
T12	346736	16	0	0
T13	764524	71	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	219339	0	0
T1	444173	8	0	0
T2	320382	13	0	0
T3	105427	62	0	0
T7	2025	21	0	0
T8	10755	169	0	0
T9	2396	16	0	0
T10	5981	107	0	0
T11	271705	482	0	0
T12	346736	16	0	0
T13	764524	65	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	214804	0	0
GntImpliesValid_A	394935464	214804	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	214804	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2845615	0	0
ReadyAndValidImplyGrant_A	394935464	214804	0	0
ReqAndReadyImplyGrant_A	394935464	214804	0	0
ReqImpliesValid_A	394935464	529660	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	214804	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214804	0	0
T1	444173	17	0	0
T2	320382	14	0	0
T3	105427	57	0	0
T7	2025	14	0	0
T8	10755	123	0	0
T9	2396	9	0	0
T10	5981	105	0	0
T11	271705	513	0	0
T12	346736	11	0	0
T13	764524	69	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214804	0	0
T1	444173	17	0	0
T2	320382	14	0	0
T3	105427	57	0	0
T7	2025	14	0	0
T8	10755	123	0	0
T9	2396	9	0	0
T10	5981	105	0	0
T11	271705	513	0	0
T12	346736	11	0	0
T13	764524	69	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214804	0	0
T1	444173	17	0	0
T2	320382	14	0	0
T3	105427	57	0	0
T7	2025	14	0	0
T8	10755	123	0	0
T9	2396	9	0	0
T10	5981	105	0	0
T11	271705	513	0	0
T12	346736	11	0	0
T13	764524	69	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2845615	0	0
T1	444173	5911	0	0
T2	320382	47	0	0
T3	105427	18550	0	0
T7	2025	15	0	0
T8	10755	121	0	0
T9	2396	10	0	0
T10	5981	103	0	0
T11	271705	3864	0	0
T12	346736	66	0	0
T13	764524	320	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214804	0	0
T1	444173	17	0	0
T2	320382	14	0	0
T3	105427	57	0	0
T7	2025	14	0	0
T8	10755	123	0	0
T9	2396	9	0	0
T10	5981	105	0	0
T11	271705	513	0	0
T12	346736	11	0	0
T13	764524	69	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214804	0	0
T1	444173	17	0	0
T2	320382	14	0	0
T3	105427	57	0	0
T7	2025	14	0	0
T8	10755	123	0	0
T9	2396	9	0	0
T10	5981	105	0	0
T11	271705	513	0	0
T12	346736	11	0	0
T13	764524	69	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	529660	0	0
T1	444173	977	0	0
T2	320382	31	0	0
T3	105427	780	0	0
T7	2025	14	0	0
T8	10755	126	0	0
T9	2396	9	0	0
T10	5981	108	0	0
T11	271705	643	0	0
T12	346736	14	0	0
T13	764524	79	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214804	0	0
T1	444173	17	0	0
T2	320382	14	0	0
T3	105427	57	0	0
T7	2025	14	0	0
T8	10755	123	0	0
T9	2396	9	0	0
T10	5981	105	0	0
T11	271705	513	0	0
T12	346736	11	0	0
T13	764524	69	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	218542	0	0
GntImpliesValid_A	394935464	218542	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	218542	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	5204528	0	0
ReadyAndValidImplyGrant_A	394935464	218542	0	0
ReqAndReadyImplyGrant_A	394935464	218542	0	0
ReqImpliesValid_A	394935464	1242452	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	218542	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218542	0	0
T1	444173	11	0	0
T2	320382	14	0	0
T3	105427	68	0	0
T7	2025	10	0	0
T8	10755	116	0	0
T9	2396	10	0	0
T10	5981	119	0	0
T11	271705	1004	0	0
T12	346736	16	0	0
T13	764524	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218542	0	0
T1	444173	11	0	0
T2	320382	14	0	0
T3	105427	68	0	0
T7	2025	10	0	0
T8	10755	116	0	0
T9	2396	10	0	0
T10	5981	119	0	0
T11	271705	1004	0	0
T12	346736	16	0	0
T13	764524	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218542	0	0
T1	444173	11	0	0
T2	320382	14	0	0
T3	105427	68	0	0
T7	2025	10	0	0
T8	10755	116	0	0
T9	2396	10	0	0
T10	5981	119	0	0
T11	271705	1004	0	0
T12	346736	16	0	0
T13	764524	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	5204528	0	0
T1	444173	2667	0	0
T2	320382	97	0	0
T3	105427	24369	0	0
T7	2025	97	0	0
T8	10755	1626	0	0
T9	2396	54	0	0
T10	5981	443	0	0
T11	271705	4831	0	0
T12	346736	155	0	0
T13	764524	1590	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218542	0	0
T1	444173	11	0	0
T2	320382	14	0	0
T3	105427	68	0	0
T7	2025	10	0	0
T8	10755	116	0	0
T9	2396	10	0	0
T10	5981	119	0	0
T11	271705	1004	0	0
T12	346736	16	0	0
T13	764524	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218542	0	0
T1	444173	11	0	0
T2	320382	14	0	0
T3	105427	68	0	0
T7	2025	10	0	0
T8	10755	116	0	0
T9	2396	10	0	0
T10	5981	119	0	0
T11	271705	1004	0	0
T12	346736	16	0	0
T13	764524	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	1242452	0	0
T1	444173	11	0	0
T2	320382	14	0	0
T3	105427	716	0	0
T7	2025	10	0	0
T8	10755	228	0	0
T9	2396	14	0	0
T10	5981	163	0	0
T11	271705	4793	0	0
T12	346736	30	0	0
T13	764524	282	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218542	0	0
T1	444173	11	0	0
T2	320382	14	0	0
T3	105427	68	0	0
T7	2025	10	0	0
T8	10755	116	0	0
T9	2396	10	0	0
T10	5981	119	0	0
T11	271705	1004	0	0
T12	346736	16	0	0
T13	764524	65	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	209411	0	0
GntImpliesValid_A	394935464	209411	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	209411	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	4884762	0	0
ReadyAndValidImplyGrant_A	394935464	209411	0	0
ReqAndReadyImplyGrant_A	394935464	209411	0	0
ReqImpliesValid_A	394935464	1148382	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	209411	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	209411	0	0
T1	444173	10	0	0
T2	320382	11	0	0
T3	105427	63	0	0
T7	2025	5	0	0
T8	10755	145	0	0
T9	2396	12	0	0
T10	5981	119	0	0
T11	271705	1020	0	0
T12	346736	16	0	0
T13	764524	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	209411	0	0
T1	444173	10	0	0
T2	320382	11	0	0
T3	105427	63	0	0
T7	2025	5	0	0
T8	10755	145	0	0
T9	2396	12	0	0
T10	5981	119	0	0
T11	271705	1020	0	0
T12	346736	16	0	0
T13	764524	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	209411	0	0
T1	444173	10	0	0
T2	320382	11	0	0
T3	105427	63	0	0
T7	2025	5	0	0
T8	10755	145	0	0
T9	2396	12	0	0
T10	5981	119	0	0
T11	271705	1020	0	0
T12	346736	16	0	0
T13	764524	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	4884762	0	0
T1	444173	1681	0	0
T2	320382	101	0	0
T3	105427	16196	0	0
T7	2025	22	0	0
T8	10755	879	0	0
T9	2396	202	0	0
T10	5981	453	0	0
T11	271705	4527	0	0
T12	346736	237	0	0
T13	764524	650	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	209411	0	0
T1	444173	10	0	0
T2	320382	11	0	0
T3	105427	63	0	0
T7	2025	5	0	0
T8	10755	145	0	0
T9	2396	12	0	0
T10	5981	119	0	0
T11	271705	1020	0	0
T12	346736	16	0	0
T13	764524	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	209411	0	0
T1	444173	10	0	0
T2	320382	11	0	0
T3	105427	63	0	0
T7	2025	5	0	0
T8	10755	145	0	0
T9	2396	12	0	0
T10	5981	119	0	0
T11	271705	1020	0	0
T12	346736	16	0	0
T13	764524	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	1148382	0	0
T1	444173	10	0	0
T2	320382	11	0	0
T3	105427	302	0	0
T7	2025	10	0	0
T8	10755	236	0	0
T9	2396	27	0	0
T10	5981	192	0	0
T11	271705	2987	0	0
T12	346736	38	0	0
T13	764524	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	209411	0	0
T1	444173	10	0	0
T2	320382	11	0	0
T3	105427	63	0	0
T7	2025	5	0	0
T8	10755	145	0	0
T9	2396	12	0	0
T10	5981	119	0	0
T11	271705	1020	0	0
T12	346736	16	0	0
T13	764524	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	224373	0	0
GntImpliesValid_A	394935464	224373	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	224373	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	4245786	0	0
ReadyAndValidImplyGrant_A	394935464	224373	0	0
ReqAndReadyImplyGrant_A	394935464	224373	0	0
ReqImpliesValid_A	394935464	1074364	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	224373	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	224373	0	0
T1	444173	12	0	0
T2	320382	15	0	0
T3	105427	76	0	0
T7	2025	8	0	0
T8	10755	157	0	0
T9	2396	16	0	0
T10	5981	129	0	0
T11	271705	616	0	0
T12	346736	13	0	0
T13	764524	68	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	224373	0	0
T1	444173	12	0	0
T2	320382	15	0	0
T3	105427	76	0	0
T7	2025	8	0	0
T8	10755	157	0	0
T9	2396	16	0	0
T10	5981	129	0	0
T11	271705	616	0	0
T12	346736	13	0	0
T13	764524	68	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	224373	0	0
T1	444173	12	0	0
T2	320382	15	0	0
T3	105427	76	0	0
T7	2025	8	0	0
T8	10755	157	0	0
T9	2396	16	0	0
T10	5981	129	0	0
T11	271705	616	0	0
T12	346736	13	0	0
T13	764524	68	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	4245786	0	0
T1	444173	2143	0	0
T2	320382	106	0	0
T3	105427	30315	0	0
T7	2025	46	0	0
T8	10755	1197	0	0
T9	2396	139	0	0
T10	5981	452	0	0
T11	271705	4727	0	0
T12	346736	89	0	0
T13	764524	716	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	224373	0	0
T1	444173	12	0	0
T2	320382	15	0	0
T3	105427	76	0	0
T7	2025	8	0	0
T8	10755	157	0	0
T9	2396	16	0	0
T10	5981	129	0	0
T11	271705	616	0	0
T12	346736	13	0	0
T13	764524	68	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	224373	0	0
T1	444173	12	0	0
T2	320382	15	0	0
T3	105427	76	0	0
T7	2025	8	0	0
T8	10755	157	0	0
T9	2396	16	0	0
T10	5981	129	0	0
T11	271705	616	0	0
T12	346736	13	0	0
T13	764524	68	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	1074364	0	0
T1	444173	182	0	0
T2	320382	29	0	0
T3	105427	2306	0	0
T7	2025	8	0	0
T8	10755	335	0	0
T9	2396	25	0	0
T10	5981	201	0	0
T11	271705	1193	0	0
T12	346736	26	0	0
T13	764524	132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	224373	0	0
T1	444173	12	0	0
T2	320382	15	0	0
T3	105427	76	0	0
T7	2025	8	0	0
T8	10755	157	0	0
T9	2396	16	0	0
T10	5981	129	0	0
T11	271705	616	0	0
T12	346736	13	0	0
T13	764524	68	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	217027	0	0
GntImpliesValid_A	394935464	217027	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	217027	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	5169717	0	0
ReadyAndValidImplyGrant_A	394935464	217027	0	0
ReqAndReadyImplyGrant_A	394935464	217027	0	0
ReqImpliesValid_A	394935464	1065928	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	217027	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	217027	0	0
T1	444173	6	0	0
T2	320382	14	0	0
T3	105427	60	0	0
T7	2025	12	0	0
T8	10755	133	0	0
T9	2396	16	0	0
T10	5981	99	0	0
T11	271705	1221	0	0
T12	346736	12	0	0
T13	764524	78	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	217027	0	0
T1	444173	6	0	0
T2	320382	14	0	0
T3	105427	60	0	0
T7	2025	12	0	0
T8	10755	133	0	0
T9	2396	16	0	0
T10	5981	99	0	0
T11	271705	1221	0	0
T12	346736	12	0	0
T13	764524	78	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	217027	0	0
T1	444173	6	0	0
T2	320382	14	0	0
T3	105427	60	0	0
T7	2025	12	0	0
T8	10755	133	0	0
T9	2396	16	0	0
T10	5981	99	0	0
T11	271705	1221	0	0
T12	346736	12	0	0
T13	764524	78	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	5169717	0	0
T1	444173	1398	0	0
T2	320382	115	0	0
T3	105427	101281	0	0
T7	2025	70	0	0
T8	10755	1119	0	0
T9	2396	89	0	0
T10	5981	313	0	0
T11	271705	7640	0	0
T12	346736	165	0	0
T13	764524	635	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	217027	0	0
T1	444173	6	0	0
T2	320382	14	0	0
T3	105427	60	0	0
T7	2025	12	0	0
T8	10755	133	0	0
T9	2396	16	0	0
T10	5981	99	0	0
T11	271705	1221	0	0
T12	346736	12	0	0
T13	764524	78	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	217027	0	0
T1	444173	6	0	0
T2	320382	14	0	0
T3	105427	60	0	0
T7	2025	12	0	0
T8	10755	133	0	0
T9	2396	16	0	0
T10	5981	99	0	0
T11	271705	1221	0	0
T12	346736	12	0	0
T13	764524	78	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	1065928	0	0
T1	444173	6	0	0
T2	320382	14	0	0
T3	105427	28654	0	0
T7	2025	26	0	0
T8	10755	247	0	0
T9	2396	43	0	0
T10	5981	126	0	0
T11	271705	10048	0	0
T12	346736	24	0	0
T13	764524	157	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	217027	0	0
T1	444173	6	0	0
T2	320382	14	0	0
T3	105427	60	0	0
T7	2025	12	0	0
T8	10755	133	0	0
T9	2396	16	0	0
T10	5981	99	0	0
T11	271705	1221	0	0
T12	346736	12	0	0
T13	764524	78	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	211628	0	0
GntImpliesValid_A	394935464	211628	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	211628	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2841535	0	0
ReadyAndValidImplyGrant_A	394935464	211628	0	0
ReqAndReadyImplyGrant_A	394935464	211628	0	0
ReqImpliesValid_A	394935464	512181	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	211628	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	211628	0	0
T1	444173	11	0	0
T2	320382	13	0	0
T3	105427	67	0	0
T7	2025	10	0	0
T8	10755	136	0	0
T9	2396	12	0	0
T10	5981	92	0	0
T11	271705	1517	0	0
T12	346736	21	0	0
T13	764524	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	211628	0	0
T1	444173	11	0	0
T2	320382	13	0	0
T3	105427	67	0	0
T7	2025	10	0	0
T8	10755	136	0	0
T9	2396	12	0	0
T10	5981	92	0	0
T11	271705	1517	0	0
T12	346736	21	0	0
T13	764524	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	211628	0	0
T1	444173	11	0	0
T2	320382	13	0	0
T3	105427	67	0	0
T7	2025	10	0	0
T8	10755	136	0	0
T9	2396	12	0	0
T10	5981	92	0	0
T11	271705	1517	0	0
T12	346736	21	0	0
T13	764524	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2841535	0	0
T1	444173	5092	0	0
T2	320382	50	0	0
T3	105427	21680	0	0
T7	2025	11	0	0
T8	10755	130	0	0
T9	2396	13	0	0
T10	5981	89	0	0
T11	271705	5144	0	0
T12	346736	80	0	0
T13	764524	256	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	211628	0	0
T1	444173	11	0	0
T2	320382	13	0	0
T3	105427	67	0	0
T7	2025	10	0	0
T8	10755	136	0	0
T9	2396	12	0	0
T10	5981	92	0	0
T11	271705	1517	0	0
T12	346736	21	0	0
T13	764524	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	211628	0	0
T1	444173	11	0	0
T2	320382	13	0	0
T3	105427	67	0	0
T7	2025	10	0	0
T8	10755	136	0	0
T9	2396	12	0	0
T10	5981	92	0	0
T11	271705	1517	0	0
T12	346736	21	0	0
T13	764524	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	512181	0	0
T1	444173	11	0	0
T2	320382	14	0	0
T3	105427	1292	0	0
T7	2025	10	0	0
T8	10755	143	0	0
T9	2396	12	0	0
T10	5981	96	0	0
T11	271705	10756	0	0
T12	346736	28	0	0
T13	764524	74	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	211628	0	0
T1	444173	11	0	0
T2	320382	13	0	0
T3	105427	67	0	0
T7	2025	10	0	0
T8	10755	136	0	0
T9	2396	12	0	0
T10	5981	92	0	0
T11	271705	1517	0	0
T12	346736	21	0	0
T13	764524	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	225984	0	0
GntImpliesValid_A	394935464	225984	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	225984	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2820970	0	0
ReadyAndValidImplyGrant_A	394935464	225984	0	0
ReqAndReadyImplyGrant_A	394935464	225984	0	0
ReqImpliesValid_A	394935464	573676	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	225984	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225984	0	0
T1	444173	7	0	0
T2	320382	16	0	0
T3	105427	67	0	0
T7	2025	20	0	0
T8	10755	139	0	0
T9	2396	9	0	0
T10	5981	100	0	0
T11	271705	501	0	0
T12	346736	15	0	0
T13	764524	56	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225984	0	0
T1	444173	7	0	0
T2	320382	16	0	0
T3	105427	67	0	0
T7	2025	20	0	0
T8	10755	139	0	0
T9	2396	9	0	0
T10	5981	100	0	0
T11	271705	501	0	0
T12	346736	15	0	0
T13	764524	56	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225984	0	0
T1	444173	7	0	0
T2	320382	16	0	0
T3	105427	67	0	0
T7	2025	20	0	0
T8	10755	139	0	0
T9	2396	9	0	0
T10	5981	100	0	0
T11	271705	501	0	0
T12	346736	15	0	0
T13	764524	56	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2820970	0	0
T1	444173	3106	0	0
T2	320382	69	0	0
T3	105427	23647	0	0
T7	2025	19	0	0
T8	10755	131	0	0
T9	2396	10	0	0
T10	5981	97	0	0
T11	271705	3637	0	0
T12	346736	77	0	0
T13	764524	264	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225984	0	0
T1	444173	7	0	0
T2	320382	16	0	0
T3	105427	67	0	0
T7	2025	20	0	0
T8	10755	139	0	0
T9	2396	9	0	0
T10	5981	100	0	0
T11	271705	501	0	0
T12	346736	15	0	0
T13	764524	56	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225984	0	0
T1	444173	7	0	0
T2	320382	16	0	0
T3	105427	67	0	0
T7	2025	20	0	0
T8	10755	139	0	0
T9	2396	9	0	0
T10	5981	100	0	0
T11	271705	501	0	0
T12	346736	15	0	0
T13	764524	56	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	573676	0	0
T1	444173	7	0	0
T2	320382	25	0	0
T3	105427	2487	0	0
T7	2025	22	0	0
T8	10755	148	0	0
T9	2396	9	0	0
T10	5981	104	0	0
T11	271705	647	0	0
T12	346736	15	0	0
T13	764524	69	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225984	0	0
T1	444173	7	0	0
T2	320382	16	0	0
T3	105427	67	0	0
T7	2025	20	0	0
T8	10755	139	0	0
T9	2396	9	0	0
T10	5981	100	0	0
T11	271705	501	0	0
T12	346736	15	0	0
T13	764524	56	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	216854	0	0
GntImpliesValid_A	394935464	216854	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	216854	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2827741	0	0
ReadyAndValidImplyGrant_A	394935464	216854	0	0
ReqAndReadyImplyGrant_A	394935464	216854	0	0
ReqImpliesValid_A	394935464	543033	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	216854	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216854	0	0
T1	444173	7	0	0
T2	320382	17	0	0
T3	105427	73	0	0
T7	2025	10	0	0
T8	10755	145	0	0
T9	2396	21	0	0
T10	5981	102	0	0
T11	271705	492	0	0
T12	346736	16	0	0
T13	764524	69	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216854	0	0
T1	444173	7	0	0
T2	320382	17	0	0
T3	105427	73	0	0
T7	2025	10	0	0
T8	10755	145	0	0
T9	2396	21	0	0
T10	5981	102	0	0
T11	271705	492	0	0
T12	346736	16	0	0
T13	764524	69	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216854	0	0
T1	444173	7	0	0
T2	320382	17	0	0
T3	105427	73	0	0
T7	2025	10	0	0
T8	10755	145	0	0
T9	2396	21	0	0
T10	5981	102	0	0
T11	271705	492	0	0
T12	346736	16	0	0
T13	764524	69	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2827741	0	0
T1	444173	3513	0	0
T2	320382	80	0	0
T3	105427	24877	0	0
T7	2025	11	0	0
T8	10755	140	0	0
T9	2396	21	0	0
T10	5981	92	0	0
T11	271705	3682	0	0
T12	346736	76	0	0
T13	764524	276	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216854	0	0
T1	444173	7	0	0
T2	320382	17	0	0
T3	105427	73	0	0
T7	2025	10	0	0
T8	10755	145	0	0
T9	2396	21	0	0
T10	5981	102	0	0
T11	271705	492	0	0
T12	346736	16	0	0
T13	764524	69	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216854	0	0
T1	444173	7	0	0
T2	320382	17	0	0
T3	105427	73	0	0
T7	2025	10	0	0
T8	10755	145	0	0
T9	2396	21	0	0
T10	5981	102	0	0
T11	271705	492	0	0
T12	346736	16	0	0
T13	764524	69	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	543033	0	0
T1	444173	7	0	0
T2	320382	24	0	0
T3	105427	1223	0	0
T7	2025	10	0	0
T8	10755	151	0	0
T9	2396	22	0	0
T10	5981	113	0	0
T11	271705	686	0	0
T12	346736	16	0	0
T13	764524	87	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216854	0	0
T1	444173	7	0	0
T2	320382	17	0	0
T3	105427	73	0	0
T7	2025	10	0	0
T8	10755	145	0	0
T9	2396	21	0	0
T10	5981	102	0	0
T11	271705	492	0	0
T12	346736	16	0	0
T13	764524	69	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	214526	0	0
GntImpliesValid_A	394935464	214526	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	214526	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2865563	0	0
ReadyAndValidImplyGrant_A	394935464	214526	0	0
ReqAndReadyImplyGrant_A	394935464	214526	0	0
ReqImpliesValid_A	394935464	560604	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	214526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214526	0	0
T1	444173	13	0	0
T2	320382	15	0	0
T3	105427	65	0	0
T7	2025	10	0	0
T8	10755	137	0	0
T9	2396	12	0	0
T10	5981	129	0	0
T11	271705	512	0	0
T12	346736	16	0	0
T13	764524	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214526	0	0
T1	444173	13	0	0
T2	320382	15	0	0
T3	105427	65	0	0
T7	2025	10	0	0
T8	10755	137	0	0
T9	2396	12	0	0
T10	5981	129	0	0
T11	271705	512	0	0
T12	346736	16	0	0
T13	764524	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214526	0	0
T1	444173	13	0	0
T2	320382	15	0	0
T3	105427	65	0	0
T7	2025	10	0	0
T8	10755	137	0	0
T9	2396	12	0	0
T10	5981	129	0	0
T11	271705	512	0	0
T12	346736	16	0	0
T13	764524	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2865563	0	0
T1	444173	4600	0	0
T2	320382	74	0	0
T3	105427	20576	0	0
T7	2025	11	0	0
T8	10755	131	0	0
T9	2396	12	0	0
T10	5981	122	0	0
T11	271705	3692	0	0
T12	346736	72	0	0
T13	764524	264	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214526	0	0
T1	444173	13	0	0
T2	320382	15	0	0
T3	105427	65	0	0
T7	2025	10	0	0
T8	10755	137	0	0
T9	2396	12	0	0
T10	5981	129	0	0
T11	271705	512	0	0
T12	346736	16	0	0
T13	764524	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214526	0	0
T1	444173	13	0	0
T2	320382	15	0	0
T3	105427	65	0	0
T7	2025	10	0	0
T8	10755	137	0	0
T9	2396	12	0	0
T10	5981	129	0	0
T11	271705	512	0	0
T12	346736	16	0	0
T13	764524	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	560604	0	0
T1	444173	13	0	0
T2	320382	25	0	0
T3	105427	734	0	0
T7	2025	10	0	0
T8	10755	144	0	0
T9	2396	13	0	0
T10	5981	137	0	0
T11	271705	665	0	0
T12	346736	16	0	0
T13	764524	72	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	214526	0	0
T1	444173	13	0	0
T2	320382	15	0	0
T3	105427	65	0	0
T7	2025	10	0	0
T8	10755	137	0	0
T9	2396	12	0	0
T10	5981	129	0	0
T11	271705	512	0	0
T12	346736	16	0	0
T13	764524	65	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	218706	0	0
GntImpliesValid_A	394935464	218706	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	218706	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2863987	0	0
ReadyAndValidImplyGrant_A	394935464	218706	0	0
ReqAndReadyImplyGrant_A	394935464	218706	0	0
ReqImpliesValid_A	394935464	546213	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	218706	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218706	0	0
T1	444173	11	0	0
T2	320382	26	0	0
T3	105427	67	0	0
T7	2025	24	0	0
T8	10755	126	0	0
T9	2396	17	0	0
T10	5981	97	0	0
T11	271705	514	0	0
T12	346736	9	0	0
T13	764524	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218706	0	0
T1	444173	11	0	0
T2	320382	26	0	0
T3	105427	67	0	0
T7	2025	24	0	0
T8	10755	126	0	0
T9	2396	17	0	0
T10	5981	97	0	0
T11	271705	514	0	0
T12	346736	9	0	0
T13	764524	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218706	0	0
T1	444173	11	0	0
T2	320382	26	0	0
T3	105427	67	0	0
T7	2025	24	0	0
T8	10755	126	0	0
T9	2396	17	0	0
T10	5981	97	0	0
T11	271705	514	0	0
T12	346736	9	0	0
T13	764524	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2863987	0	0
T1	444173	4202	0	0
T2	320382	122	0	0
T3	105427	19222	0	0
T7	2025	23	0	0
T8	10755	120	0	0
T9	2396	18	0	0
T10	5981	90	0	0
T11	271705	3824	0	0
T12	346736	55	0	0
T13	764524	272	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218706	0	0
T1	444173	11	0	0
T2	320382	26	0	0
T3	105427	67	0	0
T7	2025	24	0	0
T8	10755	126	0	0
T9	2396	17	0	0
T10	5981	97	0	0
T11	271705	514	0	0
T12	346736	9	0	0
T13	764524	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218706	0	0
T1	444173	11	0	0
T2	320382	26	0	0
T3	105427	67	0	0
T7	2025	24	0	0
T8	10755	126	0	0
T9	2396	17	0	0
T10	5981	97	0	0
T11	271705	514	0	0
T12	346736	9	0	0
T13	764524	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	546213	0	0
T1	444173	11	0	0
T2	320382	36	0	0
T3	105427	3037	0	0
T7	2025	26	0	0
T8	10755	133	0	0
T9	2396	17	0	0
T10	5981	105	0	0
T11	271705	741	0	0
T12	346736	9	0	0
T13	764524	71	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218706	0	0
T1	444173	11	0	0
T2	320382	26	0	0
T3	105427	67	0	0
T7	2025	24	0	0
T8	10755	126	0	0
T9	2396	17	0	0
T10	5981	97	0	0
T11	271705	514	0	0
T12	346736	9	0	0
T13	764524	67	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	218314	0	0
GntImpliesValid_A	394935464	218314	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	218314	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2894400	0	0
ReadyAndValidImplyGrant_A	394935464	218314	0	0
ReqAndReadyImplyGrant_A	394935464	218314	0	0
ReqImpliesValid_A	394935464	581982	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	218314	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218314	0	0
T1	444173	16	0	0
T2	320382	14	0	0
T3	105427	61	0	0
T7	2025	13	0	0
T8	10755	146	0	0
T9	2396	5	0	0
T10	5981	116	0	0
T11	271705	1527	0	0
T12	346736	17	0	0
T13	764524	69	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218314	0	0
T1	444173	16	0	0
T2	320382	14	0	0
T3	105427	61	0	0
T7	2025	13	0	0
T8	10755	146	0	0
T9	2396	5	0	0
T10	5981	116	0	0
T11	271705	1527	0	0
T12	346736	17	0	0
T13	764524	69	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218314	0	0
T1	444173	16	0	0
T2	320382	14	0	0
T3	105427	61	0	0
T7	2025	13	0	0
T8	10755	146	0	0
T9	2396	5	0	0
T10	5981	116	0	0
T11	271705	1527	0	0
T12	346736	17	0	0
T13	764524	69	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2894400	0	0
T1	444173	5832	0	0
T2	320382	69	0	0
T3	105427	17854	0	0
T7	2025	13	0	0
T8	10755	140	0	0
T9	2396	6	0	0
T10	5981	109	0	0
T11	271705	7455	0	0
T12	346736	84	0	0
T13	764524	253	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218314	0	0
T1	444173	16	0	0
T2	320382	14	0	0
T3	105427	61	0	0
T7	2025	13	0	0
T8	10755	146	0	0
T9	2396	5	0	0
T10	5981	116	0	0
T11	271705	1527	0	0
T12	346736	17	0	0
T13	764524	69	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218314	0	0
T1	444173	16	0	0
T2	320382	14	0	0
T3	105427	61	0	0
T7	2025	13	0	0
T8	10755	146	0	0
T9	2396	5	0	0
T10	5981	116	0	0
T11	271705	1527	0	0
T12	346736	17	0	0
T13	764524	69	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	581982	0	0
T1	444173	563	0	0
T2	320382	14	0	0
T3	105427	293	0	0
T7	2025	14	0	0
T8	10755	153	0	0
T9	2396	5	0	0
T10	5981	124	0	0
T11	271705	7588	0	0
T12	346736	22	0	0
T13	764524	70	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218314	0	0
T1	444173	16	0	0
T2	320382	14	0	0
T3	105427	61	0	0
T7	2025	13	0	0
T8	10755	146	0	0
T9	2396	5	0	0
T10	5981	116	0	0
T11	271705	1527	0	0
T12	346736	17	0	0
T13	764524	69	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	223027	0	0
GntImpliesValid_A	394935464	223027	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	223027	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2920155	0	0
ReadyAndValidImplyGrant_A	394935464	223027	0	0
ReqAndReadyImplyGrant_A	394935464	223027	0	0
ReqImpliesValid_A	394935464	567791	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	223027	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	223027	0	0
T1	444173	12	0	0
T2	320382	13	0	0
T3	105427	64	0	0
T7	2025	7	0	0
T8	10755	150	0	0
T9	2396	16	0	0
T10	5981	106	0	0
T11	271705	518	0	0
T12	346736	13	0	0
T13	764524	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	223027	0	0
T1	444173	12	0	0
T2	320382	13	0	0
T3	105427	64	0	0
T7	2025	7	0	0
T8	10755	150	0	0
T9	2396	16	0	0
T10	5981	106	0	0
T11	271705	518	0	0
T12	346736	13	0	0
T13	764524	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	223027	0	0
T1	444173	12	0	0
T2	320382	13	0	0
T3	105427	64	0	0
T7	2025	7	0	0
T8	10755	150	0	0
T9	2396	16	0	0
T10	5981	106	0	0
T11	271705	518	0	0
T12	346736	13	0	0
T13	764524	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2920155	0	0
T1	444173	2721	0	0
T2	320382	54	0	0
T3	105427	21857	0	0
T7	2025	8	0	0
T8	10755	146	0	0
T9	2396	17	0	0
T10	5981	99	0	0
T11	271705	3976	0	0
T12	346736	51	0	0
T13	764524	281	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	223027	0	0
T1	444173	12	0	0
T2	320382	13	0	0
T3	105427	64	0	0
T7	2025	7	0	0
T8	10755	150	0	0
T9	2396	16	0	0
T10	5981	106	0	0
T11	271705	518	0	0
T12	346736	13	0	0
T13	764524	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	223027	0	0
T1	444173	12	0	0
T2	320382	13	0	0
T3	105427	64	0	0
T7	2025	7	0	0
T8	10755	150	0	0
T9	2396	16	0	0
T10	5981	106	0	0
T11	271705	518	0	0
T12	346736	13	0	0
T13	764524	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	567791	0	0
T1	444173	181	0	0
T2	320382	13	0	0
T3	105427	939	0	0
T7	2025	7	0	0
T8	10755	155	0	0
T9	2396	16	0	0
T10	5981	114	0	0
T11	271705	762	0	0
T12	346736	21	0	0
T13	764524	89	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	223027	0	0
T1	444173	12	0	0
T2	320382	13	0	0
T3	105427	64	0	0
T7	2025	7	0	0
T8	10755	150	0	0
T9	2396	16	0	0
T10	5981	106	0	0
T11	271705	518	0	0
T12	346736	13	0	0
T13	764524	67	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	225302	0	0
GntImpliesValid_A	394935464	225302	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	225302	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2915962	0	0
ReadyAndValidImplyGrant_A	394935464	225302	0	0
ReqAndReadyImplyGrant_A	394935464	225302	0	0
ReqImpliesValid_A	394935464	588947	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	225302	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225302	0	0
T1	444173	12	0	0
T2	320382	11	0	0
T3	105427	64	0	0
T7	2025	11	0	0
T8	10755	133	0	0
T9	2396	14	0	0
T10	5981	110	0	0
T11	271705	554	0	0
T12	346736	11	0	0
T13	764524	69	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225302	0	0
T1	444173	12	0	0
T2	320382	11	0	0
T3	105427	64	0	0
T7	2025	11	0	0
T8	10755	133	0	0
T9	2396	14	0	0
T10	5981	110	0	0
T11	271705	554	0	0
T12	346736	11	0	0
T13	764524	69	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225302	0	0
T1	444173	12	0	0
T2	320382	11	0	0
T3	105427	64	0	0
T7	2025	11	0	0
T8	10755	133	0	0
T9	2396	14	0	0
T10	5981	110	0	0
T11	271705	554	0	0
T12	346736	11	0	0
T13	764524	69	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2915962	0	0
T1	444173	3782	0	0
T2	320382	41	0	0
T3	105427	20883	0	0
T7	2025	12	0	0
T8	10755	124	0	0
T9	2396	15	0	0
T10	5981	109	0	0
T11	271705	3919	0	0
T12	346736	34	0	0
T13	764524	241	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225302	0	0
T1	444173	12	0	0
T2	320382	11	0	0
T3	105427	64	0	0
T7	2025	11	0	0
T8	10755	133	0	0
T9	2396	14	0	0
T10	5981	110	0	0
T11	271705	554	0	0
T12	346736	11	0	0
T13	764524	69	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225302	0	0
T1	444173	12	0	0
T2	320382	11	0	0
T3	105427	64	0	0
T7	2025	11	0	0
T8	10755	133	0	0
T9	2396	14	0	0
T10	5981	110	0	0
T11	271705	554	0	0
T12	346736	11	0	0
T13	764524	69	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	588947	0	0
T1	444173	61	0	0
T2	320382	11	0	0
T3	105427	1128	0	0
T7	2025	11	0	0
T8	10755	143	0	0
T9	2396	14	0	0
T10	5981	112	0	0
T11	271705	883	0	0
T12	346736	16	0	0
T13	764524	83	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	225302	0	0
T1	444173	12	0	0
T2	320382	11	0	0
T3	105427	64	0	0
T7	2025	11	0	0
T8	10755	133	0	0
T9	2396	14	0	0
T10	5981	110	0	0
T11	271705	554	0	0
T12	346736	11	0	0
T13	764524	69	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	236534	0	0
GntImpliesValid_A	394935464	236534	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	236534	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2961314	0	0
ReadyAndValidImplyGrant_A	394935464	236534	0	0
ReqAndReadyImplyGrant_A	394935464	236534	0	0
ReqImpliesValid_A	394935464	616861	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	236534	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	236534	0	0
T1	444173	13	0	0
T2	320382	18	0	0
T3	105427	75	0	0
T7	2025	15	0	0
T8	10755	131	0	0
T9	2396	16	0	0
T10	5981	133	0	0
T11	271705	1483	0	0
T12	346736	17	0	0
T13	764524	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	236534	0	0
T1	444173	13	0	0
T2	320382	18	0	0
T3	105427	75	0	0
T7	2025	15	0	0
T8	10755	131	0	0
T9	2396	16	0	0
T10	5981	133	0	0
T11	271705	1483	0	0
T12	346736	17	0	0
T13	764524	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	236534	0	0
T1	444173	13	0	0
T2	320382	18	0	0
T3	105427	75	0	0
T7	2025	15	0	0
T8	10755	131	0	0
T9	2396	16	0	0
T10	5981	133	0	0
T11	271705	1483	0	0
T12	346736	17	0	0
T13	764524	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2961314	0	0
T1	444173	5845	0	0
T2	320382	87	0	0
T3	105427	24433	0	0
T7	2025	16	0	0
T8	10755	125	0	0
T9	2396	17	0	0
T10	5981	125	0	0
T11	271705	7636	0	0
T12	346736	71	0	0
T13	764524	250	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	236534	0	0
T1	444173	13	0	0
T2	320382	18	0	0
T3	105427	75	0	0
T7	2025	15	0	0
T8	10755	131	0	0
T9	2396	16	0	0
T10	5981	133	0	0
T11	271705	1483	0	0
T12	346736	17	0	0
T13	764524	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	236534	0	0
T1	444173	13	0	0
T2	320382	18	0	0
T3	105427	75	0	0
T7	2025	15	0	0
T8	10755	131	0	0
T9	2396	16	0	0
T10	5981	133	0	0
T11	271705	1483	0	0
T12	346736	17	0	0
T13	764524	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	616861	0	0
T1	444173	13	0	0
T2	320382	24	0	0
T3	105427	3788	0	0
T7	2025	15	0	0
T8	10755	138	0	0
T9	2396	16	0	0
T10	5981	142	0	0
T11	271705	7237	0	0
T12	346736	35	0	0
T13	764524	58	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	236534	0	0
T1	444173	13	0	0
T2	320382	18	0	0
T3	105427	75	0	0
T7	2025	15	0	0
T8	10755	131	0	0
T9	2396	16	0	0
T10	5981	133	0	0
T11	271705	1483	0	0
T12	346736	17	0	0
T13	764524	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	216971	0	0
GntImpliesValid_A	394935464	216971	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	216971	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2859233	0	0
ReadyAndValidImplyGrant_A	394935464	216971	0	0
ReqAndReadyImplyGrant_A	394935464	216971	0	0
ReqImpliesValid_A	394935464	533749	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	216971	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216971	0	0
T1	444173	17	0	0
T2	320382	9	0	0
T3	105427	74	0	0
T7	2025	16	0	0
T8	10755	161	0	0
T9	2396	12	0	0
T10	5981	106	0	0
T11	271705	992	0	0
T12	346736	17	0	0
T13	764524	71	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216971	0	0
T1	444173	17	0	0
T2	320382	9	0	0
T3	105427	74	0	0
T7	2025	16	0	0
T8	10755	161	0	0
T9	2396	12	0	0
T10	5981	106	0	0
T11	271705	992	0	0
T12	346736	17	0	0
T13	764524	71	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216971	0	0
T1	444173	17	0	0
T2	320382	9	0	0
T3	105427	74	0	0
T7	2025	16	0	0
T8	10755	161	0	0
T9	2396	12	0	0
T10	5981	106	0	0
T11	271705	992	0	0
T12	346736	17	0	0
T13	764524	71	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2859233	0	0
T1	444173	4404	0	0
T2	320382	33	0	0
T3	105427	23698	0	0
T7	2025	17	0	0
T8	10755	154	0	0
T9	2396	12	0	0
T10	5981	102	0	0
T11	271705	4463	0	0
T12	346736	78	0	0
T13	764524	296	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216971	0	0
T1	444173	17	0	0
T2	320382	9	0	0
T3	105427	74	0	0
T7	2025	16	0	0
T8	10755	161	0	0
T9	2396	12	0	0
T10	5981	106	0	0
T11	271705	992	0	0
T12	346736	17	0	0
T13	764524	71	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216971	0	0
T1	444173	17	0	0
T2	320382	9	0	0
T3	105427	74	0	0
T7	2025	16	0	0
T8	10755	161	0	0
T9	2396	12	0	0
T10	5981	106	0	0
T11	271705	992	0	0
T12	346736	17	0	0
T13	764524	71	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	533749	0	0
T1	444173	150	0	0
T2	320382	9	0	0
T3	105427	1914	0	0
T7	2025	16	0	0
T8	10755	169	0	0
T9	2396	13	0	0
T10	5981	111	0	0
T11	271705	5275	0	0
T12	346736	23	0	0
T13	764524	73	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	216971	0	0
T1	444173	17	0	0
T2	320382	9	0	0
T3	105427	74	0	0
T7	2025	16	0	0
T8	10755	161	0	0
T9	2396	12	0	0
T10	5981	106	0	0
T11	271705	992	0	0
T12	346736	17	0	0
T13	764524	71	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T10,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	215528	0	0
GntImpliesValid_A	394935464	215528	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	215528	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2867454	0	0
ReadyAndValidImplyGrant_A	394935464	215528	0	0
ReqAndReadyImplyGrant_A	394935464	215528	0	0
ReqImpliesValid_A	394935464	534699	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	215528	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	215528	0	0
T1	444173	8	0	0
T2	320382	7	0	0
T3	105427	58	0	0
T7	2025	18	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	116	0	0
T11	271705	982	0	0
T12	346736	14	0	0
T13	764524	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	215528	0	0
T1	444173	8	0	0
T2	320382	7	0	0
T3	105427	58	0	0
T7	2025	18	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	116	0	0
T11	271705	982	0	0
T12	346736	14	0	0
T13	764524	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	215528	0	0
T1	444173	8	0	0
T2	320382	7	0	0
T3	105427	58	0	0
T7	2025	18	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	116	0	0
T11	271705	982	0	0
T12	346736	14	0	0
T13	764524	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2867454	0	0
T1	444173	2757	0	0
T2	320382	23	0	0
T3	105427	19625	0	0
T7	2025	19	0	0
T8	10755	136	0	0
T9	2396	12	0	0
T10	5981	113	0	0
T11	271705	4607	0	0
T12	346736	60	0	0
T13	764524	183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	215528	0	0
T1	444173	8	0	0
T2	320382	7	0	0
T3	105427	58	0	0
T7	2025	18	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	116	0	0
T11	271705	982	0	0
T12	346736	14	0	0
T13	764524	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	215528	0	0
T1	444173	8	0	0
T2	320382	7	0	0
T3	105427	58	0	0
T7	2025	18	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	116	0	0
T11	271705	982	0	0
T12	346736	14	0	0
T13	764524	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	534699	0	0
T1	444173	8	0	0
T2	320382	7	0	0
T3	105427	58	0	0
T7	2025	18	0	0
T8	10755	149	0	0
T9	2396	11	0	0
T10	5981	120	0	0
T11	271705	5138	0	0
T12	346736	15	0	0
T13	764524	52	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	215528	0	0
T1	444173	8	0	0
T2	320382	7	0	0
T3	105427	58	0	0
T7	2025	18	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	116	0	0
T11	271705	982	0	0
T12	346736	14	0	0
T13	764524	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	222965	0	0
GntImpliesValid_A	394935464	222965	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	222965	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2837296	0	0
ReadyAndValidImplyGrant_A	394935464	222965	0	0
ReqAndReadyImplyGrant_A	394935464	222965	0	0
ReqImpliesValid_A	394935464	585043	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	222965	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	222965	0	0
T1	444173	18	0	0
T2	320382	15	0	0
T3	105427	56	0	0
T7	2025	14	0	0
T8	10755	132	0	0
T9	2396	7	0	0
T10	5981	108	0	0
T11	271705	1006	0	0
T12	346736	25	0	0
T13	764524	71	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	222965	0	0
T1	444173	18	0	0
T2	320382	15	0	0
T3	105427	56	0	0
T7	2025	14	0	0
T8	10755	132	0	0
T9	2396	7	0	0
T10	5981	108	0	0
T11	271705	1006	0	0
T12	346736	25	0	0
T13	764524	71	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	222965	0	0
T1	444173	18	0	0
T2	320382	15	0	0
T3	105427	56	0	0
T7	2025	14	0	0
T8	10755	132	0	0
T9	2396	7	0	0
T10	5981	108	0	0
T11	271705	1006	0	0
T12	346736	25	0	0
T13	764524	71	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2837296	0	0
T1	444173	5466	0	0
T2	320382	73	0	0
T3	105427	16977	0	0
T7	2025	13	0	0
T8	10755	120	0	0
T9	2396	8	0	0
T10	5981	99	0	0
T11	271705	4492	0	0
T12	346736	125	0	0
T13	764524	314	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	222965	0	0
T1	444173	18	0	0
T2	320382	15	0	0
T3	105427	56	0	0
T7	2025	14	0	0
T8	10755	132	0	0
T9	2396	7	0	0
T10	5981	108	0	0
T11	271705	1006	0	0
T12	346736	25	0	0
T13	764524	71	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	222965	0	0
T1	444173	18	0	0
T2	320382	15	0	0
T3	105427	56	0	0
T7	2025	14	0	0
T8	10755	132	0	0
T9	2396	7	0	0
T10	5981	108	0	0
T11	271705	1006	0	0
T12	346736	25	0	0
T13	764524	71	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	585043	0	0
T1	444173	18	0	0
T2	320382	17	0	0
T3	105427	56	0	0
T7	2025	16	0	0
T8	10755	145	0	0
T9	2396	7	0	0
T10	5981	118	0	0
T11	271705	5858	0	0
T12	346736	28	0	0
T13	764524	84	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	222965	0	0
T1	444173	18	0	0
T2	320382	15	0	0
T3	105427	56	0	0
T7	2025	14	0	0
T8	10755	132	0	0
T9	2396	7	0	0
T10	5981	108	0	0
T11	271705	1006	0	0
T12	346736	25	0	0
T13	764524	71	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	220862	0	0
GntImpliesValid_A	394935464	220862	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	220862	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2824824	0	0
ReadyAndValidImplyGrant_A	394935464	220862	0	0
ReqAndReadyImplyGrant_A	394935464	220862	0	0
ReqImpliesValid_A	394935464	561345	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	220862	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	220862	0	0
T1	444173	6	0	0
T2	320382	21	0	0
T3	105427	60	0	0
T7	2025	9	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	105	0	0
T11	271705	493	0	0
T12	346736	17	0	0
T13	764524	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	220862	0	0
T1	444173	6	0	0
T2	320382	21	0	0
T3	105427	60	0	0
T7	2025	9	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	105	0	0
T11	271705	493	0	0
T12	346736	17	0	0
T13	764524	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	220862	0	0
T1	444173	6	0	0
T2	320382	21	0	0
T3	105427	60	0	0
T7	2025	9	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	105	0	0
T11	271705	493	0	0
T12	346736	17	0	0
T13	764524	66	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2824824	0	0
T1	444173	1933	0	0
T2	320382	112	0	0
T3	105427	22744	0	0
T7	2025	8	0	0
T8	10755	139	0	0
T9	2396	11	0	0
T10	5981	97	0	0
T11	271705	3813	0	0
T12	346736	58	0	0
T13	764524	273	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	220862	0	0
T1	444173	6	0	0
T2	320382	21	0	0
T3	105427	60	0	0
T7	2025	9	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	105	0	0
T11	271705	493	0	0
T12	346736	17	0	0
T13	764524	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	220862	0	0
T1	444173	6	0	0
T2	320382	21	0	0
T3	105427	60	0	0
T7	2025	9	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	105	0	0
T11	271705	493	0	0
T12	346736	17	0	0
T13	764524	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	561345	0	0
T1	444173	6	0	0
T2	320382	33	0	0
T3	105427	468	0	0
T7	2025	11	0	0
T8	10755	146	0	0
T9	2396	12	0	0
T10	5981	114	0	0
T11	271705	666	0	0
T12	346736	17	0	0
T13	764524	82	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	220862	0	0
T1	444173	6	0	0
T2	320382	21	0	0
T3	105427	60	0	0
T7	2025	9	0	0
T8	10755	142	0	0
T9	2396	11	0	0
T10	5981	105	0	0
T11	271705	493	0	0
T12	346736	17	0	0
T13	764524	66	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	218854	0	0
GntImpliesValid_A	394935464	218854	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	218854	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	2880910	0	0
ReadyAndValidImplyGrant_A	394935464	218854	0	0
ReqAndReadyImplyGrant_A	394935464	218854	0	0
ReqImpliesValid_A	394935464	542283	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	0	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	218854	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218854	0	0
T1	444173	12	0	0
T2	320382	17	0	0
T3	105427	58	0	0
T7	2025	6	0	0
T8	10755	134	0	0
T9	2396	7	0	0
T10	5981	118	0	0
T11	271705	1420	0	0
T12	346736	10	0	0
T13	764524	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218854	0	0
T1	444173	12	0	0
T2	320382	17	0	0
T3	105427	58	0	0
T7	2025	6	0	0
T8	10755	134	0	0
T9	2396	7	0	0
T10	5981	118	0	0
T11	271705	1420	0	0
T12	346736	10	0	0
T13	764524	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218854	0	0
T1	444173	12	0	0
T2	320382	17	0	0
T3	105427	58	0	0
T7	2025	6	0	0
T8	10755	134	0	0
T9	2396	7	0	0
T10	5981	118	0	0
T11	271705	1420	0	0
T12	346736	10	0	0
T13	764524	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2880910	0	0
T1	444173	5077	0	0
T2	320382	66	0	0
T3	105427	22172	0	0
T7	2025	7	0	0
T8	10755	126	0	0
T9	2396	8	0	0
T10	5981	109	0	0
T11	271705	5120	0	0
T12	346736	53	0	0
T13	764524	255	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218854	0	0
T1	444173	12	0	0
T2	320382	17	0	0
T3	105427	58	0	0
T7	2025	6	0	0
T8	10755	134	0	0
T9	2396	7	0	0
T10	5981	118	0	0
T11	271705	1420	0	0
T12	346736	10	0	0
T13	764524	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218854	0	0
T1	444173	12	0	0
T2	320382	17	0	0
T3	105427	58	0	0
T7	2025	6	0	0
T8	10755	134	0	0
T9	2396	7	0	0
T10	5981	118	0	0
T11	271705	1420	0	0
T12	346736	10	0	0
T13	764524	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	542283	0	0
T1	444173	273	0	0
T2	320382	26	0	0
T3	105427	493	0	0
T7	2025	6	0	0
T8	10755	143	0	0
T9	2396	7	0	0
T10	5981	128	0	0
T11	271705	4512	0	0
T12	346736	11	0	0
T13	764524	75	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	218854	0	0
T1	444173	12	0	0
T2	320382	17	0	0
T3	105427	58	0	0
T7	2025	6	0	0
T8	10755	134	0	0
T9	2396	7	0	0
T10	5981	118	0	0
T11	271705	1420	0	0
T12	346736	10	0	0
T13	764524	62	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	885631	0	0
GntImpliesValid_A	394935464	885631	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	885631	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	10751008	0	0
ReadyAndValidImplyGrant_A	394935464	885631	0	0
ReqAndReadyImplyGrant_A	394935464	885631	0	0
ReqImpliesValid_A	394935464	2123155	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	20875	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	885631	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	885631	0	0
T1	444173	54	0	0
T2	320382	38	0	0
T3	105427	251	0	0
T7	2025	48	0	0
T8	10755	575	0	0
T9	2396	62	0	0
T10	5981	436	0	0
T11	271705	3724	0	0
T12	346736	59	0	0
T13	764524	269	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	885631	0	0
T1	444173	54	0	0
T2	320382	38	0	0
T3	105427	251	0	0
T7	2025	48	0	0
T8	10755	575	0	0
T9	2396	62	0	0
T10	5981	436	0	0
T11	271705	3724	0	0
T12	346736	59	0	0
T13	764524	269	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	885631	0	0
T1	444173	54	0	0
T2	320382	38	0	0
T3	105427	251	0	0
T7	2025	48	0	0
T8	10755	575	0	0
T9	2396	62	0	0
T10	5981	436	0	0
T11	271705	3724	0	0
T12	346736	59	0	0
T13	764524	269	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	10751008	0	0
T1	444173	17086	0	0
T2	320382	124	0	0
T3	105427	75936	0	0
T7	2025	1	0	0
T8	10755	1	0	0
T9	2396	1	0	0
T10	5981	1	0	0
T11	271705	21585	0	0
T12	346736	177	0	0
T13	764524	896	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	885631	0	0
T1	444173	54	0	0
T2	320382	38	0	0
T3	105427	251	0	0
T7	2025	48	0	0
T8	10755	575	0	0
T9	2396	62	0	0
T10	5981	436	0	0
T11	271705	3724	0	0
T12	346736	59	0	0
T13	764524	269	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	885631	0	0
T1	444173	54	0	0
T2	320382	38	0	0
T3	105427	251	0	0
T7	2025	48	0	0
T8	10755	575	0	0
T9	2396	62	0	0
T10	5981	436	0	0
T11	271705	3724	0	0
T12	346736	59	0	0
T13	764524	269	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	2123155	0	0
T1	444173	200	0	0
T2	320382	40	0	0
T3	105427	6938	0	0
T7	2025	48	0	0
T8	10755	575	0	0
T9	2396	62	0	0
T10	5981	436	0	0
T11	271705	10489	0	0
T12	346736	87	0	0
T13	764524	332	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	20875	0	899
T4	0	74	0	0
T5	0	6	0	0
T8	10755	6	0	1
T9	2396	0	0	1
T10	5981	11	0	1
T11	271705	10	0	1
T12	346736	0	0	1
T13	764524	0	0	1
T14	328038	9	0	1
T15	45943	0	0	1
T16	0	1	0	0
T18	0	1	0	0
T19	0	151	0	0
T20	0	13	0	0
T21	63137	0	0	1
T22	286091	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	885631	0	0
T1	444173	54	0	0
T2	320382	38	0	0
T3	105427	251	0	0
T7	2025	48	0	0
T8	10755	575	0	0
T9	2396	62	0	0
T10	5981	436	0	0
T11	271705	3724	0	0
T12	346736	59	0	0
T13	764524	269	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394935464	394812297	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	394935464	876175	0	0
GntImpliesValid_A	394935464	876175	0	0
GrantKnown_A	394935464	394812297	0	0
IdxKnown_A	394935464	394812297	0	0
IndexIsCorrect_A	394935464	876175	0	0
LockArbDecision_A	394935464	0	0	0
NoReadyValidNoGrant_A	394935464	330909284	0	0
ReadyAndValidImplyGrant_A	394935464	876175	0	0
ReqAndReadyImplyGrant_A	394935464	876175	0	0
ReqImpliesValid_A	394935464	12695430	0	0
ReqStaysHighUntilGranted0_M	394935464	0	0	0
RoundRobin_A	394935464	26079	0	899
ValidKnown_A	394935464	394812297	0	0
gen_data_port_assertion.DataFlow_A	394935464	876175	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	876175	0	0
T1	444173	55	0	0
T2	320382	61	0	0
T3	105427	234	0	0
T7	2025	51	0	0
T8	10755	550	0	0
T9	2396	51	0	0
T10	5981	426	0	0
T11	271705	3516	0	0
T12	346736	54	0	0
T13	764524	253	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	876175	0	0
T1	444173	55	0	0
T2	320382	61	0	0
T3	105427	234	0	0
T7	2025	51	0	0
T8	10755	550	0	0
T9	2396	51	0	0
T10	5981	426	0	0
T11	271705	3516	0	0
T12	346736	54	0	0
T13	764524	253	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	876175	0	0
T1	444173	55	0	0
T2	320382	61	0	0
T3	105427	234	0	0
T7	2025	51	0	0
T8	10755	550	0	0
T9	2396	51	0	0
T10	5981	426	0	0
T11	271705	3516	0	0
T12	346736	54	0	0
T13	764524	253	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	330909284	0	0
T1	444173	422974	0	0
T2	320382	266664	0	0
T3	105427	976047	0	0
T7	2025	1	0	0
T8	10755	1	0	0
T9	2396	1	0	0
T10	5981	1	0	0
T11	271705	220057	0	0
T12	346736	288875	0	0
T13	764524	636097	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	876175	0	0
T1	444173	55	0	0
T2	320382	61	0	0
T3	105427	234	0	0
T7	2025	51	0	0
T8	10755	550	0	0
T9	2396	51	0	0
T10	5981	426	0	0
T11	271705	3516	0	0
T12	346736	54	0	0
T13	764524	253	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	876175	0	0
T1	444173	55	0	0
T2	320382	61	0	0
T3	105427	234	0	0
T7	2025	51	0	0
T8	10755	550	0	0
T9	2396	51	0	0
T10	5981	426	0	0
T11	271705	3516	0	0
T12	346736	54	0	0
T13	764524	253	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	12695430	0	0
T1	444173	20333	0	0
T2	320382	282	0	0
T3	105427	76325	0	0
T7	2025	51	0	0
T8	10755	550	0	0
T9	2396	51	0	0
T10	5981	426	0	0
T11	271705	30059	0	0
T12	346736	254	0	0
T13	764524	1134	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	26079	0	899
T4	0	502	0	0
T8	10755	6	0	1
T9	2396	0	0	1
T10	5981	10	0	1
T11	271705	6	0	1
T12	346736	0	0	1
T13	764524	0	0	1
T14	328038	11	0	1
T15	45943	2	0	1
T16	0	9	0	0
T17	0	1	0	0
T18	0	3	0	0
T19	0	78	0	0
T21	63137	0	0	1
T22	286091	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	394812297	0	0
T1	444173	444140	0	0
T2	320382	320343	0	0
T3	105427	105424	0	0
T7	2025	1981	0	0
T8	10755	10705	0	0
T9	2396	2358	0	0
T10	5981	5972	0	0
T11	271705	271255	0	0
T12	346736	346654	0	0
T13	764524	764458	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394935464	876175	0	0
T1	444173	55	0	0
T2	320382	61	0	0
T3	105427	234	0	0
T7	2025	51	0	0
T8	10755	550	0	0
T9	2396	51	0	0
T10	5981	426	0	0
T11	271705	3516	0	0
T12	346736	54	0	0
T13	764524	253	0	0