Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1504680 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 238617 1 T1 95 T3 218 T4 86


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 591773 1 T1 233 T3 509 T4 370
values[0x0] 560071 1 T1 224 T3 514 T4 51
values[0x1] 591453 1 T1 250 T3 488 T4 405


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1162847 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 580450 1 T1 228 T3 499 T4 329


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26988 1 T1 12 T3 46 T4 15
valid_sources[0x01] 27655 1 T3 47 T4 21 T8 4
valid_sources[0x02] 27157 1 T4 18 T8 6 T9 1
valid_sources[0x03] 26446 1 T1 40 T3 13 T4 8
valid_sources[0x04] 27859 1 T1 43 T3 36 T4 9
valid_sources[0x05] 27141 1 T1 7 T4 13 T8 1
valid_sources[0x06] 27920 1 T1 20 T3 41 T4 12
valid_sources[0x07] 28389 1 T3 33 T4 13 T8 2
valid_sources[0x08] 27468 1 T3 63 T4 21 T8 2
valid_sources[0x09] 27968 1 T3 67 T4 15 T8 2
valid_sources[0x0a] 27544 1 T4 12 T8 2 T9 2
valid_sources[0x0b] 27236 1 T1 36 T3 16 T4 10
valid_sources[0x0c] 26857 1 T1 26 T3 29 T4 11
valid_sources[0x0d] 26885 1 T1 12 T3 11 T4 11
valid_sources[0x0e] 26817 1 T1 16 T3 27 T4 12
valid_sources[0x0f] 26727 1 T1 37 T3 15 T4 9
valid_sources[0x10] 28031 1 T4 9 T8 2 T9 4
valid_sources[0x11] 26282 1 T1 33 T3 26 T4 12
valid_sources[0x12] 27193 1 T3 47 T4 12 T8 5
valid_sources[0x13] 27101 1 T1 27 T3 28 T4 14
valid_sources[0x14] 27089 1 T1 12 T3 18 T4 14
valid_sources[0x15] 26645 1 T3 23 T4 10 T8 2
valid_sources[0x16] 27294 1 T1 6 T3 11 T4 7
valid_sources[0x17] 26598 1 T3 42 T4 15 T8 3
valid_sources[0x18] 27561 1 T1 20 T3 22 T4 8
valid_sources[0x19] 28207 1 T3 18 T4 13 T8 1
valid_sources[0x1a] 26801 1 T3 24 T4 12 T8 1
valid_sources[0x1b] 27125 1 T1 11 T4 9 T8 4
valid_sources[0x1c] 27946 1 T3 32 T4 8 T8 3
valid_sources[0x1d] 26567 1 T4 13 T8 2 T9 6
valid_sources[0x1e] 26568 1 T4 10 T8 3 T9 1
valid_sources[0x1f] 26768 1 T1 6 T3 24 T4 16
valid_sources[0x20] 26463 1 T1 24 T3 9 T4 24


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24946 1 T1 15 T3 20 T4 30
values[0x0] all_enables biggest_size 188393 1 T1 70 T3 178 T4 27
values[0x1] all_enables biggest_size 25278 1 T1 10 T3 20 T4 29


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1514275 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 246762 1 T1 103 T3 223 T4 80


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 602045 1 T1 213 T3 519 T4 351
values[0x0] 556027 1 T1 256 T3 502 T4 42
values[0x1] 602965 1 T1 207 T3 499 T4 391


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1162393 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 598644 1 T1 228 T3 515 T4 302


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26951 1 T1 16 T3 36 T4 13
valid_sources[0x01] 27562 1 T3 38 T4 14 T8 3
valid_sources[0x02] 26813 1 T4 11 T10 8 T11 11
valid_sources[0x03] 27530 1 T1 48 T3 11 T4 20
valid_sources[0x04] 27350 1 T1 47 T3 51 T4 16
valid_sources[0x05] 27072 1 T1 18 T4 13 T8 1
valid_sources[0x06] 27722 1 T1 5 T3 66 T4 11
valid_sources[0x07] 27986 1 T3 36 T4 12 T8 3
valid_sources[0x08] 27079 1 T3 64 T4 17 T10 1
valid_sources[0x09] 28078 1 T3 41 T4 13 T8 9
valid_sources[0x0a] 27691 1 T4 13 T8 3 T9 2
valid_sources[0x0b] 27177 1 T1 22 T3 30 T4 14
valid_sources[0x0c] 27654 1 T1 31 T3 40 T4 8
valid_sources[0x0d] 26751 1 T1 5 T3 13 T4 13
valid_sources[0x0e] 27249 1 T1 19 T3 39 T4 11
valid_sources[0x0f] 27698 1 T1 33 T3 29 T4 13
valid_sources[0x10] 27811 1 T4 7 T9 3 T10 22
valid_sources[0x11] 27264 1 T1 26 T3 37 T4 14
valid_sources[0x12] 27717 1 T3 38 T4 12 T9 2
valid_sources[0x13] 27722 1 T1 15 T3 31 T4 10
valid_sources[0x14] 28129 1 T1 19 T3 8 T4 16
valid_sources[0x15] 27468 1 T3 23 T4 7 T8 8
valid_sources[0x16] 27107 1 T1 10 T3 17 T4 10
valid_sources[0x17] 26877 1 T3 34 T4 10 T8 5
valid_sources[0x18] 27790 1 T1 16 T3 38 T4 14
valid_sources[0x19] 28187 1 T3 8 T4 8 T9 37
valid_sources[0x1a] 27452 1 T3 20 T4 13 T9 3
valid_sources[0x1b] 27715 1 T1 10 T4 18 T9 12
valid_sources[0x1c] 27828 1 T3 15 T4 11 T8 3
valid_sources[0x1d] 27270 1 T4 11 T8 3 T10 10
valid_sources[0x1e] 28239 1 T4 10 T9 2 T11 1
valid_sources[0x1f] 27742 1 T1 5 T3 30 T4 14
valid_sources[0x20] 27718 1 T1 32 T3 17 T4 15


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25869 1 T1 9 T3 24 T4 23
values[0x0] all_enables biggest_size 195108 1 T1 85 T3 178 T4 20
values[0x1] all_enables biggest_size 25785 1 T1 9 T3 21 T4 37


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1519195 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 241194 1 T1 91 T3 197 T4 78


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 597911 1 T1 227 T3 482 T4 363
values[0x0] 565027 1 T1 240 T3 451 T4 61
values[0x1] 597451 1 T1 219 T3 513 T4 380


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1173680 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 586709 1 T1 214 T3 468 T4 312


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28262 1 T1 7 T3 36 T4 9
valid_sources[0x01] 27841 1 T3 29 T4 11 T9 3
valid_sources[0x02] 27638 1 T4 14 T9 3 T11 9
valid_sources[0x03] 27011 1 T1 45 T3 11 T4 12
valid_sources[0x04] 26794 1 T1 42 T3 31 T4 13
valid_sources[0x05] 27479 1 T1 17 T4 7 T8 17
valid_sources[0x06] 27596 1 T1 6 T3 60 T4 14
valid_sources[0x07] 28327 1 T3 43 T4 16 T9 1
valid_sources[0x08] 27939 1 T3 62 T4 12 T9 1
valid_sources[0x09] 27937 1 T3 41 T4 11 T8 8
valid_sources[0x0a] 28174 1 T4 6 T9 2 T10 3
valid_sources[0x0b] 27632 1 T1 31 T3 29 T4 12
valid_sources[0x0c] 27718 1 T1 26 T3 39 T4 8
valid_sources[0x0d] 27278 1 T1 14 T3 7 T4 16
valid_sources[0x0e] 28019 1 T1 13 T3 47 T4 11
valid_sources[0x0f] 27412 1 T1 24 T3 13 T4 11
valid_sources[0x10] 27756 1 T4 11 T9 1 T12 1
valid_sources[0x11] 26991 1 T1 24 T3 28 T4 21
valid_sources[0x12] 27368 1 T3 27 T4 12 T9 1
valid_sources[0x13] 27613 1 T1 22 T3 22 T4 13
valid_sources[0x14] 27119 1 T1 13 T3 8 T4 9
valid_sources[0x15] 27074 1 T3 31 T4 10 T9 1
valid_sources[0x16] 27606 1 T1 6 T3 31 T4 7
valid_sources[0x17] 26875 1 T3 40 T4 12 T11 2
valid_sources[0x18] 27247 1 T1 15 T3 40 T4 13
valid_sources[0x19] 28437 1 T3 9 T4 15 T9 1
valid_sources[0x1a] 27011 1 T3 20 T4 22 T8 2
valid_sources[0x1b] 27856 1 T1 8 T4 12 T9 3
valid_sources[0x1c] 27264 1 T3 29 T4 16 T9 4
valid_sources[0x1d] 28271 1 T4 8 T9 3 T12 2
valid_sources[0x1e] 27958 1 T4 16 T9 2 T12 2
valid_sources[0x1f] 26870 1 T1 16 T3 38 T4 12
valid_sources[0x20] 27518 1 T1 30 T3 10 T4 9


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25430 1 T1 5 T3 28 T4 19
values[0x0] all_enables biggest_size 190636 1 T1 79 T3 148 T4 29
values[0x1] all_enables biggest_size 25128 1 T1 7 T3 21 T4 30

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%