Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7635592	0	0
GntImpliesValid_A	2147483647	7635592	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7635592	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	470755805	0	0
ReadyAndValidImplyGrant_A	2147483647	7635592	0	0
ReqAndReadyImplyGrant_A	2147483647	7635592	0	0
ReqImpliesValid_A	2147483647	35403573	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46267	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7635592	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	805512	805248	0	0
T2	6072	4080	0	0
T3	1874856	1874112	0	0
T4	11318136	11317056	0	0
T8	11935104	11934000	0	0
T9	28800	27840	0	0
T10	7542816	7541928	0	0
T11	10354392	10353744	0	0
T12	306456	304608	0	0
T13	1545408	1544832	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7635592	0	0
T1	805512	2060	0	0
T2	6072	0	0	0
T3	1874856	4460	0	0
T4	11318136	45870	0	0
T8	11935104	483	0	0
T9	28800	459	0	0
T10	7542816	369	0	0
T11	10354392	480	0	0
T12	306456	505	0	0
T13	1545408	4342	0	0
T14	0	2302	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7635592	0	0
T1	805512	2060	0	0
T2	6072	0	0	0
T3	1874856	4460	0	0
T4	11318136	45870	0	0
T8	11935104	483	0	0
T9	28800	459	0	0
T10	7542816	369	0	0
T11	10354392	480	0	0
T12	306456	505	0	0
T13	1545408	4342	0	0
T14	0	2302	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	805512	805248	0	0
T2	6072	4080	0	0
T3	1874856	1874112	0	0
T4	11318136	11317056	0	0
T8	11935104	11934000	0	0
T9	28800	27840	0	0
T10	7542816	7541928	0	0
T11	10354392	10353744	0	0
T12	306456	304608	0	0
T13	1545408	1544832	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	805512	805248	0	0
T2	6072	4080	0	0
T3	1874856	1874112	0	0
T4	11318136	11317056	0	0
T8	11935104	11934000	0	0
T9	28800	27840	0	0
T10	7542816	7541928	0	0
T11	10354392	10353744	0	0
T12	306456	304608	0	0
T13	1545408	1544832	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7635592	0	0
T1	805512	2060	0	0
T2	6072	0	0	0
T3	1874856	4460	0	0
T4	11318136	45870	0	0
T8	11935104	483	0	0
T9	28800	459	0	0
T10	7542816	369	0	0
T11	10354392	480	0	0
T12	306456	505	0	0
T13	1545408	4342	0	0
T14	0	2302	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	470755805	0	0
T1	805512	43203	0	0
T2	6072	172	0	0
T3	1874856	97636	0	0
T4	11318136	654188	0	0
T8	11935104	621003	0	0
T9	28800	753	0	0
T10	7542816	263251	0	0
T11	10354392	547094	0	0
T12	306456	15796	0	0
T13	1545408	85319	0	0
T14	0	2082	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7635592	0	0
T1	805512	2060	0	0
T2	6072	0	0	0
T3	1874856	4460	0	0
T4	11318136	45870	0	0
T8	11935104	483	0	0
T9	28800	459	0	0
T10	7542816	369	0	0
T11	10354392	480	0	0
T12	306456	505	0	0
T13	1545408	4342	0	0
T14	0	2302	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7635592	0	0
T1	805512	2060	0	0
T2	6072	0	0	0
T3	1874856	4460	0	0
T4	11318136	45870	0	0
T8	11935104	483	0	0
T9	28800	459	0	0
T10	7542816	369	0	0
T11	10354392	480	0	0
T12	306456	505	0	0
T13	1545408	4342	0	0
T14	0	2302	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35403573	0	0
T1	805512	3545	0	0
T2	6072	0	0	0
T3	1874856	8389	0	0
T4	11318136	139810	0	0
T8	11935104	36084	0	0
T9	28800	536	0	0
T10	7542816	688	0	0
T11	10354392	26743	0	0
T12	306456	1069	0	0
T13	1545408	8889	0	0
T14	0	3814	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46267	0	21600
T3	78119	1	0	1
T4	943178	10	0	2
T8	994592	0	0	2
T9	2400	8	0	2
T10	628568	0	0	2
T11	862866	0	0	2
T12	25538	0	0	2
T13	128784	1	0	2
T14	1010382	0	0	2
T15	10562	15	0	1
T16	0	12	0	0
T17	0	37	0	0
T18	0	6	0	0
T19	0	1	0	0
T20	0	38	0	0
T21	0	23	0	0
T22	0	2	0	0
T23	221062	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	805512	805248	0	0
T2	6072	4080	0	0
T3	1874856	1874112	0	0
T4	11318136	11317056	0	0
T8	11935104	11934000	0	0
T9	28800	27840	0	0
T10	7542816	7541928	0	0
T11	10354392	10353744	0	0
T12	306456	304608	0	0
T13	1545408	1544832	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7635592	0	0
T1	805512	2060	0	0
T2	6072	0	0	0
T3	1874856	4460	0	0
T4	11318136	45870	0	0
T8	11935104	483	0	0
T9	28800	459	0	0
T10	7542816	369	0	0
T11	10354392	480	0	0
T12	306456	505	0	0
T13	1545408	4342	0	0
T14	0	2302	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	846178	0	0
GntImpliesValid_A	429068271	846178	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	846178	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	12620805	0	0
ReadyAndValidImplyGrant_A	429068271	846178	0	0
ReqAndReadyImplyGrant_A	429068271	846178	0	0
ReqImpliesValid_A	429068271	2478172	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	846178	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	846178	0	0
T1	33563	251	0	0
T2	253	0	0	0
T3	78119	498	0	0
T4	471589	5222	0	0
T8	497296	54	0	0
T9	1200	52	0	0
T10	314284	45	0	0
T11	431433	47	0	0
T12	12769	50	0	0
T13	64392	493	0	0
T14	0	277	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	846178	0	0
T1	33563	251	0	0
T2	253	0	0	0
T3	78119	498	0	0
T4	471589	5222	0	0
T8	497296	54	0	0
T9	1200	52	0	0
T10	314284	45	0	0
T11	431433	47	0	0
T12	12769	50	0	0
T13	64392	493	0	0
T14	0	277	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	846178	0	0
T1	33563	251	0	0
T2	253	0	0	0
T3	78119	498	0	0
T4	471589	5222	0	0
T8	497296	54	0	0
T9	1200	52	0	0
T10	314284	45	0	0
T11	431433	47	0	0
T12	12769	50	0	0
T13	64392	493	0	0
T14	0	277	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	12620805	0	0
T1	33563	1893	0	0
T2	253	1	0	0
T3	78119	3869	0	0
T4	471589	36031	0	0
T8	497296	17363	0	0
T9	1200	44	0	0
T10	314284	179	0	0
T11	431433	13820	0	0
T12	12769	336	0	0
T13	64392	3399	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	846178	0	0
T1	33563	251	0	0
T2	253	0	0	0
T3	78119	498	0	0
T4	471589	5222	0	0
T8	497296	54	0	0
T9	1200	52	0	0
T10	314284	45	0	0
T11	431433	47	0	0
T12	12769	50	0	0
T13	64392	493	0	0
T14	0	277	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	846178	0	0
T1	33563	251	0	0
T2	253	0	0	0
T3	78119	498	0	0
T4	471589	5222	0	0
T8	497296	54	0	0
T9	1200	52	0	0
T10	314284	45	0	0
T11	431433	47	0	0
T12	12769	50	0	0
T13	64392	493	0	0
T14	0	277	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	2478172	0	0
T1	33563	294	0	0
T2	253	0	0	0
T3	78119	586	0	0
T4	471589	12570	0	0
T8	497296	1710	0	0
T9	1200	61	0	0
T10	314284	47	0	0
T11	431433	480	0	0
T12	12769	65	0	0
T13	64392	775	0	0
T14	0	409	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	846178	0	0
T1	33563	251	0	0
T2	253	0	0	0
T3	78119	498	0	0
T4	471589	5222	0	0
T8	497296	54	0	0
T9	1200	52	0	0
T10	314284	45	0	0
T11	431433	47	0	0
T12	12769	50	0	0
T13	64392	493	0	0
T14	0	277	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	842215	0	0
GntImpliesValid_A	429068271	842215	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	842215	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	12521238	0	0
ReadyAndValidImplyGrant_A	429068271	842215	0	0
ReqAndReadyImplyGrant_A	429068271	842215	0	0
ReqImpliesValid_A	429068271	2546419	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	842215	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	842215	0	0
T1	33563	220	0	0
T2	253	0	0	0
T3	78119	525	0	0
T4	471589	4561	0	0
T8	497296	45	0	0
T9	1200	68	0	0
T10	314284	51	0	0
T11	431433	58	0	0
T12	12769	55	0	0
T13	64392	504	0	0
T14	0	273	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	842215	0	0
T1	33563	220	0	0
T2	253	0	0	0
T3	78119	525	0	0
T4	471589	4561	0	0
T8	497296	45	0	0
T9	1200	68	0	0
T10	314284	51	0	0
T11	431433	58	0	0
T12	12769	55	0	0
T13	64392	504	0	0
T14	0	273	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	842215	0	0
T1	33563	220	0	0
T2	253	0	0	0
T3	78119	525	0	0
T4	471589	4561	0	0
T8	497296	45	0	0
T9	1200	68	0	0
T10	314284	51	0	0
T11	431433	58	0	0
T12	12769	55	0	0
T13	64392	504	0	0
T14	0	273	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	12521238	0	0
T1	33563	1722	0	0
T2	253	1	0	0
T3	78119	4197	0	0
T4	471589	33943	0	0
T8	497296	15086	0	0
T9	1200	51	0	0
T10	314284	181	0	0
T11	431433	17209	0	0
T12	12769	434	0	0
T13	64392	3448	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	842215	0	0
T1	33563	220	0	0
T2	253	0	0	0
T3	78119	525	0	0
T4	471589	4561	0	0
T8	497296	45	0	0
T9	1200	68	0	0
T10	314284	51	0	0
T11	431433	58	0	0
T12	12769	55	0	0
T13	64392	504	0	0
T14	0	273	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	842215	0	0
T1	33563	220	0	0
T2	253	0	0	0
T3	78119	525	0	0
T4	471589	4561	0	0
T8	497296	45	0	0
T9	1200	68	0	0
T10	314284	51	0	0
T11	431433	58	0	0
T12	12769	55	0	0
T13	64392	504	0	0
T14	0	273	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	2546419	0	0
T1	33563	261	0	0
T2	253	0	0	0
T3	78119	602	0	0
T4	471589	7092	0	0
T8	497296	2246	0	0
T9	1200	86	0	0
T10	314284	84	0	0
T11	431433	2464	0	0
T12	12769	95	0	0
T13	64392	677	0	0
T14	0	417	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	842215	0	0
T1	33563	220	0	0
T2	253	0	0	0
T3	78119	525	0	0
T4	471589	4561	0	0
T8	497296	45	0	0
T9	1200	68	0	0
T10	314284	51	0	0
T11	431433	58	0	0
T12	12769	55	0	0
T13	64392	504	0	0
T14	0	273	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	205831	0	0
GntImpliesValid_A	429068271	205831	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	205831	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3201845	0	0
ReadyAndValidImplyGrant_A	429068271	205831	0	0
ReqAndReadyImplyGrant_A	429068271	205831	0	0
ReqImpliesValid_A	429068271	585549	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	205831	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	205831	0	0
T1	33563	47	0	0
T2	253	0	0	0
T3	78119	126	0	0
T4	471589	809	0	0
T8	497296	16	0	0
T9	1200	15	0	0
T10	314284	11	0	0
T11	431433	10	0	0
T12	12769	22	0	0
T13	64392	110	0	0
T14	0	79	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	205831	0	0
T1	33563	47	0	0
T2	253	0	0	0
T3	78119	126	0	0
T4	471589	809	0	0
T8	497296	16	0	0
T9	1200	15	0	0
T10	314284	11	0	0
T11	431433	10	0	0
T12	12769	22	0	0
T13	64392	110	0	0
T14	0	79	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	205831	0	0
T1	33563	47	0	0
T2	253	0	0	0
T3	78119	126	0	0
T4	471589	809	0	0
T8	497296	16	0	0
T9	1200	15	0	0
T10	314284	11	0	0
T11	431433	10	0	0
T12	12769	22	0	0
T13	64392	110	0	0
T14	0	79	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3201845	0	0
T1	33563	372	0	0
T2	253	1	0	0
T3	78119	913	0	0
T4	471589	5846	0	0
T8	497296	4947	0	0
T9	1200	15	0	0
T10	314284	36	0	0
T11	431433	2713	0	0
T12	12769	185	0	0
T13	64392	804	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	205831	0	0
T1	33563	47	0	0
T2	253	0	0	0
T3	78119	126	0	0
T4	471589	809	0	0
T8	497296	16	0	0
T9	1200	15	0	0
T10	314284	11	0	0
T11	431433	10	0	0
T12	12769	22	0	0
T13	64392	110	0	0
T14	0	79	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	205831	0	0
T1	33563	47	0	0
T2	253	0	0	0
T3	78119	126	0	0
T4	471589	809	0	0
T8	497296	16	0	0
T9	1200	15	0	0
T10	314284	11	0	0
T11	431433	10	0	0
T12	12769	22	0	0
T13	64392	110	0	0
T14	0	79	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	585549	0	0
T1	33563	47	0	0
T2	253	0	0	0
T3	78119	141	0	0
T4	471589	926	0	0
T8	497296	714	0	0
T9	1200	16	0	0
T10	314284	11	0	0
T11	431433	19	0	0
T12	12769	25	0	0
T13	64392	122	0	0
T14	0	82	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	205831	0	0
T1	33563	47	0	0
T2	253	0	0	0
T3	78119	126	0	0
T4	471589	809	0	0
T8	497296	16	0	0
T9	1200	15	0	0
T10	314284	11	0	0
T11	431433	10	0	0
T12	12769	22	0	0
T13	64392	110	0	0
T14	0	79	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	221277	0	0
GntImpliesValid_A	429068271	221277	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	221277	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3223453	0	0
ReadyAndValidImplyGrant_A	429068271	221277	0	0
ReqAndReadyImplyGrant_A	429068271	221277	0	0
ReqImpliesValid_A	429068271	654341	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	221277	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	221277	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1284	0	0
T8	497296	15	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	9	0	0
T12	12769	30	0	0
T13	64392	108	0	0
T14	0	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	221277	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1284	0	0
T8	497296	15	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	9	0	0
T12	12769	30	0	0
T13	64392	108	0	0
T14	0	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	221277	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1284	0	0
T8	497296	15	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	9	0	0
T12	12769	30	0	0
T13	64392	108	0	0
T14	0	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3223453	0	0
T1	33563	477	0	0
T2	253	1	0	0
T3	78119	839	0	0
T4	471589	8710	0	0
T8	497296	5814	0	0
T9	1200	10	0	0
T10	314284	38	0	0
T11	431433	2428	0	0
T12	12769	256	0	0
T13	64392	720	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	221277	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1284	0	0
T8	497296	15	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	9	0	0
T12	12769	30	0	0
T13	64392	108	0	0
T14	0	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	221277	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1284	0	0
T8	497296	15	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	9	0	0
T12	12769	30	0	0
T13	64392	108	0	0
T14	0	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	654341	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	120	0	0
T4	471589	3212	0	0
T8	497296	110	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	9	0	0
T12	12769	30	0	0
T13	64392	167	0	0
T14	0	70	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	221277	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1284	0	0
T8	497296	15	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	9	0	0
T12	12769	30	0	0
T13	64392	108	0	0
T14	0	60	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T4,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T4,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	207759	0	0
GntImpliesValid_A	429068271	207759	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	207759	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	5032142	0	0
ReadyAndValidImplyGrant_A	429068271	207759	0	0
ReqAndReadyImplyGrant_A	429068271	207759	0	0
ReqImpliesValid_A	429068271	1118373	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	207759	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207759	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	144	0	0
T4	471589	839	0	0
T8	497296	11	0	0
T9	1200	12	0	0
T10	314284	8	0	0
T11	431433	15	0	0
T12	12769	10	0	0
T13	64392	112	0	0
T14	0	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207759	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	144	0	0
T4	471589	839	0	0
T8	497296	11	0	0
T9	1200	12	0	0
T10	314284	8	0	0
T11	431433	15	0	0
T12	12769	10	0	0
T13	64392	112	0	0
T14	0	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207759	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	144	0	0
T4	471589	839	0	0
T8	497296	11	0	0
T9	1200	12	0	0
T10	314284	8	0	0
T11	431433	15	0	0
T12	12769	10	0	0
T13	64392	112	0	0
T14	0	53	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	5032142	0	0
T1	33563	443	0	0
T2	253	0	0	0
T3	78119	1506	0	0
T4	471589	3470	0	0
T8	497296	2435	0	0
T9	1200	174	0	0
T10	314284	80	0	0
T11	431433	2581	0	0
T12	12769	116	0	0
T13	64392	972	0	0
T14	0	443	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207759	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	144	0	0
T4	471589	839	0	0
T8	497296	11	0	0
T9	1200	12	0	0
T10	314284	8	0	0
T11	431433	15	0	0
T12	12769	10	0	0
T13	64392	112	0	0
T14	0	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207759	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	144	0	0
T4	471589	839	0	0
T8	497296	11	0	0
T9	1200	12	0	0
T10	314284	8	0	0
T11	431433	15	0	0
T12	12769	10	0	0
T13	64392	112	0	0
T14	0	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	1118373	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	144	0	0
T4	471589	889	0	0
T8	497296	307	0	0
T9	1200	29	0	0
T10	314284	8	0	0
T11	431433	15	0	0
T12	12769	10	0	0
T13	64392	124	0	0
T14	0	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207759	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	144	0	0
T4	471589	839	0	0
T8	497296	11	0	0
T9	1200	12	0	0
T10	314284	8	0	0
T11	431433	15	0	0
T12	12769	10	0	0
T13	64392	112	0	0
T14	0	53	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	207384	0	0
GntImpliesValid_A	429068271	207384	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	207384	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	5656794	0	0
ReadyAndValidImplyGrant_A	429068271	207384	0	0
ReqAndReadyImplyGrant_A	429068271	207384	0	0
ReqImpliesValid_A	429068271	1236159	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	207384	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207384	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	132	0	0
T4	471589	1284	0	0
T8	497296	14	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	16	0	0
T13	64392	116	0	0
T14	0	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207384	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	132	0	0
T4	471589	1284	0	0
T8	497296	14	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	16	0	0
T13	64392	116	0	0
T14	0	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207384	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	132	0	0
T4	471589	1284	0	0
T8	497296	14	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	16	0	0
T13	64392	116	0	0
T14	0	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	5656794	0	0
T1	33563	473	0	0
T2	253	0	0	0
T3	78119	846	0	0
T4	471589	4906	0	0
T8	497296	2300	0	0
T9	1200	173	0	0
T10	314284	71	0	0
T11	431433	9598	0	0
T12	12769	299	0	0
T13	64392	2500	0	0
T14	0	424	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207384	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	132	0	0
T4	471589	1284	0	0
T8	497296	14	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	16	0	0
T13	64392	116	0	0
T14	0	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207384	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	132	0	0
T4	471589	1284	0	0
T8	497296	14	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	16	0	0
T13	64392	116	0	0
T14	0	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	1236159	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	137	0	0
T4	471589	1877	0	0
T8	497296	14	0	0
T9	1200	37	0	0
T10	314284	9	0	0
T11	431433	1349	0	0
T12	12769	33	0	0
T13	64392	185	0	0
T14	0	49	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	207384	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	132	0	0
T4	471589	1284	0	0
T8	497296	14	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	16	0	0
T13	64392	116	0	0
T14	0	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T10
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T3,T4,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	209964	0	0
GntImpliesValid_A	429068271	209964	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	209964	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	4927308	0	0
ReadyAndValidImplyGrant_A	429068271	209964	0	0
ReqAndReadyImplyGrant_A	429068271	209964	0	0
ReqImpliesValid_A	429068271	1110653	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	209964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209964	0	0
T1	33563	60	0	0
T2	253	0	0	0
T3	78119	108	0	0
T4	471589	2281	0	0
T8	497296	10	0	0
T9	1200	9	0	0
T10	314284	15	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	115	0	0
T14	0	71	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209964	0	0
T1	33563	60	0	0
T2	253	0	0	0
T3	78119	108	0	0
T4	471589	2281	0	0
T8	497296	10	0	0
T9	1200	9	0	0
T10	314284	15	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	115	0	0
T14	0	71	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209964	0	0
T1	33563	60	0	0
T2	253	0	0	0
T3	78119	108	0	0
T4	471589	2281	0	0
T8	497296	10	0	0
T9	1200	9	0	0
T10	314284	15	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	115	0	0
T14	0	71	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	4927308	0	0
T1	33563	372	0	0
T2	253	0	0	0
T3	78119	802	0	0
T4	471589	11129	0	0
T8	497296	2142	0	0
T9	1200	91	0	0
T10	314284	352	0	0
T11	431433	4128	0	0
T12	12769	705	0	0
T13	64392	877	0	0
T14	0	651	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209964	0	0
T1	33563	60	0	0
T2	253	0	0	0
T3	78119	108	0	0
T4	471589	2281	0	0
T8	497296	10	0	0
T9	1200	9	0	0
T10	314284	15	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	115	0	0
T14	0	71	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209964	0	0
T1	33563	60	0	0
T2	253	0	0	0
T3	78119	108	0	0
T4	471589	2281	0	0
T8	497296	10	0	0
T9	1200	9	0	0
T10	314284	15	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	115	0	0
T14	0	71	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	1110653	0	0
T1	33563	60	0	0
T2	253	0	0	0
T3	78119	112	0	0
T4	471589	5351	0	0
T8	497296	10	0	0
T9	1200	9	0	0
T10	314284	89	0	0
T11	431433	13	0	0
T12	12769	43	0	0
T13	64392	157	0	0
T14	0	129	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209964	0	0
T1	33563	60	0	0
T2	253	0	0	0
T3	78119	108	0	0
T4	471589	2281	0	0
T8	497296	10	0	0
T9	1200	9	0	0
T10	314284	15	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	115	0	0
T14	0	71	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T11
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T4,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T4,T8,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	214073	0	0
GntImpliesValid_A	429068271	214073	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	214073	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	5916416	0	0
ReadyAndValidImplyGrant_A	429068271	214073	0	0
ReqAndReadyImplyGrant_A	429068271	214073	0	0
ReqImpliesValid_A	429068271	1226813	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	214073	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	214073	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	112	0	0
T4	471589	880	0	0
T8	497296	10	0	0
T9	1200	5	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	21	0	0
T13	64392	120	0	0
T14	0	51	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	214073	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	112	0	0
T4	471589	880	0	0
T8	497296	10	0	0
T9	1200	5	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	21	0	0
T13	64392	120	0	0
T14	0	51	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	214073	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	112	0	0
T4	471589	880	0	0
T8	497296	10	0	0
T9	1200	5	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	21	0	0
T13	64392	120	0	0
T14	0	51	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	5916416	0	0
T1	33563	275	0	0
T2	253	0	0	0
T3	78119	1075	0	0
T4	471589	8059	0	0
T8	497296	15933	0	0
T9	1200	26	0	0
T10	314284	131	0	0
T11	431433	6986	0	0
T12	12769	450	0	0
T13	64392	946	0	0
T14	0	564	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	214073	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	112	0	0
T4	471589	880	0	0
T8	497296	10	0	0
T9	1200	5	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	21	0	0
T13	64392	120	0	0
T14	0	51	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	214073	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	112	0	0
T4	471589	880	0	0
T8	497296	10	0	0
T9	1200	5	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	21	0	0
T13	64392	120	0	0
T14	0	51	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	1226813	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	112	0	0
T4	471589	1089	0	0
T8	497296	2927	0	0
T9	1200	5	0	0
T10	314284	9	0	0
T11	431433	498	0	0
T12	12769	60	0	0
T13	64392	157	0	0
T14	0	102	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	214073	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	112	0	0
T4	471589	880	0	0
T8	497296	10	0	0
T9	1200	5	0	0
T10	314284	9	0	0
T11	431433	12	0	0
T12	12769	21	0	0
T13	64392	120	0	0
T14	0	51	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T11
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	217163	0	0
GntImpliesValid_A	429068271	217163	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	217163	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3176989	0	0
ReadyAndValidImplyGrant_A	429068271	217163	0	0
ReqAndReadyImplyGrant_A	429068271	217163	0	0
ReqImpliesValid_A	429068271	666500	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	217163	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217163	0	0
T1	33563	49	0	0
T2	253	0	0	0
T3	78119	119	0	0
T4	471589	1734	0	0
T8	497296	10	0	0
T9	1200	10	0	0
T10	314284	5	0	0
T11	431433	14	0	0
T12	12769	16	0	0
T13	64392	117	0	0
T14	0	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217163	0	0
T1	33563	49	0	0
T2	253	0	0	0
T3	78119	119	0	0
T4	471589	1734	0	0
T8	497296	10	0	0
T9	1200	10	0	0
T10	314284	5	0	0
T11	431433	14	0	0
T12	12769	16	0	0
T13	64392	117	0	0
T14	0	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217163	0	0
T1	33563	49	0	0
T2	253	0	0	0
T3	78119	119	0	0
T4	471589	1734	0	0
T8	497296	10	0	0
T9	1200	10	0	0
T10	314284	5	0	0
T11	431433	14	0	0
T12	12769	16	0	0
T13	64392	117	0	0
T14	0	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3176989	0	0
T1	33563	385	0	0
T2	253	1	0	0
T3	78119	998	0	0
T4	471589	9260	0	0
T8	497296	3458	0	0
T9	1200	11	0	0
T10	314284	20	0	0
T11	431433	4618	0	0
T12	12769	132	0	0
T13	64392	936	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217163	0	0
T1	33563	49	0	0
T2	253	0	0	0
T3	78119	119	0	0
T4	471589	1734	0	0
T8	497296	10	0	0
T9	1200	10	0	0
T10	314284	5	0	0
T11	431433	14	0	0
T12	12769	16	0	0
T13	64392	117	0	0
T14	0	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217163	0	0
T1	33563	49	0	0
T2	253	0	0	0
T3	78119	119	0	0
T4	471589	1734	0	0
T8	497296	10	0	0
T9	1200	10	0	0
T10	314284	5	0	0
T11	431433	14	0	0
T12	12769	16	0	0
T13	64392	117	0	0
T14	0	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	666500	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	119	0	0
T4	471589	7780	0	0
T8	497296	10	0	0
T9	1200	10	0	0
T10	314284	5	0	0
T11	431433	33	0	0
T12	12769	16	0	0
T13	64392	125	0	0
T14	0	55	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217163	0	0
T1	33563	49	0	0
T2	253	0	0	0
T3	78119	119	0	0
T4	471589	1734	0	0
T8	497296	10	0	0
T9	1200	10	0	0
T10	314284	5	0	0
T11	431433	14	0	0
T12	12769	16	0	0
T13	64392	117	0	0
T14	0	54	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T9
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	208047	0	0
GntImpliesValid_A	429068271	208047	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	208047	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3109848	0	0
ReadyAndValidImplyGrant_A	429068271	208047	0	0
ReqAndReadyImplyGrant_A	429068271	208047	0	0
ReqImpliesValid_A	429068271	575954	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	208047	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208047	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1304	0	0
T8	497296	16	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	131	0	0
T14	0	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208047	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1304	0	0
T8	497296	16	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	131	0	0
T14	0	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208047	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1304	0	0
T8	497296	16	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	131	0	0
T14	0	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3109848	0	0
T1	33563	463	0	0
T2	253	1	0	0
T3	78119	775	0	0
T4	471589	7285	0	0
T8	497296	5783	0	0
T9	1200	16	0	0
T10	314284	44	0	0
T11	431433	4292	0	0
T12	12769	100	0	0
T13	64392	1046	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208047	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1304	0	0
T8	497296	16	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	131	0	0
T14	0	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208047	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1304	0	0
T8	497296	16	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	131	0	0
T14	0	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	575954	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	123	0	0
T4	471589	3014	0	0
T8	497296	16	0	0
T9	1200	17	0	0
T10	314284	9	0	0
T11	431433	13	0	0
T12	12769	22	0	0
T13	64392	160	0	0
T14	0	69	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208047	0	0
T1	33563	59	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1304	0	0
T8	497296	16	0	0
T9	1200	16	0	0
T10	314284	9	0	0
T11	431433	13	0	0
T12	12769	12	0	0
T13	64392	131	0	0
T14	0	67	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T11,T12
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T4,T11,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	200987	0	0
GntImpliesValid_A	429068271	200987	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	200987	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3166542	0	0
ReadyAndValidImplyGrant_A	429068271	200987	0	0
ReqAndReadyImplyGrant_A	429068271	200987	0	0
ReqImpliesValid_A	429068271	577055	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	200987	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	200987	0	0
T1	33563	56	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1359	0	0
T8	497296	10	0	0
T9	1200	12	0	0
T10	314284	5	0	0
T11	431433	11	0	0
T12	12769	10	0	0
T13	64392	122	0	0
T14	0	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	200987	0	0
T1	33563	56	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1359	0	0
T8	497296	10	0	0
T9	1200	12	0	0
T10	314284	5	0	0
T11	431433	11	0	0
T12	12769	10	0	0
T13	64392	122	0	0
T14	0	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	200987	0	0
T1	33563	56	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1359	0	0
T8	497296	10	0	0
T9	1200	12	0	0
T10	314284	5	0	0
T11	431433	11	0	0
T12	12769	10	0	0
T13	64392	122	0	0
T14	0	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3166542	0	0
T1	33563	503	0	0
T2	253	1	0	0
T3	78119	942	0	0
T4	471589	8111	0	0
T8	497296	3418	0	0
T9	1200	13	0	0
T10	314284	37	0	0
T11	431433	3224	0	0
T12	12769	61	0	0
T13	64392	969	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	200987	0	0
T1	33563	56	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1359	0	0
T8	497296	10	0	0
T9	1200	12	0	0
T10	314284	5	0	0
T11	431433	11	0	0
T12	12769	10	0	0
T13	64392	122	0	0
T14	0	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	200987	0	0
T1	33563	56	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1359	0	0
T8	497296	10	0	0
T9	1200	12	0	0
T10	314284	5	0	0
T11	431433	11	0	0
T12	12769	10	0	0
T13	64392	122	0	0
T14	0	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	577055	0	0
T1	33563	56	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	2763	0	0
T8	497296	10	0	0
T9	1200	12	0	0
T10	314284	5	0	0
T11	431433	72	0	0
T12	12769	20	0	0
T13	64392	175	0	0
T14	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	200987	0	0
T1	33563	56	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1359	0	0
T8	497296	10	0	0
T9	1200	12	0	0
T10	314284	5	0	0
T11	431433	11	0	0
T12	12769	10	0	0
T13	64392	122	0	0
T14	0	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T11
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T4,T8,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	217081	0	0
GntImpliesValid_A	429068271	217081	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	217081	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3206152	0	0
ReadyAndValidImplyGrant_A	429068271	217081	0	0
ReqAndReadyImplyGrant_A	429068271	217081	0	0
ReqImpliesValid_A	429068271	623629	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	217081	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217081	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1274	0	0
T8	497296	13	0	0
T9	1200	12	0	0
T10	314284	7	0	0
T11	431433	17	0	0
T12	12769	18	0	0
T13	64392	108	0	0
T14	0	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217081	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1274	0	0
T8	497296	13	0	0
T9	1200	12	0	0
T10	314284	7	0	0
T11	431433	17	0	0
T12	12769	18	0	0
T13	64392	108	0	0
T14	0	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217081	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1274	0	0
T8	497296	13	0	0
T9	1200	12	0	0
T10	314284	7	0	0
T11	431433	17	0	0
T12	12769	18	0	0
T13	64392	108	0	0
T14	0	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3206152	0	0
T1	33563	510	0	0
T2	253	1	0	0
T3	78119	854	0	0
T4	471589	8426	0	0
T8	497296	3955	0	0
T9	1200	13	0	0
T10	314284	32	0	0
T11	431433	5275	0	0
T12	12769	140	0	0
T13	64392	808	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217081	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1274	0	0
T8	497296	13	0	0
T9	1200	12	0	0
T10	314284	7	0	0
T11	431433	17	0	0
T12	12769	18	0	0
T13	64392	108	0	0
T14	0	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217081	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1274	0	0
T8	497296	13	0	0
T9	1200	12	0	0
T10	314284	7	0	0
T11	431433	17	0	0
T12	12769	18	0	0
T13	64392	108	0	0
T14	0	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	623629	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	3289	0	0
T8	497296	285	0	0
T9	1200	12	0	0
T10	314284	7	0	0
T11	431433	443	0	0
T12	12769	37	0	0
T13	64392	117	0	0
T14	0	77	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217081	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	1274	0	0
T8	497296	13	0	0
T9	1200	12	0	0
T10	314284	7	0	0
T11	431433	17	0	0
T12	12769	18	0	0
T13	64392	108	0	0
T14	0	67	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	217097	0	0
GntImpliesValid_A	429068271	217097	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	217097	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3214741	0	0
ReadyAndValidImplyGrant_A	429068271	217097	0	0
ReqAndReadyImplyGrant_A	429068271	217097	0	0
ReqImpliesValid_A	429068271	626550	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	217097	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217097	0	0
T1	33563	62	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1654	0	0
T8	497296	12	0	0
T9	1200	11	0	0
T10	314284	11	0	0
T11	431433	20	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	56	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217097	0	0
T1	33563	62	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1654	0	0
T8	497296	12	0	0
T9	1200	11	0	0
T10	314284	11	0	0
T11	431433	20	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	56	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217097	0	0
T1	33563	62	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1654	0	0
T8	497296	12	0	0
T9	1200	11	0	0
T10	314284	11	0	0
T11	431433	20	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	56	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3214741	0	0
T1	33563	528	0	0
T2	253	1	0	0
T3	78119	883	0	0
T4	471589	10238	0	0
T8	497296	2137	0	0
T9	1200	10	0	0
T10	314284	42	0	0
T11	431433	5383	0	0
T12	12769	85	0	0
T13	64392	852	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217097	0	0
T1	33563	62	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1654	0	0
T8	497296	12	0	0
T9	1200	11	0	0
T10	314284	11	0	0
T11	431433	20	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	56	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217097	0	0
T1	33563	62	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1654	0	0
T8	497296	12	0	0
T9	1200	11	0	0
T10	314284	11	0	0
T11	431433	20	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	56	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	626550	0	0
T1	33563	73	0	0
T2	253	0	0	0
T3	78119	119	0	0
T4	471589	6364	0	0
T8	497296	12	0	0
T9	1200	13	0	0
T10	314284	11	0	0
T11	431433	63	0	0
T12	12769	16	0	0
T13	64392	164	0	0
T14	0	78	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	217097	0	0
T1	33563	62	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	1654	0	0
T8	497296	12	0	0
T9	1200	11	0	0
T10	314284	11	0	0
T11	431433	20	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	56	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	215953	0	0
GntImpliesValid_A	429068271	215953	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	215953	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3165399	0	0
ReadyAndValidImplyGrant_A	429068271	215953	0	0
ReqAndReadyImplyGrant_A	429068271	215953	0	0
ReqImpliesValid_A	429068271	610674	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	215953	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	215953	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1871	0	0
T8	497296	16	0	0
T9	1200	11	0	0
T10	314284	4	0	0
T11	431433	9	0	0
T12	12769	12	0	0
T13	64392	122	0	0
T14	0	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	215953	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1871	0	0
T8	497296	16	0	0
T9	1200	11	0	0
T10	314284	4	0	0
T11	431433	9	0	0
T12	12769	12	0	0
T13	64392	122	0	0
T14	0	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	215953	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1871	0	0
T8	497296	16	0	0
T9	1200	11	0	0
T10	314284	4	0	0
T11	431433	9	0	0
T12	12769	12	0	0
T13	64392	122	0	0
T14	0	66	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3165399	0	0
T1	33563	432	0	0
T2	253	1	0	0
T3	78119	898	0	0
T4	471589	8666	0	0
T8	497296	3396	0	0
T9	1200	12	0	0
T10	314284	21	0	0
T11	431433	3069	0	0
T12	12769	122	0	0
T13	64392	814	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	215953	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1871	0	0
T8	497296	16	0	0
T9	1200	11	0	0
T10	314284	4	0	0
T11	431433	9	0	0
T12	12769	12	0	0
T13	64392	122	0	0
T14	0	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	215953	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1871	0	0
T8	497296	16	0	0
T9	1200	11	0	0
T10	314284	4	0	0
T11	431433	9	0	0
T12	12769	12	0	0
T13	64392	122	0	0
T14	0	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	610674	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	117	0	0
T4	471589	4931	0	0
T8	497296	16	0	0
T9	1200	11	0	0
T10	314284	4	0	0
T11	431433	9	0	0
T12	12769	13	0	0
T13	64392	166	0	0
T14	0	71	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	215953	0	0
T1	33563	53	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1871	0	0
T8	497296	16	0	0
T9	1200	11	0	0
T10	314284	4	0	0
T11	431433	9	0	0
T12	12769	12	0	0
T13	64392	122	0	0
T14	0	66	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	213223	0	0
GntImpliesValid_A	429068271	213223	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	213223	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3156517	0	0
ReadyAndValidImplyGrant_A	429068271	213223	0	0
ReqAndReadyImplyGrant_A	429068271	213223	0	0
ReqImpliesValid_A	429068271	633776	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	213223	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	213223	0	0
T1	33563	67	0	0
T2	253	0	0	0
T3	78119	138	0	0
T4	471589	830	0	0
T8	497296	18	0	0
T9	1200	14	0	0
T10	314284	11	0	0
T11	431433	14	0	0
T12	12769	9	0	0
T13	64392	127	0	0
T14	0	56	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	213223	0	0
T1	33563	67	0	0
T2	253	0	0	0
T3	78119	138	0	0
T4	471589	830	0	0
T8	497296	18	0	0
T9	1200	14	0	0
T10	314284	11	0	0
T11	431433	14	0	0
T12	12769	9	0	0
T13	64392	127	0	0
T14	0	56	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	213223	0	0
T1	33563	67	0	0
T2	253	0	0	0
T3	78119	138	0	0
T4	471589	830	0	0
T8	497296	18	0	0
T9	1200	14	0	0
T10	314284	11	0	0
T11	431433	14	0	0
T12	12769	9	0	0
T13	64392	127	0	0
T14	0	56	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3156517	0	0
T1	33563	458	0	0
T2	253	1	0	0
T3	78119	1041	0	0
T4	471589	6431	0	0
T8	497296	7896	0	0
T9	1200	13	0	0
T10	314284	42	0	0
T11	431433	5962	0	0
T12	12769	59	0	0
T13	64392	918	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	213223	0	0
T1	33563	67	0	0
T2	253	0	0	0
T3	78119	138	0	0
T4	471589	830	0	0
T8	497296	18	0	0
T9	1200	14	0	0
T10	314284	11	0	0
T11	431433	14	0	0
T12	12769	9	0	0
T13	64392	127	0	0
T14	0	56	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	213223	0	0
T1	33563	67	0	0
T2	253	0	0	0
T3	78119	138	0	0
T4	471589	830	0	0
T8	497296	18	0	0
T9	1200	14	0	0
T10	314284	11	0	0
T11	431433	14	0	0
T12	12769	9	0	0
T13	64392	127	0	0
T14	0	56	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	633776	0	0
T1	33563	67	0	0
T2	253	0	0	0
T3	78119	140	0	0
T4	471589	918	0	0
T8	497296	292	0	0
T9	1200	16	0	0
T10	314284	14	0	0
T11	431433	14	0	0
T12	12769	9	0	0
T13	64392	173	0	0
T14	0	60	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	213223	0	0
T1	33563	67	0	0
T2	253	0	0	0
T3	78119	138	0	0
T4	471589	830	0	0
T8	497296	18	0	0
T9	1200	14	0	0
T10	314284	11	0	0
T11	431433	14	0	0
T12	12769	9	0	0
T13	64392	127	0	0
T14	0	56	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	209546	0	0
GntImpliesValid_A	429068271	209546	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	209546	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3184706	0	0
ReadyAndValidImplyGrant_A	429068271	209546	0	0
ReqAndReadyImplyGrant_A	429068271	209546	0	0
ReqImpliesValid_A	429068271	586829	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	209546	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209546	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	123	0	0
T4	471589	1746	0	0
T8	497296	13	0	0
T9	1200	9	0	0
T10	314284	11	0	0
T11	431433	17	0	0
T12	12769	15	0	0
T13	64392	111	0	0
T14	0	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209546	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	123	0	0
T4	471589	1746	0	0
T8	497296	13	0	0
T9	1200	9	0	0
T10	314284	11	0	0
T11	431433	17	0	0
T12	12769	15	0	0
T13	64392	111	0	0
T14	0	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209546	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	123	0	0
T4	471589	1746	0	0
T8	497296	13	0	0
T9	1200	9	0	0
T10	314284	11	0	0
T11	431433	17	0	0
T12	12769	15	0	0
T13	64392	111	0	0
T14	0	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3184706	0	0
T1	33563	453	0	0
T2	253	1	0	0
T3	78119	839	0	0
T4	471589	8408	0	0
T8	497296	5821	0	0
T9	1200	10	0	0
T10	314284	57	0	0
T11	431433	5745	0	0
T12	12769	114	0	0
T13	64392	797	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209546	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	123	0	0
T4	471589	1746	0	0
T8	497296	13	0	0
T9	1200	9	0	0
T10	314284	11	0	0
T11	431433	17	0	0
T12	12769	15	0	0
T13	64392	111	0	0
T14	0	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209546	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	123	0	0
T4	471589	1746	0	0
T8	497296	13	0	0
T9	1200	9	0	0
T10	314284	11	0	0
T11	431433	17	0	0
T12	12769	15	0	0
T13	64392	111	0	0
T14	0	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	586829	0	0
T1	33563	67	0	0
T2	253	0	0	0
T3	78119	123	0	0
T4	471589	9439	0	0
T8	497296	808	0	0
T9	1200	9	0	0
T10	314284	11	0	0
T11	431433	201	0	0
T12	12769	16	0	0
T13	64392	171	0	0
T14	0	75	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209546	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	123	0	0
T4	471589	1746	0	0
T8	497296	13	0	0
T9	1200	9	0	0
T10	314284	11	0	0
T11	431433	17	0	0
T12	12769	15	0	0
T13	64392	111	0	0
T14	0	67	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T9
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	220326	0	0
GntImpliesValid_A	429068271	220326	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	220326	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3156307	0	0
ReadyAndValidImplyGrant_A	429068271	220326	0	0
ReqAndReadyImplyGrant_A	429068271	220326	0	0
ReqImpliesValid_A	429068271	555883	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	220326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	220326	0	0
T1	33563	71	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	906	0	0
T8	497296	10	0	0
T9	1200	19	0	0
T10	314284	11	0	0
T11	431433	8	0	0
T12	12769	14	0	0
T13	64392	215	0	0
T14	0	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	220326	0	0
T1	33563	71	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	906	0	0
T8	497296	10	0	0
T9	1200	19	0	0
T10	314284	11	0	0
T11	431433	8	0	0
T12	12769	14	0	0
T13	64392	215	0	0
T14	0	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	220326	0	0
T1	33563	71	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	906	0	0
T8	497296	10	0	0
T9	1200	19	0	0
T10	314284	11	0	0
T11	431433	8	0	0
T12	12769	14	0	0
T13	64392	215	0	0
T14	0	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3156307	0	0
T1	33563	488	0	0
T2	253	1	0	0
T3	78119	782	0	0
T4	471589	6883	0	0
T8	497296	1893	0	0
T9	1200	18	0	0
T10	314284	49	0	0
T11	431433	2177	0	0
T12	12769	116	0	0
T13	64392	1681	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	220326	0	0
T1	33563	71	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	906	0	0
T8	497296	10	0	0
T9	1200	19	0	0
T10	314284	11	0	0
T11	431433	8	0	0
T12	12769	14	0	0
T13	64392	215	0	0
T14	0	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	220326	0	0
T1	33563	71	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	906	0	0
T8	497296	10	0	0
T9	1200	19	0	0
T10	314284	11	0	0
T11	431433	8	0	0
T12	12769	14	0	0
T13	64392	215	0	0
T14	0	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	555883	0	0
T1	33563	71	0	0
T2	253	0	0	0
T3	78119	138	0	0
T4	471589	1113	0	0
T8	497296	10	0	0
T9	1200	21	0	0
T10	314284	18	0	0
T11	431433	8	0	0
T12	12769	14	0	0
T13	64392	288	0	0
T14	0	58	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	220326	0	0
T1	33563	71	0	0
T2	253	0	0	0
T3	78119	118	0	0
T4	471589	906	0	0
T8	497296	10	0	0
T9	1200	19	0	0
T10	314284	11	0	0
T11	431433	8	0	0
T12	12769	14	0	0
T13	64392	215	0	0
T14	0	54	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	210576	0	0
GntImpliesValid_A	429068271	210576	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	210576	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3219024	0	0
ReadyAndValidImplyGrant_A	429068271	210576	0	0
ReqAndReadyImplyGrant_A	429068271	210576	0	0
ReqImpliesValid_A	429068271	595546	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	210576	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	210576	0	0
T1	33563	44	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	837	0	0
T8	497296	18	0	0
T9	1200	10	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	16	0	0
T13	64392	124	0	0
T14	0	69	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	210576	0	0
T1	33563	44	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	837	0	0
T8	497296	18	0	0
T9	1200	10	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	16	0	0
T13	64392	124	0	0
T14	0	69	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	210576	0	0
T1	33563	44	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	837	0	0
T8	497296	18	0	0
T9	1200	10	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	16	0	0
T13	64392	124	0	0
T14	0	69	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3219024	0	0
T1	33563	291	0	0
T2	253	1	0	0
T3	78119	914	0	0
T4	471589	6479	0	0
T8	497296	8028	0	0
T9	1200	10	0	0
T10	314284	39	0	0
T11	431433	4218	0	0
T12	12769	95	0	0
T13	64392	1014	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	210576	0	0
T1	33563	44	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	837	0	0
T8	497296	18	0	0
T9	1200	10	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	16	0	0
T13	64392	124	0	0
T14	0	69	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	210576	0	0
T1	33563	44	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	837	0	0
T8	497296	18	0	0
T9	1200	10	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	16	0	0
T13	64392	124	0	0
T14	0	69	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	595546	0	0
T1	33563	44	0	0
T2	253	0	0	0
T3	78119	124	0	0
T4	471589	979	0	0
T8	497296	120	0	0
T9	1200	11	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	30	0	0
T13	64392	173	0	0
T14	0	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	210576	0	0
T1	33563	44	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	837	0	0
T8	497296	18	0	0
T9	1200	10	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	16	0	0
T13	64392	124	0	0
T14	0	69	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T14
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T13,T14

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T4,T13,T14
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	212319	0	0
GntImpliesValid_A	429068271	212319	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	212319	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3148598	0	0
ReadyAndValidImplyGrant_A	429068271	212319	0	0
ReqAndReadyImplyGrant_A	429068271	212319	0	0
ReqImpliesValid_A	429068271	588061	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	212319	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212319	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	146	0	0
T4	471589	1391	0	0
T8	497296	11	0	0
T9	1200	13	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	14	0	0
T13	64392	118	0	0
T14	0	58	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212319	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	146	0	0
T4	471589	1391	0	0
T8	497296	11	0	0
T9	1200	13	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	14	0	0
T13	64392	118	0	0
T14	0	58	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212319	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	146	0	0
T4	471589	1391	0	0
T8	497296	11	0	0
T9	1200	13	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	14	0	0
T13	64392	118	0	0
T14	0	58	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3148598	0	0
T1	33563	516	0	0
T2	253	1	0	0
T3	78119	1154	0	0
T4	471589	7735	0	0
T8	497296	3119	0	0
T9	1200	14	0	0
T10	314284	40	0	0
T11	431433	4771	0	0
T12	12769	74	0	0
T13	64392	902	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212319	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	146	0	0
T4	471589	1391	0	0
T8	497296	11	0	0
T9	1200	13	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	14	0	0
T13	64392	118	0	0
T14	0	58	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212319	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	146	0	0
T4	471589	1391	0	0
T8	497296	11	0	0
T9	1200	13	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	14	0	0
T13	64392	118	0	0
T14	0	58	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	588061	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	146	0	0
T4	471589	5888	0	0
T8	497296	11	0	0
T9	1200	13	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	14	0	0
T13	64392	167	0	0
T14	0	84	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212319	0	0
T1	33563	61	0	0
T2	253	0	0	0
T3	78119	146	0	0
T4	471589	1391	0	0
T8	497296	11	0	0
T9	1200	13	0	0
T10	314284	11	0	0
T11	431433	13	0	0
T12	12769	14	0	0
T13	64392	118	0	0
T14	0	58	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T9
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	212411	0	0
GntImpliesValid_A	429068271	212411	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	212411	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3148039	0	0
ReadyAndValidImplyGrant_A	429068271	212411	0	0
ReqAndReadyImplyGrant_A	429068271	212411	0	0
ReqImpliesValid_A	429068271	562054	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	212411	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212411	0	0
T1	33563	54	0	0
T2	253	0	0	0
T3	78119	110	0	0
T4	471589	2387	0	0
T8	497296	13	0	0
T9	1200	8	0	0
T10	314284	8	0	0
T11	431433	11	0	0
T12	12769	13	0	0
T13	64392	112	0	0
T14	0	72	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212411	0	0
T1	33563	54	0	0
T2	253	0	0	0
T3	78119	110	0	0
T4	471589	2387	0	0
T8	497296	13	0	0
T9	1200	8	0	0
T10	314284	8	0	0
T11	431433	11	0	0
T12	12769	13	0	0
T13	64392	112	0	0
T14	0	72	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212411	0	0
T1	33563	54	0	0
T2	253	0	0	0
T3	78119	110	0	0
T4	471589	2387	0	0
T8	497296	13	0	0
T9	1200	8	0	0
T10	314284	8	0	0
T11	431433	11	0	0
T12	12769	13	0	0
T13	64392	112	0	0
T14	0	72	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3148039	0	0
T1	33563	419	0	0
T2	253	1	0	0
T3	78119	936	0	0
T4	471589	14663	0	0
T8	497296	4543	0	0
T9	1200	8	0	0
T10	314284	18	0	0
T11	431433	4550	0	0
T12	12769	109	0	0
T13	64392	762	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212411	0	0
T1	33563	54	0	0
T2	253	0	0	0
T3	78119	110	0	0
T4	471589	2387	0	0
T8	497296	13	0	0
T9	1200	8	0	0
T10	314284	8	0	0
T11	431433	11	0	0
T12	12769	13	0	0
T13	64392	112	0	0
T14	0	72	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212411	0	0
T1	33563	54	0	0
T2	253	0	0	0
T3	78119	110	0	0
T4	471589	2387	0	0
T8	497296	13	0	0
T9	1200	8	0	0
T10	314284	8	0	0
T11	431433	11	0	0
T12	12769	13	0	0
T13	64392	112	0	0
T14	0	72	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	562054	0	0
T1	33563	54	0	0
T2	253	0	0	0
T3	78119	111	0	0
T4	471589	8719	0	0
T8	497296	13	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	11	0	0
T12	12769	22	0	0
T13	64392	137	0	0
T14	0	75	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	212411	0	0
T1	33563	54	0	0
T2	253	0	0	0
T3	78119	110	0	0
T4	471589	2387	0	0
T8	497296	13	0	0
T9	1200	8	0	0
T10	314284	8	0	0
T11	431433	11	0	0
T12	12769	13	0	0
T13	64392	112	0	0
T14	0	72	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T13
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T4,T8,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	208588	0	0
GntImpliesValid_A	429068271	208588	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	208588	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3141383	0	0
ReadyAndValidImplyGrant_A	429068271	208588	0	0
ReqAndReadyImplyGrant_A	429068271	208588	0	0
ReqImpliesValid_A	429068271	546085	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	208588	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208588	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	818	0	0
T8	497296	20	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	12	0	0
T12	12769	14	0	0
T13	64392	123	0	0
T14	0	68	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208588	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	818	0	0
T8	497296	20	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	12	0	0
T12	12769	14	0	0
T13	64392	123	0	0
T14	0	68	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208588	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	818	0	0
T8	497296	20	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	12	0	0
T12	12769	14	0	0
T13	64392	123	0	0
T14	0	68	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3141383	0	0
T1	33563	398	0	0
T2	253	1	0	0
T3	78119	850	0	0
T4	471589	6097	0	0
T8	497296	4759	0	0
T9	1200	10	0	0
T10	314284	33	0	0
T11	431433	5314	0	0
T12	12769	105	0	0
T13	64392	898	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208588	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	818	0	0
T8	497296	20	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	12	0	0
T12	12769	14	0	0
T13	64392	123	0	0
T14	0	68	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208588	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	818	0	0
T8	497296	20	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	12	0	0
T12	12769	14	0	0
T13	64392	123	0	0
T14	0	68	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	546085	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	1004	0	0
T8	497296	218	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	12	0	0
T12	12769	14	0	0
T13	64392	161	0	0
T14	0	88	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	208588	0	0
T1	33563	66	0	0
T2	253	0	0	0
T3	78119	116	0	0
T4	471589	818	0	0
T8	497296	20	0	0
T9	1200	9	0	0
T10	314284	8	0	0
T11	431433	12	0	0
T12	12769	14	0	0
T13	64392	123	0	0
T14	0	68	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	209237	0	0
GntImpliesValid_A	429068271	209237	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	209237	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	3127289	0	0
ReadyAndValidImplyGrant_A	429068271	209237	0	0
ReqAndReadyImplyGrant_A	429068271	209237	0	0
ReqImpliesValid_A	429068271	599159	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	0	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	209237	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209237	0	0
T1	33563	55	0	0
T2	253	0	0	0
T3	78119	115	0	0
T4	471589	821	0	0
T8	497296	14	0	0
T9	1200	10	0	0
T10	314284	13	0	0
T11	431433	10	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209237	0	0
T1	33563	55	0	0
T2	253	0	0	0
T3	78119	115	0	0
T4	471589	821	0	0
T8	497296	14	0	0
T9	1200	10	0	0
T10	314284	13	0	0
T11	431433	10	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209237	0	0
T1	33563	55	0	0
T2	253	0	0	0
T3	78119	115	0	0
T4	471589	821	0	0
T8	497296	14	0	0
T9	1200	10	0	0
T10	314284	13	0	0
T11	431433	10	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	3127289	0	0
T1	33563	455	0	0
T2	253	1	0	0
T3	78119	913	0	0
T4	471589	6255	0	0
T8	497296	6020	0	0
T9	1200	9	0	0
T10	314284	53	0	0
T11	431433	3620	0	0
T12	12769	151	0	0
T13	64392	831	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209237	0	0
T1	33563	55	0	0
T2	253	0	0	0
T3	78119	115	0	0
T4	471589	821	0	0
T8	497296	14	0	0
T9	1200	10	0	0
T10	314284	13	0	0
T11	431433	10	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209237	0	0
T1	33563	55	0	0
T2	253	0	0	0
T3	78119	115	0	0
T4	471589	821	0	0
T8	497296	14	0	0
T9	1200	10	0	0
T10	314284	13	0	0
T11	431433	10	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	599159	0	0
T1	33563	68	0	0
T2	253	0	0	0
T3	78119	142	0	0
T4	471589	1017	0	0
T8	497296	14	0	0
T9	1200	12	0	0
T10	314284	13	0	0
T11	431433	242	0	0
T12	12769	23	0	0
T13	64392	151	0	0
T14	0	72	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	209237	0	0
T1	33563	55	0	0
T2	253	0	0	0
T3	78119	115	0	0
T4	471589	821	0	0
T8	497296	14	0	0
T9	1200	10	0	0
T10	314284	13	0	0
T11	431433	10	0	0
T12	12769	16	0	0
T13	64392	114	0	0
T14	0	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	857446	0	0
GntImpliesValid_A	429068271	857446	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	857446	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	11927453	0	0
ReadyAndValidImplyGrant_A	429068271	857446	0	0
ReqAndReadyImplyGrant_A	429068271	857446	0	0
ReqImpliesValid_A	429068271	2288726	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	20438	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	857446	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	857446	0	0
T1	33563	237	0	0
T2	253	0	0	0
T3	78119	503	0	0
T4	471589	5218	0	0
T8	497296	52	0	0
T9	1200	54	0	0
T10	314284	44	0	0
T11	431433	64	0	0
T12	12769	48	0	0
T13	64392	476	0	0
T14	0	258	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	857446	0	0
T1	33563	237	0	0
T2	253	0	0	0
T3	78119	503	0	0
T4	471589	5218	0	0
T8	497296	52	0	0
T9	1200	54	0	0
T10	314284	44	0	0
T11	431433	64	0	0
T12	12769	48	0	0
T13	64392	476	0	0
T14	0	258	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	857446	0	0
T1	33563	237	0	0
T2	253	0	0	0
T3	78119	503	0	0
T4	471589	5218	0	0
T8	497296	52	0	0
T9	1200	54	0	0
T10	314284	44	0	0
T11	431433	64	0	0
T12	12769	48	0	0
T13	64392	476	0	0
T14	0	258	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	11927453	0	0
T1	33563	1690	0	0
T2	253	1	0	0
T3	78119	3423	0	0
T4	471589	31951	0	0
T8	497296	18795	0	0
T9	1200	1	0	0
T10	314284	149	0	0
T11	431433	22475	0	0
T12	12769	335	0	0
T13	64392	2979	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	857446	0	0
T1	33563	237	0	0
T2	253	0	0	0
T3	78119	503	0	0
T4	471589	5218	0	0
T8	497296	52	0	0
T9	1200	54	0	0
T10	314284	44	0	0
T11	431433	64	0	0
T12	12769	48	0	0
T13	64392	476	0	0
T14	0	258	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	857446	0	0
T1	33563	237	0	0
T2	253	0	0	0
T3	78119	503	0	0
T4	471589	5218	0	0
T8	497296	52	0	0
T9	1200	54	0	0
T10	314284	44	0	0
T11	431433	64	0	0
T12	12769	48	0	0
T13	64392	476	0	0
T14	0	258	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	2288726	0	0
T1	33563	279	0	0
T2	253	0	0	0
T3	78119	559	0	0
T4	471589	11449	0	0
T8	497296	1835	0	0
T9	1200	54	0	0
T10	314284	51	0	0
T11	431433	3184	0	0
T12	12769	66	0	0
T13	64392	705	0	0
T14	0	318	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	20438	0	900
T4	471589	6	0	1
T8	497296	0	0	1
T9	1200	6	0	1
T10	314284	0	0	1
T11	431433	0	0	1
T12	12769	0	0	1
T13	64392	1	0	1
T14	505191	0	0	1
T15	10562	7	0	1
T16	0	4	0	0
T17	0	21	0	0
T18	0	2	0	0
T20	0	15	0	0
T21	0	11	0	0
T22	0	2	0	0
T23	110531	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	857446	0	0
T1	33563	237	0	0
T2	253	0	0	0
T3	78119	503	0	0
T4	471589	5218	0	0
T8	497296	52	0	0
T9	1200	54	0	0
T10	314284	44	0	0
T11	431433	64	0	0
T12	12769	48	0	0
T13	64392	476	0	0
T14	0	258	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429068271	428947732	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	429068271	850911	0	0
GntImpliesValid_A	429068271	850911	0	0
GrantKnown_A	429068271	428947732	0	0
IdxKnown_A	429068271	428947732	0	0
IndexIsCorrect_A	429068271	850911	0	0
LockArbDecision_A	429068271	0	0	0
NoReadyValidNoGrant_A	429068271	361406817	0	0
ReadyAndValidImplyGrant_A	429068271	850911	0	0
ReqAndReadyImplyGrant_A	429068271	850911	0	0
ReqImpliesValid_A	429068271	13810613	0	0
ReqStaysHighUntilGranted0_M	429068271	0	0	0
RoundRobin_A	429068271	25829	0	900
ValidKnown_A	429068271	428947732	0	0
gen_data_port_assertion.DataFlow_A	429068271	850911	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	850911	0	0
T1	33563	197	0	0
T2	253	0	0	0
T3	78119	521	0	0
T4	471589	4560	0	0
T8	497296	62	0	0
T9	1200	55	0	0
T10	314284	44	0	0
T11	431433	58	0	0
T12	12769	46	0	0
T13	64392	430	0	0
T14	0	257	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	850911	0	0
T1	33563	197	0	0
T2	253	0	0	0
T3	78119	521	0	0
T4	471589	4560	0	0
T8	497296	62	0	0
T9	1200	55	0	0
T10	314284	44	0	0
T11	431433	58	0	0
T12	12769	46	0	0
T13	64392	430	0	0
T14	0	257	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	850911	0	0
T1	33563	197	0	0
T2	253	0	0	0
T3	78119	521	0	0
T4	471589	4560	0	0
T8	497296	62	0	0
T9	1200	55	0	0
T10	314284	44	0	0
T11	431433	58	0	0
T12	12769	46	0	0
T13	64392	430	0	0
T14	0	257	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	361406817	0	0
T1	33563	29187	0	0
T2	253	153	0	0
T3	78119	67387	0	0
T4	471589	395206	0	0
T8	497296	471962	0	0
T9	1200	1	0	0
T10	314284	261507	0	0
T11	431433	402938	0	0
T12	12769	11217	0	0
T13	64392	55446	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	850911	0	0
T1	33563	197	0	0
T2	253	0	0	0
T3	78119	521	0	0
T4	471589	4560	0	0
T8	497296	62	0	0
T9	1200	55	0	0
T10	314284	44	0	0
T11	431433	58	0	0
T12	12769	46	0	0
T13	64392	430	0	0
T14	0	257	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	850911	0	0
T1	33563	197	0	0
T2	253	0	0	0
T3	78119	521	0	0
T4	471589	4560	0	0
T8	497296	62	0	0
T9	1200	55	0	0
T10	314284	44	0	0
T11	431433	58	0	0
T12	12769	46	0	0
T13	64392	430	0	0
T14	0	257	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	13810613	0	0
T1	33563	1511	0	0
T2	253	0	0	0
T3	78119	4122	0	0
T4	471589	38137	0	0
T8	497296	24376	0	0
T9	1200	55	0	0
T10	314284	237	0	0
T11	431433	17565	0	0
T12	12769	376	0	0
T13	64392	3492	0	0
T14	0	1154	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	25829	0	900
T3	78119	1	0	1
T4	471589	4	0	1
T8	497296	0	0	1
T9	1200	2	0	1
T10	314284	0	0	1
T11	431433	0	0	1
T12	12769	0	0	1
T13	64392	0	0	1
T14	505191	0	0	1
T15	0	8	0	0
T16	0	8	0	0
T17	0	16	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	23	0	0
T21	0	12	0	0
T23	110531	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	428947732	0	0
T1	33563	33552	0	0
T2	253	170	0	0
T3	78119	78088	0	0
T4	471589	471544	0	0
T8	497296	497250	0	0
T9	1200	1160	0	0
T10	314284	314247	0	0
T11	431433	431406	0	0
T12	12769	12692	0	0
T13	64392	64368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429068271	850911	0	0
T1	33563	197	0	0
T2	253	0	0	0
T3	78119	521	0	0
T4	471589	4560	0	0
T8	497296	62	0	0
T9	1200	55	0	0
T10	314284	44	0	0
T11	431433	58	0	0
T12	12769	46	0	0
T13	64392	430	0	0
T14	0	257	0	0