Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1667550	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264186

1

T1

206

T2

23

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	655983	1			T1	524		T2	49		T3	47
values[0x0]	620580	1			T1	531		T2	58		T3	5
values[0x1]	655173	1			T1	545		T2	52		T3	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1288726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

643010

1

T1

523

T2

38

T3

43

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30552	1			T1	50		T2	4		T7	36
valid_sources[0x01]	29772	1			T1	17		T3	1		T7	8
valid_sources[0x02]	30708	1			T1	8		T3	1		T7	59
valid_sources[0x03]	30469	1			T1	7		T2	2		T3	1
valid_sources[0x04]	29997	1			T1	40		T2	1		T3	2
valid_sources[0x05]	29601	1			T1	19		T2	9		T3	1
valid_sources[0x06]	31106	1			T2	1		T3	1		T7	3
valid_sources[0x07]	30188	1			T1	31		T2	3		T3	3
valid_sources[0x08]	30729	1			T1	13		T2	8		T7	29
valid_sources[0x09]	30726	1			T1	26		T2	2		T3	4
valid_sources[0x0a]	30322	1			T1	67		T2	4		T7	28
valid_sources[0x0b]	30035	1			T1	30		T2	4		T3	3
valid_sources[0x0c]	29965	1			T1	5		T2	1		T3	2
valid_sources[0x0d]	29564	1			T1	5		T2	2		T3	2
valid_sources[0x0e]	30191	1			T1	28		T3	4		T8	17
valid_sources[0x0f]	30341	1			T1	43		T3	1		T7	32
valid_sources[0x10]	30130	1			T1	18		T7	69		T8	21
valid_sources[0x11]	30099	1			T1	4		T2	5		T3	2
valid_sources[0x12]	30649	1			T2	3		T3	2		T7	28
valid_sources[0x13]	30125	1			T1	61		T2	2		T3	1
valid_sources[0x14]	30289	1			T1	8		T2	5		T7	35
valid_sources[0x15]	30434	1			T1	62		T2	1		T3	3
valid_sources[0x16]	29711	1			T1	73		T2	4		T3	2
valid_sources[0x17]	30210	1			T1	40		T2	4		T3	2
valid_sources[0x18]	29479	1			T1	45		T2	2		T3	2
valid_sources[0x19]	30534	1			T1	175		T7	22		T8	14
valid_sources[0x1a]	30378	1			T1	42		T2	1		T3	1
valid_sources[0x1b]	30986	1			T1	5		T2	4		T7	49
valid_sources[0x1c]	30817	1			T1	5		T2	1		T3	3
valid_sources[0x1d]	29562	1			T1	8		T2	2		T3	2
valid_sources[0x1e]	30344	1			T1	18		T2	1		T3	3
valid_sources[0x1f]	30455	1			T1	36		T2	1		T3	2
valid_sources[0x20]	30914	1			T1	29		T2	2		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27579

1

T1

18

T2

1

T3

1

values[0x0]

all_enables

biggest_size

209100

1

T1

170

T2

20

T3

3

values[0x1]

all_enables

biggest_size

27507

1

T1

18

T2

2

T3

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1692219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

275339

1

T1

243

T2

15

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	673818	1			T1	563		T2	32		T3	56
values[0x0]	621109	1			T1	542		T2	39		T3	12
values[0x1]	672631	1			T1	639		T2	34		T3	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1299788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

667770

1

T1

644

T2

32

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30370	1			T1	23		T3	3		T7	26
valid_sources[0x01]	30236	1			T1	38		T3	2		T7	45
valid_sources[0x02]	30433	1			T1	25		T3	3		T7	42
valid_sources[0x03]	30957	1			T1	41		T3	5		T7	35
valid_sources[0x04]	29724	1			T1	26		T2	1		T3	3
valid_sources[0x05]	29913	1			T1	22		T3	1		T7	49
valid_sources[0x06]	31052	1			T1	27		T7	36		T8	15
valid_sources[0x07]	31336	1			T1	25		T2	7		T3	1
valid_sources[0x08]	31347	1			T1	20		T3	1		T7	41
valid_sources[0x09]	30742	1			T1	20		T2	1		T3	2
valid_sources[0x0a]	30622	1			T1	31		T2	7		T3	1
valid_sources[0x0b]	29815	1			T1	33		T3	3		T7	36
valid_sources[0x0c]	30252	1			T1	32		T3	2		T7	40
valid_sources[0x0d]	31197	1			T1	31		T2	4		T3	4
valid_sources[0x0e]	31795	1			T1	22		T3	3		T7	33
valid_sources[0x0f]	29924	1			T1	28		T2	12		T7	22
valid_sources[0x10]	30344	1			T1	20		T3	3		T7	40
valid_sources[0x11]	30508	1			T1	34		T2	9		T3	4
valid_sources[0x12]	31167	1			T1	25		T2	9		T3	2
valid_sources[0x13]	30833	1			T1	24		T3	1		T7	34
valid_sources[0x14]	30509	1			T1	30		T3	1		T7	34
valid_sources[0x15]	30324	1			T1	30		T3	3		T7	41
valid_sources[0x16]	30647	1			T1	26		T3	1		T7	51
valid_sources[0x17]	30319	1			T1	24		T3	1		T7	41
valid_sources[0x18]	31559	1			T1	22		T3	1		T7	35
valid_sources[0x19]	31334	1			T1	27		T3	5		T7	31
valid_sources[0x1a]	31222	1			T1	25		T7	37		T8	17
valid_sources[0x1b]	31489	1			T1	18		T2	5		T3	1
valid_sources[0x1c]	31030	1			T1	21		T3	4		T7	50
valid_sources[0x1d]	31291	1			T1	31		T2	2		T3	2
valid_sources[0x1e]	30927	1			T1	42		T3	2		T7	42
valid_sources[0x1f]	31225	1			T1	28		T3	1		T7	44
valid_sources[0x20]	30841	1			T1	28		T2	1		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28783

1

T1

22

T2

2

T3

3

values[0x0]

all_enables

biggest_size

217659

1

T1

197

T2

12

T3

4

values[0x1]

all_enables

biggest_size

28897

1

T1

24

T2

1

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1679802	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

266377

1

T1

264

T2

29

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	660553	1			T1	611		T2	62		T3	54
values[0x0]	626219	1			T1	576		T2	62		T3	11
values[0x1]	659407	1			T1	559		T2	71		T3	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1299298	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

646881

1

T1

630

T2

67

T3

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30759	1			T1	16		T2	4		T3	1
valid_sources[0x01]	30133	1			T1	63		T2	9		T3	1
valid_sources[0x02]	29761	1			T1	60		T2	3		T3	4
valid_sources[0x03]	29854	1			T1	32		T7	77		T8	16
valid_sources[0x04]	30222	1			T1	38		T2	14		T7	38
valid_sources[0x05]	30539	1			T1	32		T2	3		T3	1
valid_sources[0x06]	30828	1			T3	3		T7	7		T8	15
valid_sources[0x07]	30409	1			T1	11		T2	2		T3	1
valid_sources[0x08]	30913	1			T1	17		T7	60		T8	19
valid_sources[0x09]	30159	1			T1	9		T2	6		T3	1
valid_sources[0x0a]	31065	1			T1	11		T2	1		T3	1
valid_sources[0x0b]	30085	1			T1	44		T2	6		T3	4
valid_sources[0x0c]	30463	1			T1	38		T2	12		T3	5
valid_sources[0x0d]	29939	1			T1	10		T2	4		T7	11
valid_sources[0x0e]	30454	1			T1	48		T3	4		T7	52
valid_sources[0x0f]	30007	1			T1	27		T3	1		T7	17
valid_sources[0x10]	30249	1			T1	11		T2	3		T3	1
valid_sources[0x11]	29834	1			T1	38		T2	2		T3	1
valid_sources[0x12]	30320	1			T1	23		T3	6		T7	4
valid_sources[0x13]	30725	1			T1	8		T7	27		T8	11
valid_sources[0x14]	30897	1			T1	31		T2	7		T3	2
valid_sources[0x15]	29708	1			T1	31		T2	2		T3	6
valid_sources[0x16]	30477	1			T1	22		T2	1		T7	39
valid_sources[0x17]	30353	1			T1	8		T2	2		T3	1
valid_sources[0x18]	30118	1			T1	29		T2	6		T3	2
valid_sources[0x19]	31217	1			T1	6		T2	7		T7	52
valid_sources[0x1a]	29840	1			T1	23		T2	6		T3	3
valid_sources[0x1b]	30778	1			T1	29		T3	6		T7	14
valid_sources[0x1c]	30744	1			T1	40		T2	2		T3	1
valid_sources[0x1d]	31061	1			T1	40		T2	5		T3	2
valid_sources[0x1e]	30437	1			T1	48		T7	58		T8	19
valid_sources[0x1f]	30879	1			T1	33		T2	3		T7	19
valid_sources[0x20]	30085	1			T1	24		T2	10		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27973

1

T1

29

T2

2

T3

3

values[0x0]

all_enables

biggest_size

210664

1

T1

214

T2

20

T3

2

values[0x1]

all_enables

biggest_size

27740

1

T1

21

T2

7

T3

2