Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8279801	0	0
GntImpliesValid_A	2147483647	8279801	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8279801	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	453914405	0	0
ReadyAndValidImplyGrant_A	2147483647	8279801	0	0
ReqAndReadyImplyGrant_A	2147483647	8279801	0	0
ReqImpliesValid_A	2147483647	35042073	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50874	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8279801	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	244416	243096	0	0
T2	48552	47568	0	0
T3	1534800	1534080	0	0
T7	8124144	8123952	0	0
T8	6656352	6656184	0	0
T9	610800	609192	0	0
T10	1673688	1672896	0	0
T11	9640728	9640656	0	0
T12	183264	182256	0	0
T13	15031584	15029976	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8279801	0	0
T1	244416	5089	0	0
T2	48552	458	0	0
T3	1534800	7394	0	0
T7	8124144	7356	0	0
T8	6656352	2959	0	0
T9	610800	1648	0	0
T10	1673688	6807	0	0
T11	9640728	9971	0	0
T12	183264	504	0	0
T13	15031584	61214	0	0
T14	0	3634	0	0
T15	0	137	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8279801	0	0
T1	244416	5089	0	0
T2	48552	458	0	0
T3	1534800	7394	0	0
T7	8124144	7356	0	0
T8	6656352	2959	0	0
T9	610800	1648	0	0
T10	1673688	6807	0	0
T11	9640728	9971	0	0
T12	183264	504	0	0
T13	15031584	61214	0	0
T14	0	3634	0	0
T15	0	137	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	244416	243096	0	0
T2	48552	47568	0	0
T3	1534800	1534080	0	0
T7	8124144	8123952	0	0
T8	6656352	6656184	0	0
T9	610800	609192	0	0
T10	1673688	1672896	0	0
T11	9640728	9640656	0	0
T12	183264	182256	0	0
T13	15031584	15029976	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	244416	243096	0	0
T2	48552	47568	0	0
T3	1534800	1534080	0	0
T7	8124144	8123952	0	0
T8	6656352	6656184	0	0
T9	610800	609192	0	0
T10	1673688	1672896	0	0
T11	9640728	9640656	0	0
T12	183264	182256	0	0
T13	15031584	15029976	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8279801	0	0
T1	244416	5089	0	0
T2	48552	458	0	0
T3	1534800	7394	0	0
T7	8124144	7356	0	0
T8	6656352	2959	0	0
T9	610800	1648	0	0
T10	1673688	6807	0	0
T11	9640728	9971	0	0
T12	183264	504	0	0
T13	15031584	61214	0	0
T14	0	3634	0	0
T15	0	137	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	453914405	0	0
T1	244416	7621	0	0
T2	48552	557	0	0
T3	1534800	100362	0	0
T7	8124144	2636935	0	0
T8	6656352	255780	0	0
T9	610800	34540	0	0
T10	1673688	104967	0	0
T11	9640728	365829	0	0
T12	183264	10307	0	0
T13	15031584	898722	0	0
T14	0	411266	0	0
T15	0	8371	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8279801	0	0
T1	244416	5089	0	0
T2	48552	458	0	0
T3	1534800	7394	0	0
T7	8124144	7356	0	0
T8	6656352	2959	0	0
T9	610800	1648	0	0
T10	1673688	6807	0	0
T11	9640728	9971	0	0
T12	183264	504	0	0
T13	15031584	61214	0	0
T14	0	3634	0	0
T15	0	137	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8279801	0	0
T1	244416	5089	0	0
T2	48552	458	0	0
T3	1534800	7394	0	0
T7	8124144	7356	0	0
T8	6656352	2959	0	0
T9	610800	1648	0	0
T10	1673688	6807	0	0
T11	9640728	9971	0	0
T12	183264	504	0	0
T13	15031584	61214	0	0
T14	0	3634	0	0
T15	0	137	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35042073	0	0
T1	244416	6124	0	0
T2	48552	483	0	0
T3	1534800	17456	0	0
T7	8124144	464925	0	0
T8	6656352	12323	0	0
T9	610800	3383	0	0
T10	1673688	15765	0	0
T11	9640728	23484	0	0
T12	183264	1034	0	0
T13	15031584	147490	0	0
T14	0	102569	0	0
T15	0	1923	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50874	0	21600
T1	20368	16	0	2
T2	4046	0	0	2
T3	127900	2	0	2
T4	0	18	0	0
T7	677012	0	0	2
T8	554696	16	0	2
T9	50900	0	0	2
T10	139474	2	0	2
T11	803394	10	0	2
T12	15272	0	0	2
T13	1252632	19	0	2
T16	0	81	0	0
T17	0	27	0	0
T18	0	24	0	0
T19	0	8	0	0
T20	0	18	0	0
T21	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	244416	243096	0	0
T2	48552	47568	0	0
T3	1534800	1534080	0	0
T7	8124144	8123952	0	0
T8	6656352	6656184	0	0
T9	610800	609192	0	0
T10	1673688	1672896	0	0
T11	9640728	9640656	0	0
T12	183264	182256	0	0
T13	15031584	15029976	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8279801	0	0
T1	244416	5089	0	0
T2	48552	458	0	0
T3	1534800	7394	0	0
T7	8124144	7356	0	0
T8	6656352	2959	0	0
T9	610800	1648	0	0
T10	1673688	6807	0	0
T11	9640728	9971	0	0
T12	183264	504	0	0
T13	15031584	61214	0	0
T14	0	3634	0	0
T15	0	137	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	930878	0	0
GntImpliesValid_A	418699397	930878	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	930878	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	12186628	0	0
ReadyAndValidImplyGrant_A	418699397	930878	0	0
ReqAndReadyImplyGrant_A	418699397	930878	0	0
ReqImpliesValid_A	418699397	2598527	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	930878	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	930878	0	0
T1	10184	552	0	0
T2	2023	33	0	0
T3	63950	907	0	0
T7	338506	842	0	0
T8	277348	170	0	0
T9	25450	184	0	0
T10	69737	763	0	0
T11	401697	2090	0	0
T12	7636	49	0	0
T13	626316	8267	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	930878	0	0
T1	10184	552	0	0
T2	2023	33	0	0
T3	63950	907	0	0
T7	338506	842	0	0
T8	277348	170	0	0
T9	25450	184	0	0
T10	69737	763	0	0
T11	401697	2090	0	0
T12	7636	49	0	0
T13	626316	8267	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	930878	0	0
T1	10184	552	0	0
T2	2023	33	0	0
T3	63950	907	0	0
T7	338506	842	0	0
T8	277348	170	0	0
T9	25450	184	0	0
T10	69737	763	0	0
T11	401697	2090	0	0
T12	7636	49	0	0
T13	626316	8267	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	12186628	0	0
T1	10184	404	0	0
T2	2023	29	0	0
T3	63950	6659	0	0
T7	338506	271628	0	0
T8	277348	747	0	0
T9	25450	1505	0	0
T10	69737	5271	0	0
T11	401697	7401	0	0
T12	7636	336	0	0
T13	626316	52332	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	930878	0	0
T1	10184	552	0	0
T2	2023	33	0	0
T3	63950	907	0	0
T7	338506	842	0	0
T8	277348	170	0	0
T9	25450	184	0	0
T10	69737	763	0	0
T11	401697	2090	0	0
T12	7636	49	0	0
T13	626316	8267	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	930878	0	0
T1	10184	552	0	0
T2	2023	33	0	0
T3	63950	907	0	0
T7	338506	842	0	0
T8	277348	170	0	0
T9	25450	184	0	0
T10	69737	763	0	0
T11	401697	2090	0	0
T12	7636	49	0	0
T13	626316	8267	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2598527	0	0
T1	10184	701	0	0
T2	2023	38	0	0
T3	63950	1846	0	0
T7	338506	29255	0	0
T8	277348	234	0	0
T9	25450	275	0	0
T10	69737	1402	0	0
T11	401697	4341	0	0
T12	7636	59	0	0
T13	626316	15780	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	930878	0	0
T1	10184	552	0	0
T2	2023	33	0	0
T3	63950	907	0	0
T7	338506	842	0	0
T8	277348	170	0	0
T9	25450	184	0	0
T10	69737	763	0	0
T11	401697	2090	0	0
T12	7636	49	0	0
T13	626316	8267	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	914786	0	0
GntImpliesValid_A	418699397	914786	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	914786	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	12007465	0	0
ReadyAndValidImplyGrant_A	418699397	914786	0	0
ReqAndReadyImplyGrant_A	418699397	914786	0	0
ReqImpliesValid_A	418699397	2430699	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	914786	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	914786	0	0
T1	10184	613	0	0
T2	2023	31	0	0
T3	63950	876	0	0
T7	338506	824	0	0
T8	277348	156	0	0
T9	25450	176	0	0
T10	69737	685	0	0
T11	401697	618	0	0
T12	7636	59	0	0
T13	626316	6198	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	914786	0	0
T1	10184	613	0	0
T2	2023	31	0	0
T3	63950	876	0	0
T7	338506	824	0	0
T8	277348	156	0	0
T9	25450	176	0	0
T10	69737	685	0	0
T11	401697	618	0	0
T12	7636	59	0	0
T13	626316	6198	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	914786	0	0
T1	10184	613	0	0
T2	2023	31	0	0
T3	63950	876	0	0
T7	338506	824	0	0
T8	277348	156	0	0
T9	25450	176	0	0
T10	69737	685	0	0
T11	401697	618	0	0
T12	7636	59	0	0
T13	626316	6198	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	12007465	0	0
T1	10184	450	0	0
T2	2023	26	0	0
T3	63950	5869	0	0
T7	338506	271442	0	0
T8	277348	665	0	0
T9	25450	1266	0	0
T10	69737	5003	0	0
T11	401697	2531	0	0
T12	7636	425	0	0
T13	626316	45883	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	914786	0	0
T1	10184	613	0	0
T2	2023	31	0	0
T3	63950	876	0	0
T7	338506	824	0	0
T8	277348	156	0	0
T9	25450	176	0	0
T10	69737	685	0	0
T11	401697	618	0	0
T12	7636	59	0	0
T13	626316	6198	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	914786	0	0
T1	10184	613	0	0
T2	2023	31	0	0
T3	63950	876	0	0
T7	338506	824	0	0
T8	277348	156	0	0
T9	25450	176	0	0
T10	69737	685	0	0
T11	401697	618	0	0
T12	7636	59	0	0
T13	626316	6198	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2430699	0	0
T1	10184	777	0	0
T2	2023	37	0	0
T3	63950	1567	0	0
T7	338506	28374	0	0
T8	277348	211	0	0
T9	25450	227	0	0
T10	69737	1209	0	0
T11	401697	840	0	0
T12	7636	91	0	0
T13	626316	10222	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	914786	0	0
T1	10184	613	0	0
T2	2023	31	0	0
T3	63950	876	0	0
T7	338506	824	0	0
T8	277348	156	0	0
T9	25450	176	0	0
T10	69737	685	0	0
T11	401697	618	0	0
T12	7636	59	0	0
T13	626316	6198	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	224007	0	0
GntImpliesValid_A	418699397	224007	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	224007	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	3005320	0	0
ReadyAndValidImplyGrant_A	418699397	224007	0	0
ReqAndReadyImplyGrant_A	418699397	224007	0	0
ReqImpliesValid_A	418699397	589460	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	224007	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224007	0	0
T1	10184	165	0	0
T2	2023	18	0	0
T3	63950	170	0	0
T7	338506	200	0	0
T8	277348	0	0	0
T9	25450	38	0	0
T10	69737	212	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2237	0	0
T14	0	206	0	0
T15	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224007	0	0
T1	10184	165	0	0
T2	2023	18	0	0
T3	63950	170	0	0
T7	338506	200	0	0
T8	277348	0	0	0
T9	25450	38	0	0
T10	69737	212	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2237	0	0
T14	0	206	0	0
T15	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224007	0	0
T1	10184	165	0	0
T2	2023	18	0	0
T3	63950	170	0	0
T7	338506	200	0	0
T8	277348	0	0	0
T9	25450	38	0	0
T10	69737	212	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2237	0	0
T14	0	206	0	0
T15	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	3005320	0	0
T1	10184	156	0	0
T2	2023	18	0	0
T3	63950	1305	0	0
T7	338506	65361	0	0
T8	277348	1	0	0
T9	25450	293	0	0
T10	69737	1650	0	0
T11	401697	1	0	0
T12	7636	115	0	0
T13	626316	16210	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224007	0	0
T1	10184	165	0	0
T2	2023	18	0	0
T3	63950	170	0	0
T7	338506	200	0	0
T8	277348	0	0	0
T9	25450	38	0	0
T10	69737	212	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2237	0	0
T14	0	206	0	0
T15	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224007	0	0
T1	10184	165	0	0
T2	2023	18	0	0
T3	63950	170	0	0
T7	338506	200	0	0
T8	277348	0	0	0
T9	25450	38	0	0
T10	69737	212	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2237	0	0
T14	0	206	0	0
T15	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	589460	0	0
T1	10184	175	0	0
T2	2023	19	0	0
T3	63950	237	0	0
T7	338506	3152	0	0
T8	277348	0	0	0
T9	25450	56	0	0
T10	69737	292	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	4414	0	0
T14	0	3814	0	0
T15	0	351	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224007	0	0
T1	10184	165	0	0
T2	2023	18	0	0
T3	63950	170	0	0
T7	338506	200	0	0
T8	277348	0	0	0
T9	25450	38	0	0
T10	69737	212	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2237	0	0
T14	0	206	0	0
T15	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	226315	0	0
GntImpliesValid_A	418699397	226315	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	226315	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2903863	0	0
ReadyAndValidImplyGrant_A	418699397	226315	0	0
ReqAndReadyImplyGrant_A	418699397	226315	0	0
ReqImpliesValid_A	418699397	545880	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	226315	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226315	0	0
T1	10184	144	0	0
T2	2023	15	0	0
T3	63950	191	0	0
T7	338506	222	0	0
T8	277348	0	0	0
T9	25450	34	0	0
T10	69737	194	0	0
T11	401697	533	0	0
T12	7636	17	0	0
T13	626316	1251	0	0
T14	0	179	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226315	0	0
T1	10184	144	0	0
T2	2023	15	0	0
T3	63950	191	0	0
T7	338506	222	0	0
T8	277348	0	0	0
T9	25450	34	0	0
T10	69737	194	0	0
T11	401697	533	0	0
T12	7636	17	0	0
T13	626316	1251	0	0
T14	0	179	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226315	0	0
T1	10184	144	0	0
T2	2023	15	0	0
T3	63950	191	0	0
T7	338506	222	0	0
T8	277348	0	0	0
T9	25450	34	0	0
T10	69737	194	0	0
T11	401697	533	0	0
T12	7636	17	0	0
T13	626316	1251	0	0
T14	0	179	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2903863	0	0
T1	10184	142	0	0
T2	2023	16	0	0
T3	63950	1441	0	0
T7	338506	75397	0	0
T8	277348	1	0	0
T9	25450	230	0	0
T10	69737	1525	0	0
T11	401697	1810	0	0
T12	7636	114	0	0
T13	626316	9498	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226315	0	0
T1	10184	144	0	0
T2	2023	15	0	0
T3	63950	191	0	0
T7	338506	222	0	0
T8	277348	0	0	0
T9	25450	34	0	0
T10	69737	194	0	0
T11	401697	533	0	0
T12	7636	17	0	0
T13	626316	1251	0	0
T14	0	179	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226315	0	0
T1	10184	144	0	0
T2	2023	15	0	0
T3	63950	191	0	0
T7	338506	222	0	0
T8	277348	0	0	0
T9	25450	34	0	0
T10	69737	194	0	0
T11	401697	533	0	0
T12	7636	17	0	0
T13	626316	1251	0	0
T14	0	179	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	545880	0	0
T1	10184	147	0	0
T2	2023	15	0	0
T3	63950	290	0	0
T7	338506	6264	0	0
T8	277348	0	0	0
T9	25450	34	0	0
T10	69737	298	0	0
T11	401697	1315	0	0
T12	7636	20	0	0
T13	626316	1522	0	0
T14	0	3629	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226315	0	0
T1	10184	144	0	0
T2	2023	15	0	0
T3	63950	191	0	0
T7	338506	222	0	0
T8	277348	0	0	0
T9	25450	34	0	0
T10	69737	194	0	0
T11	401697	533	0	0
T12	7636	17	0	0
T13	626316	1251	0	0
T14	0	179	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	231053	0	0
GntImpliesValid_A	418699397	231053	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	231053	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	5192706	0	0
ReadyAndValidImplyGrant_A	418699397	231053	0	0
ReqAndReadyImplyGrant_A	418699397	231053	0	0
ReqImpliesValid_A	418699397	1341183	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	231053	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231053	0	0
T1	10184	109	0	0
T2	2023	11	0	0
T3	63950	185	0	0
T7	338506	191	0	0
T8	277348	561	0	0
T9	25450	43	0	0
T10	69737	192	0	0
T11	401697	0	0	0
T12	7636	10	0	0
T13	626316	2763	0	0
T14	0	181	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231053	0	0
T1	10184	109	0	0
T2	2023	11	0	0
T3	63950	185	0	0
T7	338506	191	0	0
T8	277348	561	0	0
T9	25450	43	0	0
T10	69737	192	0	0
T11	401697	0	0	0
T12	7636	10	0	0
T13	626316	2763	0	0
T14	0	181	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231053	0	0
T1	10184	109	0	0
T2	2023	11	0	0
T3	63950	185	0	0
T7	338506	191	0	0
T8	277348	561	0	0
T9	25450	43	0	0
T10	69737	192	0	0
T11	401697	0	0	0
T12	7636	10	0	0
T13	626316	2763	0	0
T14	0	181	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	5192706	0	0
T1	10184	1173	0	0
T2	2023	54	0	0
T3	63950	2423	0	0
T7	338506	268293	0	0
T8	277348	17839	0	0
T9	25450	481	0	0
T10	69737	1868	0	0
T11	401697	0	0	0
T12	7636	85	0	0
T13	626316	16409	0	0
T14	0	46728	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231053	0	0
T1	10184	109	0	0
T2	2023	11	0	0
T3	63950	185	0	0
T7	338506	191	0	0
T8	277348	561	0	0
T9	25450	43	0	0
T10	69737	192	0	0
T11	401697	0	0	0
T12	7636	10	0	0
T13	626316	2763	0	0
T14	0	181	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231053	0	0
T1	10184	109	0	0
T2	2023	11	0	0
T3	63950	185	0	0
T7	338506	191	0	0
T8	277348	561	0	0
T9	25450	43	0	0
T10	69737	192	0	0
T11	401697	0	0	0
T12	7636	10	0	0
T13	626316	2763	0	0
T14	0	181	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	1341183	0	0
T1	10184	261	0	0
T2	2023	11	0	0
T3	63950	355	0	0
T7	338506	21327	0	0
T8	277348	6944	0	0
T9	25450	104	0	0
T10	69737	370	0	0
T11	401697	0	0	0
T12	7636	11	0	0
T13	626316	5295	0	0
T14	0	2992	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231053	0	0
T1	10184	109	0	0
T2	2023	11	0	0
T3	63950	185	0	0
T7	338506	191	0	0
T8	277348	561	0	0
T9	25450	43	0	0
T10	69737	192	0	0
T11	401697	0	0	0
T12	7636	10	0	0
T13	626316	2763	0	0
T14	0	181	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	222936	0	0
GntImpliesValid_A	418699397	222936	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	222936	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	5292153	0	0
ReadyAndValidImplyGrant_A	418699397	222936	0	0
ReqAndReadyImplyGrant_A	418699397	222936	0	0
ReqImpliesValid_A	418699397	1192069	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	222936	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	222936	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	194	0	0
T7	338506	197	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	206	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1735	0	0
T14	0	190	0	0
T15	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	222936	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	194	0	0
T7	338506	197	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	206	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1735	0	0
T14	0	190	0	0
T15	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	222936	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	194	0	0
T7	338506	197	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	206	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1735	0	0
T14	0	190	0	0
T15	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	5292153	0	0
T1	10184	977	0	0
T2	2023	81	0	0
T3	63950	1877	0	0
T7	338506	54966	0	0
T8	277348	0	0	0
T9	25450	540	0	0
T10	69737	2799	0	0
T11	401697	0	0	0
T12	7636	115	0	0
T13	626316	11797	0	0
T14	0	144268	0	0
T15	0	2933	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	222936	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	194	0	0
T7	338506	197	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	206	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1735	0	0
T14	0	190	0	0
T15	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	222936	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	194	0	0
T7	338506	197	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	206	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1735	0	0
T14	0	190	0	0
T15	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	1192069	0	0
T1	10184	215	0	0
T2	2023	20	0	0
T3	63950	268	0	0
T7	338506	2644	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	437	0	0
T11	401697	0	0	0
T12	7636	24	0	0
T13	626316	2564	0	0
T14	0	12497	0	0
T15	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	222936	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	194	0	0
T7	338506	197	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	206	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1735	0	0
T14	0	190	0	0
T15	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	231154	0	0
GntImpliesValid_A	418699397	231154	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	231154	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	4995030	0	0
ReadyAndValidImplyGrant_A	418699397	231154	0	0
ReqAndReadyImplyGrant_A	418699397	231154	0	0
ReqImpliesValid_A	418699397	1285484	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	231154	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231154	0	0
T1	10184	123	0	0
T2	2023	13	0	0
T3	63950	211	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	17	0	0
T13	626316	1224	0	0
T14	0	181	0	0
T15	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231154	0	0
T1	10184	123	0	0
T2	2023	13	0	0
T3	63950	211	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	17	0	0
T13	626316	1224	0	0
T14	0	181	0	0
T15	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231154	0	0
T1	10184	123	0	0
T2	2023	13	0	0
T3	63950	211	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	17	0	0
T13	626316	1224	0	0
T14	0	181	0	0
T15	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	4995030	0	0
T1	10184	589	0	0
T2	2023	68	0	0
T3	63950	3687	0	0
T7	338506	55573	0	0
T8	277348	0	0	0
T9	25450	1315	0	0
T10	69737	1512	0	0
T11	401697	0	0	0
T12	7636	440	0	0
T13	626316	15849	0	0
T14	0	158199	0	0
T15	0	5438	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231154	0	0
T1	10184	123	0	0
T2	2023	13	0	0
T3	63950	211	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	17	0	0
T13	626316	1224	0	0
T14	0	181	0	0
T15	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231154	0	0
T1	10184	123	0	0
T2	2023	13	0	0
T3	63950	211	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	17	0	0
T13	626316	1224	0	0
T14	0	181	0	0
T15	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	1285484	0	0
T1	10184	210	0	0
T2	2023	13	0	0
T3	63950	553	0	0
T7	338506	2063	0	0
T8	277348	0	0	0
T9	25450	99	0	0
T10	69737	233	0	0
T11	401697	0	0	0
T12	7636	169	0	0
T13	626316	1799	0	0
T14	0	11164	0	0
T15	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	231154	0	0
T1	10184	123	0	0
T2	2023	13	0	0
T3	63950	211	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	17	0	0
T13	626316	1224	0	0
T14	0	181	0	0
T15	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	219095	0	0
GntImpliesValid_A	418699397	219095	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	219095	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	4899453	0	0
ReadyAndValidImplyGrant_A	418699397	219095	0	0
ReqAndReadyImplyGrant_A	418699397	219095	0	0
ReqImpliesValid_A	418699397	1215072	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	219095	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	219095	0	0
T1	10184	126	0	0
T2	2023	10	0	0
T3	63950	181	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	217	0	0
T11	401697	516	0	0
T12	7636	11	0	0
T13	626316	1750	0	0
T14	0	174	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	219095	0	0
T1	10184	126	0	0
T2	2023	10	0	0
T3	63950	181	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	217	0	0
T11	401697	516	0	0
T12	7636	11	0	0
T13	626316	1750	0	0
T14	0	174	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	219095	0	0
T1	10184	126	0	0
T2	2023	10	0	0
T3	63950	181	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	217	0	0
T11	401697	516	0	0
T12	7636	11	0	0
T13	626316	1750	0	0
T14	0	174	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	4899453	0	0
T1	10184	1857	0	0
T2	2023	47	0	0
T3	63950	1182	0	0
T7	338506	97313	0	0
T8	277348	0	0	0
T9	25450	797	0	0
T10	69737	2608	0	0
T11	401697	2514	0	0
T12	7636	152	0	0
T13	626316	9665	0	0
T14	0	62071	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	219095	0	0
T1	10184	126	0	0
T2	2023	10	0	0
T3	63950	181	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	217	0	0
T11	401697	516	0	0
T12	7636	11	0	0
T13	626316	1750	0	0
T14	0	174	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	219095	0	0
T1	10184	126	0	0
T2	2023	10	0	0
T3	63950	181	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	217	0	0
T11	401697	516	0	0
T12	7636	11	0	0
T13	626316	1750	0	0
T14	0	174	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	1215072	0	0
T1	10184	432	0	0
T2	2023	10	0	0
T3	63950	260	0	0
T7	338506	6546	0	0
T8	277348	0	0	0
T9	25450	69	0	0
T10	69737	359	0	0
T11	401697	1136	0	0
T12	7636	11	0	0
T13	626316	2543	0	0
T14	0	4485	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	219095	0	0
T1	10184	126	0	0
T2	2023	10	0	0
T3	63950	181	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	217	0	0
T11	401697	516	0	0
T12	7636	11	0	0
T13	626316	1750	0	0
T14	0	174	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	237808	0	0
GntImpliesValid_A	418699397	237808	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	237808	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2959877	0	0
ReadyAndValidImplyGrant_A	418699397	237808	0	0
ReqAndReadyImplyGrant_A	418699397	237808	0	0
ReqImpliesValid_A	418699397	663191	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	237808	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	237808	0	0
T1	10184	125	0	0
T2	2023	17	0	0
T3	63950	199	0	0
T7	338506	180	0	0
T8	277348	0	0	0
T9	25450	39	0	0
T10	69737	210	0	0
T11	401697	1409	0	0
T12	7636	15	0	0
T13	626316	1281	0	0
T14	0	187	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	237808	0	0
T1	10184	125	0	0
T2	2023	17	0	0
T3	63950	199	0	0
T7	338506	180	0	0
T8	277348	0	0	0
T9	25450	39	0	0
T10	69737	210	0	0
T11	401697	1409	0	0
T12	7636	15	0	0
T13	626316	1281	0	0
T14	0	187	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	237808	0	0
T1	10184	125	0	0
T2	2023	17	0	0
T3	63950	199	0	0
T7	338506	180	0	0
T8	277348	0	0	0
T9	25450	39	0	0
T10	69737	210	0	0
T11	401697	1409	0	0
T12	7636	15	0	0
T13	626316	1281	0	0
T14	0	187	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2959877	0	0
T1	10184	120	0	0
T2	2023	18	0	0
T3	63950	1496	0	0
T7	338506	58905	0	0
T8	277348	1	0	0
T9	25450	272	0	0
T10	69737	1671	0	0
T11	401697	4632	0	0
T12	7636	89	0	0
T13	626316	9511	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	237808	0	0
T1	10184	125	0	0
T2	2023	17	0	0
T3	63950	199	0	0
T7	338506	180	0	0
T8	277348	0	0	0
T9	25450	39	0	0
T10	69737	210	0	0
T11	401697	1409	0	0
T12	7636	15	0	0
T13	626316	1281	0	0
T14	0	187	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	237808	0	0
T1	10184	125	0	0
T2	2023	17	0	0
T3	63950	199	0	0
T7	338506	180	0	0
T8	277348	0	0	0
T9	25450	39	0	0
T10	69737	210	0	0
T11	401697	1409	0	0
T12	7636	15	0	0
T13	626316	1281	0	0
T14	0	187	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	663191	0	0
T1	10184	131	0	0
T2	2023	17	0	0
T3	63950	343	0	0
T7	338506	4964	0	0
T8	277348	0	0	0
T9	25450	47	0	0
T10	69737	313	0	0
T11	401697	3388	0	0
T12	7636	15	0	0
T13	626316	1496	0	0
T14	0	5096	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	237808	0	0
T1	10184	125	0	0
T2	2023	17	0	0
T3	63950	199	0	0
T7	338506	180	0	0
T8	277348	0	0	0
T9	25450	39	0	0
T10	69737	210	0	0
T11	401697	1409	0	0
T12	7636	15	0	0
T13	626316	1281	0	0
T14	0	187	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	234421	0	0
GntImpliesValid_A	418699397	234421	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	234421	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2978636	0	0
ReadyAndValidImplyGrant_A	418699397	234421	0	0
ReqAndReadyImplyGrant_A	418699397	234421	0	0
ReqImpliesValid_A	418699397	619529	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	234421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	234421	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	197	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	44	0	0
T10	69737	197	0	0
T11	401697	0	0	0
T12	7636	8	0	0
T13	626316	1266	0	0
T14	0	206	0	0
T15	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	234421	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	197	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	44	0	0
T10	69737	197	0	0
T11	401697	0	0	0
T12	7636	8	0	0
T13	626316	1266	0	0
T14	0	206	0	0
T15	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	234421	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	197	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	44	0	0
T10	69737	197	0	0
T11	401697	0	0	0
T12	7636	8	0	0
T13	626316	1266	0	0
T14	0	206	0	0
T15	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2978636	0	0
T1	10184	139	0	0
T2	2023	14	0	0
T3	63950	1467	0	0
T7	338506	67202	0	0
T8	277348	1	0	0
T9	25450	330	0	0
T10	69737	1504	0	0
T11	401697	1	0	0
T12	7636	54	0	0
T13	626316	9557	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	234421	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	197	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	44	0	0
T10	69737	197	0	0
T11	401697	0	0	0
T12	7636	8	0	0
T13	626316	1266	0	0
T14	0	206	0	0
T15	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	234421	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	197	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	44	0	0
T10	69737	197	0	0
T11	401697	0	0	0
T12	7636	8	0	0
T13	626316	1266	0	0
T14	0	206	0	0
T15	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	619529	0	0
T1	10184	150	0	0
T2	2023	15	0	0
T3	63950	323	0	0
T7	338506	2538	0	0
T8	277348	0	0	0
T9	25450	62	0	0
T10	69737	340	0	0
T11	401697	0	0	0
T12	7636	8	0	0
T13	626316	1567	0	0
T14	0	5633	0	0
T15	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	234421	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	197	0	0
T7	338506	206	0	0
T8	277348	0	0	0
T9	25450	44	0	0
T10	69737	197	0	0
T11	401697	0	0	0
T12	7636	8	0	0
T13	626316	1266	0	0
T14	0	206	0	0
T15	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	218502	0	0
GntImpliesValid_A	418699397	218502	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	218502	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2979918	0	0
ReadyAndValidImplyGrant_A	418699397	218502	0	0
ReqAndReadyImplyGrant_A	418699397	218502	0	0
ReqImpliesValid_A	418699397	574618	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	218502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	218502	0	0
T1	10184	141	0	0
T2	2023	18	0	0
T3	63950	188	0	0
T7	338506	205	0	0
T8	277348	0	0	0
T9	25450	42	0	0
T10	69737	188	0	0
T11	401697	0	0	0
T12	7636	19	0	0
T13	626316	1881	0	0
T14	0	212	0	0
T15	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	218502	0	0
T1	10184	141	0	0
T2	2023	18	0	0
T3	63950	188	0	0
T7	338506	205	0	0
T8	277348	0	0	0
T9	25450	42	0	0
T10	69737	188	0	0
T11	401697	0	0	0
T12	7636	19	0	0
T13	626316	1881	0	0
T14	0	212	0	0
T15	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	218502	0	0
T1	10184	141	0	0
T2	2023	18	0	0
T3	63950	188	0	0
T7	338506	205	0	0
T8	277348	0	0	0
T9	25450	42	0	0
T10	69737	188	0	0
T11	401697	0	0	0
T12	7636	19	0	0
T13	626316	1881	0	0
T14	0	212	0	0
T15	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2979918	0	0
T1	10184	139	0	0
T2	2023	18	0	0
T3	63950	1420	0	0
T7	338506	64296	0	0
T8	277348	1	0	0
T9	25450	422	0	0
T10	69737	1368	0	0
T11	401697	1	0	0
T12	7636	184	0	0
T13	626316	12821	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	218502	0	0
T1	10184	141	0	0
T2	2023	18	0	0
T3	63950	188	0	0
T7	338506	205	0	0
T8	277348	0	0	0
T9	25450	42	0	0
T10	69737	188	0	0
T11	401697	0	0	0
T12	7636	19	0	0
T13	626316	1881	0	0
T14	0	212	0	0
T15	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	218502	0	0
T1	10184	141	0	0
T2	2023	18	0	0
T3	63950	188	0	0
T7	338506	205	0	0
T8	277348	0	0	0
T9	25450	42	0	0
T10	69737	188	0	0
T11	401697	0	0	0
T12	7636	19	0	0
T13	626316	1881	0	0
T14	0	212	0	0
T15	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	574618	0	0
T1	10184	144	0	0
T2	2023	19	0	0
T3	63950	281	0	0
T7	338506	2803	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	256	0	0
T11	401697	0	0	0
T12	7636	19	0	0
T13	626316	4151	0	0
T14	0	6761	0	0
T15	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	218502	0	0
T1	10184	141	0	0
T2	2023	18	0	0
T3	63950	188	0	0
T7	338506	205	0	0
T8	277348	0	0	0
T9	25450	42	0	0
T10	69737	188	0	0
T11	401697	0	0	0
T12	7636	19	0	0
T13	626316	1881	0	0
T14	0	212	0	0
T15	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	248981	0	0
GntImpliesValid_A	418699397	248981	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	248981	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2928599	0	0
ReadyAndValidImplyGrant_A	418699397	248981	0	0
ReqAndReadyImplyGrant_A	418699397	248981	0	0
ReqImpliesValid_A	418699397	653576	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	248981	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	248981	0	0
T1	10184	146	0	0
T2	2023	9	0	0
T3	63950	190	0	0
T7	338506	187	0	0
T8	277348	475	0	0
T9	25450	58	0	0
T10	69737	216	0	0
T11	401697	0	0	0
T12	7636	21	0	0
T13	626316	1631	0	0
T14	0	194	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	248981	0	0
T1	10184	146	0	0
T2	2023	9	0	0
T3	63950	190	0	0
T7	338506	187	0	0
T8	277348	475	0	0
T9	25450	58	0	0
T10	69737	216	0	0
T11	401697	0	0	0
T12	7636	21	0	0
T13	626316	1631	0	0
T14	0	194	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	248981	0	0
T1	10184	146	0	0
T2	2023	9	0	0
T3	63950	190	0	0
T7	338506	187	0	0
T8	277348	475	0	0
T9	25450	58	0	0
T10	69737	216	0	0
T11	401697	0	0	0
T12	7636	21	0	0
T13	626316	1631	0	0
T14	0	194	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2928599	0	0
T1	10184	142	0	0
T2	2023	10	0	0
T3	63950	1487	0	0
T7	338506	58250	0	0
T8	277348	1476	0	0
T9	25450	418	0	0
T10	69737	1569	0	0
T11	401697	1	0	0
T12	7636	145	0	0
T13	626316	11495	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	248981	0	0
T1	10184	146	0	0
T2	2023	9	0	0
T3	63950	190	0	0
T7	338506	187	0	0
T8	277348	475	0	0
T9	25450	58	0	0
T10	69737	216	0	0
T11	401697	0	0	0
T12	7636	21	0	0
T13	626316	1631	0	0
T14	0	194	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	248981	0	0
T1	10184	146	0	0
T2	2023	9	0	0
T3	63950	190	0	0
T7	338506	187	0	0
T8	277348	475	0	0
T9	25450	58	0	0
T10	69737	216	0	0
T11	401697	0	0	0
T12	7636	21	0	0
T13	626316	1631	0	0
T14	0	194	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	653576	0	0
T1	10184	151	0	0
T2	2023	9	0	0
T3	63950	308	0	0
T7	338506	2572	0	0
T8	277348	1151	0	0
T9	25450	60	0	0
T10	69737	285	0	0
T11	401697	0	0	0
T12	7636	21	0	0
T13	626316	3624	0	0
T14	0	5744	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	248981	0	0
T1	10184	146	0	0
T2	2023	9	0	0
T3	63950	190	0	0
T7	338506	187	0	0
T8	277348	475	0	0
T9	25450	58	0	0
T10	69737	216	0	0
T11	401697	0	0	0
T12	7636	21	0	0
T13	626316	1631	0	0
T14	0	194	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	232891	0	0
GntImpliesValid_A	418699397	232891	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	232891	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2977898	0	0
ReadyAndValidImplyGrant_A	418699397	232891	0	0
ReqAndReadyImplyGrant_A	418699397	232891	0	0
ReqImpliesValid_A	418699397	622327	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	232891	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	232891	0	0
T1	10184	139	0	0
T2	2023	15	0	0
T3	63950	218	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	43	0	0
T10	69737	233	0	0
T11	401697	0	0	0
T12	7636	11	0	0
T13	626316	1797	0	0
T14	0	194	0	0
T15	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	232891	0	0
T1	10184	139	0	0
T2	2023	15	0	0
T3	63950	218	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	43	0	0
T10	69737	233	0	0
T11	401697	0	0	0
T12	7636	11	0	0
T13	626316	1797	0	0
T14	0	194	0	0
T15	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	232891	0	0
T1	10184	139	0	0
T2	2023	15	0	0
T3	63950	218	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	43	0	0
T10	69737	233	0	0
T11	401697	0	0	0
T12	7636	11	0	0
T13	626316	1797	0	0
T14	0	194	0	0
T15	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2977898	0	0
T1	10184	134	0	0
T2	2023	16	0	0
T3	63950	1602	0	0
T7	338506	64254	0	0
T8	277348	1	0	0
T9	25450	299	0	0
T10	69737	1873	0	0
T11	401697	1	0	0
T12	7636	80	0	0
T13	626316	12342	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	232891	0	0
T1	10184	139	0	0
T2	2023	15	0	0
T3	63950	218	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	43	0	0
T10	69737	233	0	0
T11	401697	0	0	0
T12	7636	11	0	0
T13	626316	1797	0	0
T14	0	194	0	0
T15	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	232891	0	0
T1	10184	139	0	0
T2	2023	15	0	0
T3	63950	218	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	43	0	0
T10	69737	233	0	0
T11	401697	0	0	0
T12	7636	11	0	0
T13	626316	1797	0	0
T14	0	194	0	0
T15	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	622327	0	0
T1	10184	145	0	0
T2	2023	15	0	0
T3	63950	311	0	0
T7	338506	4228	0	0
T8	277348	0	0	0
T9	25450	47	0	0
T10	69737	333	0	0
T11	401697	0	0	0
T12	7636	12	0	0
T13	626316	2860	0	0
T14	0	7631	0	0
T15	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	232891	0	0
T1	10184	139	0	0
T2	2023	15	0	0
T3	63950	218	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	43	0	0
T10	69737	233	0	0
T11	401697	0	0	0
T12	7636	11	0	0
T13	626316	1797	0	0
T14	0	194	0	0
T15	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	210977	0	0
GntImpliesValid_A	418699397	210977	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	210977	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2865615	0	0
ReadyAndValidImplyGrant_A	418699397	210977	0	0
ReqAndReadyImplyGrant_A	418699397	210977	0	0
ReqImpliesValid_A	418699397	538083	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	210977	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	210977	0	0
T1	10184	118	0	0
T2	2023	22	0	0
T3	63950	232	0	0
T7	338506	219	0	0
T8	277348	0	0	0
T9	25450	61	0	0
T10	69737	191	0	0
T11	401697	486	0	0
T12	7636	14	0	0
T13	626316	1281	0	0
T14	0	192	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	210977	0	0
T1	10184	118	0	0
T2	2023	22	0	0
T3	63950	232	0	0
T7	338506	219	0	0
T8	277348	0	0	0
T9	25450	61	0	0
T10	69737	191	0	0
T11	401697	486	0	0
T12	7636	14	0	0
T13	626316	1281	0	0
T14	0	192	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	210977	0	0
T1	10184	118	0	0
T2	2023	22	0	0
T3	63950	232	0	0
T7	338506	219	0	0
T8	277348	0	0	0
T9	25450	61	0	0
T10	69737	191	0	0
T11	401697	486	0	0
T12	7636	14	0	0
T13	626316	1281	0	0
T14	0	192	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2865615	0	0
T1	10184	111	0	0
T2	2023	21	0	0
T3	63950	1761	0	0
T7	338506	70680	0	0
T8	277348	1	0	0
T9	25450	433	0	0
T10	69737	1349	0	0
T11	401697	1484	0	0
T12	7636	111	0	0
T13	626316	9747	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	210977	0	0
T1	10184	118	0	0
T2	2023	22	0	0
T3	63950	232	0	0
T7	338506	219	0	0
T8	277348	0	0	0
T9	25450	61	0	0
T10	69737	191	0	0
T11	401697	486	0	0
T12	7636	14	0	0
T13	626316	1281	0	0
T14	0	192	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	210977	0	0
T1	10184	118	0	0
T2	2023	22	0	0
T3	63950	232	0	0
T7	338506	219	0	0
T8	277348	0	0	0
T9	25450	61	0	0
T10	69737	191	0	0
T11	401697	486	0	0
T12	7636	14	0	0
T13	626316	1281	0	0
T14	0	192	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	538083	0	0
T1	10184	126	0	0
T2	2023	24	0	0
T3	63950	327	0	0
T7	338506	2060	0	0
T8	277348	0	0	0
T9	25450	81	0	0
T10	69737	259	0	0
T11	401697	1180	0	0
T12	7636	21	0	0
T13	626316	1656	0	0
T14	0	5336	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	210977	0	0
T1	10184	118	0	0
T2	2023	22	0	0
T3	63950	232	0	0
T7	338506	219	0	0
T8	277348	0	0	0
T9	25450	61	0	0
T10	69737	191	0	0
T11	401697	486	0	0
T12	7636	14	0	0
T13	626316	1281	0	0
T14	0	192	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	240869	0	0
GntImpliesValid_A	418699397	240869	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	240869	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2935776	0	0
ReadyAndValidImplyGrant_A	418699397	240869	0	0
ReqAndReadyImplyGrant_A	418699397	240869	0	0
ReqImpliesValid_A	418699397	614918	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	240869	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	240869	0	0
T1	10184	138	0	0
T2	2023	9	0	0
T3	63950	201	0	0
T7	338506	192	0	0
T8	277348	0	0	0
T9	25450	48	0	0
T10	69737	178	0	0
T11	401697	910	0	0
T12	7636	11	0	0
T13	626316	1198	0	0
T14	0	196	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	240869	0	0
T1	10184	138	0	0
T2	2023	9	0	0
T3	63950	201	0	0
T7	338506	192	0	0
T8	277348	0	0	0
T9	25450	48	0	0
T10	69737	178	0	0
T11	401697	910	0	0
T12	7636	11	0	0
T13	626316	1198	0	0
T14	0	196	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	240869	0	0
T1	10184	138	0	0
T2	2023	9	0	0
T3	63950	201	0	0
T7	338506	192	0	0
T8	277348	0	0	0
T9	25450	48	0	0
T10	69737	178	0	0
T11	401697	910	0	0
T12	7636	11	0	0
T13	626316	1198	0	0
T14	0	196	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2935776	0	0
T1	10184	132	0	0
T2	2023	10	0	0
T3	63950	1481	0	0
T7	338506	61868	0	0
T8	277348	1	0	0
T9	25450	380	0	0
T10	69737	1234	0	0
T11	401697	2804	0	0
T12	7636	66	0	0
T13	626316	9238	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	240869	0	0
T1	10184	138	0	0
T2	2023	9	0	0
T3	63950	201	0	0
T7	338506	192	0	0
T8	277348	0	0	0
T9	25450	48	0	0
T10	69737	178	0	0
T11	401697	910	0	0
T12	7636	11	0	0
T13	626316	1198	0	0
T14	0	196	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	240869	0	0
T1	10184	138	0	0
T2	2023	9	0	0
T3	63950	201	0	0
T7	338506	192	0	0
T8	277348	0	0	0
T9	25450	48	0	0
T10	69737	178	0	0
T11	401697	910	0	0
T12	7636	11	0	0
T13	626316	1198	0	0
T14	0	196	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	614918	0	0
T1	10184	145	0	0
T2	2023	9	0	0
T3	63950	275	0	0
T7	338506	1123	0	0
T8	277348	0	0	0
T9	25450	48	0	0
T10	69737	231	0	0
T11	401697	2289	0	0
T12	7636	11	0	0
T13	626316	1457	0	0
T14	0	5124	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	240869	0	0
T1	10184	138	0	0
T2	2023	9	0	0
T3	63950	201	0	0
T7	338506	192	0	0
T8	277348	0	0	0
T9	25450	48	0	0
T10	69737	178	0	0
T11	401697	910	0	0
T12	7636	11	0	0
T13	626316	1198	0	0
T14	0	196	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	224008	0	0
GntImpliesValid_A	418699397	224008	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	224008	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2960938	0	0
ReadyAndValidImplyGrant_A	418699397	224008	0	0
ReqAndReadyImplyGrant_A	418699397	224008	0	0
ReqImpliesValid_A	418699397	552193	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	224008	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224008	0	0
T1	10184	138	0	0
T2	2023	20	0	0
T3	63950	206	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	178	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1189	0	0
T14	0	190	0	0
T15	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224008	0	0
T1	10184	138	0	0
T2	2023	20	0	0
T3	63950	206	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	178	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1189	0	0
T14	0	190	0	0
T15	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224008	0	0
T1	10184	138	0	0
T2	2023	20	0	0
T3	63950	206	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	178	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1189	0	0
T14	0	190	0	0
T15	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2960938	0	0
T1	10184	135	0	0
T2	2023	19	0	0
T3	63950	1608	0	0
T7	338506	68156	0	0
T8	277348	1	0	0
T9	25450	241	0	0
T10	69737	1347	0	0
T11	401697	1	0	0
T12	7636	85	0	0
T13	626316	8878	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224008	0	0
T1	10184	138	0	0
T2	2023	20	0	0
T3	63950	206	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	178	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1189	0	0
T14	0	190	0	0
T15	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224008	0	0
T1	10184	138	0	0
T2	2023	20	0	0
T3	63950	206	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	178	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1189	0	0
T14	0	190	0	0
T15	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	552193	0	0
T1	10184	142	0	0
T2	2023	22	0	0
T3	63950	296	0	0
T7	338506	3950	0	0
T8	277348	0	0	0
T9	25450	66	0	0
T10	69737	229	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1360	0	0
T14	0	4874	0	0
T15	0	105	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224008	0	0
T1	10184	138	0	0
T2	2023	20	0	0
T3	63950	206	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	40	0	0
T10	69737	178	0	0
T11	401697	0	0	0
T12	7636	13	0	0
T13	626316	1189	0	0
T14	0	190	0	0
T15	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	257108	0	0
GntImpliesValid_A	418699397	257108	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	257108	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	3122795	0	0
ReadyAndValidImplyGrant_A	418699397	257108	0	0
ReqAndReadyImplyGrant_A	418699397	257108	0	0
ReqImpliesValid_A	418699397	670551	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	257108	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	257108	0	0
T1	10184	157	0	0
T2	2023	13	0	0
T3	63950	212	0	0
T7	338506	227	0	0
T8	277348	495	0	0
T9	25450	98	0	0
T10	69737	190	0	0
T11	401697	905	0	0
T12	7636	22	0	0
T13	626316	1367	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	257108	0	0
T1	10184	157	0	0
T2	2023	13	0	0
T3	63950	212	0	0
T7	338506	227	0	0
T8	277348	495	0	0
T9	25450	98	0	0
T10	69737	190	0	0
T11	401697	905	0	0
T12	7636	22	0	0
T13	626316	1367	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	257108	0	0
T1	10184	157	0	0
T2	2023	13	0	0
T3	63950	212	0	0
T7	338506	227	0	0
T8	277348	495	0	0
T9	25450	98	0	0
T10	69737	190	0	0
T11	401697	905	0	0
T12	7636	22	0	0
T13	626316	1367	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	3122795	0	0
T1	10184	148	0	0
T2	2023	14	0	0
T3	63950	1548	0	0
T7	338506	74867	0	0
T8	277348	1597	0	0
T9	25450	774	0	0
T10	69737	1358	0	0
T11	401697	2971	0	0
T12	7636	173	0	0
T13	626316	10156	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	257108	0	0
T1	10184	157	0	0
T2	2023	13	0	0
T3	63950	212	0	0
T7	338506	227	0	0
T8	277348	495	0	0
T9	25450	98	0	0
T10	69737	190	0	0
T11	401697	905	0	0
T12	7636	22	0	0
T13	626316	1367	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	257108	0	0
T1	10184	157	0	0
T2	2023	13	0	0
T3	63950	212	0	0
T7	338506	227	0	0
T8	277348	495	0	0
T9	25450	98	0	0
T10	69737	190	0	0
T11	401697	905	0	0
T12	7636	22	0	0
T13	626316	1367	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	670551	0	0
T1	10184	167	0	0
T2	2023	13	0	0
T3	63950	299	0	0
T7	338506	1867	0	0
T8	277348	1149	0	0
T9	25450	124	0	0
T10	69737	320	0	0
T11	401697	2175	0	0
T12	7636	22	0	0
T13	626316	1650	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	257108	0	0
T1	10184	157	0	0
T2	2023	13	0	0
T3	63950	212	0	0
T7	338506	227	0	0
T8	277348	495	0	0
T9	25450	98	0	0
T10	69737	190	0	0
T11	401697	905	0	0
T12	7636	22	0	0
T13	626316	1367	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	229016	0	0
GntImpliesValid_A	418699397	229016	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	229016	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2972565	0	0
ReadyAndValidImplyGrant_A	418699397	229016	0	0
ReqAndReadyImplyGrant_A	418699397	229016	0	0
ReqImpliesValid_A	418699397	606926	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	229016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	229016	0	0
T1	10184	136	0	0
T2	2023	14	0	0
T3	63950	178	0	0
T7	338506	234	0	0
T8	277348	0	0	0
T9	25450	36	0	0
T10	69737	186	0	0
T11	401697	0	0	0
T12	7636	16	0	0
T13	626316	1797	0	0
T14	0	185	0	0
T15	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	229016	0	0
T1	10184	136	0	0
T2	2023	14	0	0
T3	63950	178	0	0
T7	338506	234	0	0
T8	277348	0	0	0
T9	25450	36	0	0
T10	69737	186	0	0
T11	401697	0	0	0
T12	7636	16	0	0
T13	626316	1797	0	0
T14	0	185	0	0
T15	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	229016	0	0
T1	10184	136	0	0
T2	2023	14	0	0
T3	63950	178	0	0
T7	338506	234	0	0
T8	277348	0	0	0
T9	25450	36	0	0
T10	69737	186	0	0
T11	401697	0	0	0
T12	7636	16	0	0
T13	626316	1797	0	0
T14	0	185	0	0
T15	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2972565	0	0
T1	10184	133	0	0
T2	2023	15	0	0
T3	63950	1324	0	0
T7	338506	70207	0	0
T8	277348	1	0	0
T9	25450	210	0	0
T10	69737	1468	0	0
T11	401697	1	0	0
T12	7636	135	0	0
T13	626316	13390	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	229016	0	0
T1	10184	136	0	0
T2	2023	14	0	0
T3	63950	178	0	0
T7	338506	234	0	0
T8	277348	0	0	0
T9	25450	36	0	0
T10	69737	186	0	0
T11	401697	0	0	0
T12	7636	16	0	0
T13	626316	1797	0	0
T14	0	185	0	0
T15	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	229016	0	0
T1	10184	136	0	0
T2	2023	14	0	0
T3	63950	178	0	0
T7	338506	234	0	0
T8	277348	0	0	0
T9	25450	36	0	0
T10	69737	186	0	0
T11	401697	0	0	0
T12	7636	16	0	0
T13	626316	1797	0	0
T14	0	185	0	0
T15	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	606926	0	0
T1	10184	140	0	0
T2	2023	14	0	0
T3	63950	263	0	0
T7	338506	6037	0	0
T8	277348	0	0	0
T9	25450	36	0	0
T10	69737	269	0	0
T11	401697	0	0	0
T12	7636	16	0	0
T13	626316	2825	0	0
T14	0	1354	0	0
T15	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	229016	0	0
T1	10184	136	0	0
T2	2023	14	0	0
T3	63950	178	0	0
T7	338506	234	0	0
T8	277348	0	0	0
T9	25450	36	0	0
T10	69737	186	0	0
T11	401697	0	0	0
T12	7636	16	0	0
T13	626316	1797	0	0
T14	0	185	0	0
T15	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	223341	0	0
GntImpliesValid_A	418699397	223341	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	223341	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2971793	0	0
ReadyAndValidImplyGrant_A	418699397	223341	0	0
ReqAndReadyImplyGrant_A	418699397	223341	0	0
ReqImpliesValid_A	418699397	568094	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	223341	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	223341	0	0
T1	10184	151	0	0
T2	2023	11	0	0
T3	63950	211	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	45	0	0
T10	69737	183	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1227	0	0
T14	0	207	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	223341	0	0
T1	10184	151	0	0
T2	2023	11	0	0
T3	63950	211	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	45	0	0
T10	69737	183	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1227	0	0
T14	0	207	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	223341	0	0
T1	10184	151	0	0
T2	2023	11	0	0
T3	63950	211	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	45	0	0
T10	69737	183	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1227	0	0
T14	0	207	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2971793	0	0
T1	10184	144	0	0
T2	2023	12	0	0
T3	63950	1608	0	0
T7	338506	73075	0	0
T8	277348	1	0	0
T9	25450	358	0	0
T10	69737	1435	0	0
T11	401697	1	0	0
T12	7636	128	0	0
T13	626316	9312	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	223341	0	0
T1	10184	151	0	0
T2	2023	11	0	0
T3	63950	211	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	45	0	0
T10	69737	183	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1227	0	0
T14	0	207	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	223341	0	0
T1	10184	151	0	0
T2	2023	11	0	0
T3	63950	211	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	45	0	0
T10	69737	183	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1227	0	0
T14	0	207	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	568094	0	0
T1	10184	159	0	0
T2	2023	11	0	0
T3	63950	360	0	0
T7	338506	5018	0	0
T8	277348	0	0	0
T9	25450	45	0	0
T10	69737	241	0	0
T11	401697	0	0	0
T12	7636	18	0	0
T13	626316	1483	0	0
T14	0	6883	0	0
T15	0	223	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	223341	0	0
T1	10184	151	0	0
T2	2023	11	0	0
T3	63950	211	0	0
T7	338506	216	0	0
T8	277348	0	0	0
T9	25450	45	0	0
T10	69737	183	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1227	0	0
T14	0	207	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	224571	0	0
GntImpliesValid_A	418699397	224571	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	224571	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2842854	0	0
ReadyAndValidImplyGrant_A	418699397	224571	0	0
ReqAndReadyImplyGrant_A	418699397	224571	0	0
ReqImpliesValid_A	418699397	571702	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	224571	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224571	0	0
T1	10184	132	0	0
T2	2023	14	0	0
T3	63950	175	0	0
T7	338506	213	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	198	0	0
T11	401697	443	0	0
T12	7636	13	0	0
T13	626316	2140	0	0
T14	0	185	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224571	0	0
T1	10184	132	0	0
T2	2023	14	0	0
T3	63950	175	0	0
T7	338506	213	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	198	0	0
T11	401697	443	0	0
T12	7636	13	0	0
T13	626316	2140	0	0
T14	0	185	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224571	0	0
T1	10184	132	0	0
T2	2023	14	0	0
T3	63950	175	0	0
T7	338506	213	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	198	0	0
T11	401697	443	0	0
T12	7636	13	0	0
T13	626316	2140	0	0
T14	0	185	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2842854	0	0
T1	10184	121	0	0
T2	2023	15	0	0
T3	63950	1207	0	0
T7	338506	75268	0	0
T8	277348	1	0	0
T9	25450	381	0	0
T10	69737	1572	0	0
T11	401697	1317	0	0
T12	7636	64	0	0
T13	626316	14486	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224571	0	0
T1	10184	132	0	0
T2	2023	14	0	0
T3	63950	175	0	0
T7	338506	213	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	198	0	0
T11	401697	443	0	0
T12	7636	13	0	0
T13	626316	2140	0	0
T14	0	185	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224571	0	0
T1	10184	132	0	0
T2	2023	14	0	0
T3	63950	175	0	0
T7	338506	213	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	198	0	0
T11	401697	443	0	0
T12	7636	13	0	0
T13	626316	2140	0	0
T14	0	185	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	571702	0	0
T1	10184	144	0	0
T2	2023	14	0	0
T3	63950	311	0	0
T7	338506	2068	0	0
T8	277348	0	0	0
T9	25450	57	0	0
T10	69737	229	0	0
T11	401697	1124	0	0
T12	7636	13	0	0
T13	626316	5249	0	0
T14	0	2739	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	224571	0	0
T1	10184	132	0	0
T2	2023	14	0	0
T3	63950	175	0	0
T7	338506	213	0	0
T8	277348	0	0	0
T9	25450	50	0	0
T10	69737	198	0	0
T11	401697	443	0	0
T12	7636	13	0	0
T13	626316	2140	0	0
T14	0	185	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	226917	0	0
GntImpliesValid_A	418699397	226917	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	226917	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2976495	0	0
ReadyAndValidImplyGrant_A	418699397	226917	0	0
ReqAndReadyImplyGrant_A	418699397	226917	0	0
ReqImpliesValid_A	418699397	624094	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	226917	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226917	0	0
T1	10184	145	0	0
T2	2023	21	0	0
T3	63950	180	0	0
T7	338506	177	0	0
T8	277348	0	0	0
T9	25450	41	0	0
T10	69737	163	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2289	0	0
T14	0	188	0	0
T15	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226917	0	0
T1	10184	145	0	0
T2	2023	21	0	0
T3	63950	180	0	0
T7	338506	177	0	0
T8	277348	0	0	0
T9	25450	41	0	0
T10	69737	163	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2289	0	0
T14	0	188	0	0
T15	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226917	0	0
T1	10184	145	0	0
T2	2023	21	0	0
T3	63950	180	0	0
T7	338506	177	0	0
T8	277348	0	0	0
T9	25450	41	0	0
T10	69737	163	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2289	0	0
T14	0	188	0	0
T15	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2976495	0	0
T1	10184	140	0	0
T2	2023	21	0	0
T3	63950	1241	0	0
T7	338506	57780	0	0
T8	277348	1	0	0
T9	25450	335	0	0
T10	69737	1149	0	0
T11	401697	1	0	0
T12	7636	124	0	0
T13	626316	15994	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226917	0	0
T1	10184	145	0	0
T2	2023	21	0	0
T3	63950	180	0	0
T7	338506	177	0	0
T8	277348	0	0	0
T9	25450	41	0	0
T10	69737	163	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2289	0	0
T14	0	188	0	0
T15	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226917	0	0
T1	10184	145	0	0
T2	2023	21	0	0
T3	63950	180	0	0
T7	338506	177	0	0
T8	277348	0	0	0
T9	25450	41	0	0
T10	69737	163	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2289	0	0
T14	0	188	0	0
T15	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	624094	0	0
T1	10184	151	0	0
T2	2023	22	0	0
T3	63950	265	0	0
T7	338506	2874	0	0
T8	277348	0	0	0
T9	25450	54	0	0
T10	69737	239	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	5630	0	0
T14	0	4524	0	0
T15	0	783	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	226917	0	0
T1	10184	145	0	0
T2	2023	21	0	0
T3	63950	180	0	0
T7	338506	177	0	0
T8	277348	0	0	0
T9	25450	41	0	0
T10	69737	163	0	0
T11	401697	0	0	0
T12	7636	15	0	0
T13	626316	2289	0	0
T14	0	188	0	0
T15	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	225658	0	0
GntImpliesValid_A	418699397	225658	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	225658	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	2932667	0	0
ReadyAndValidImplyGrant_A	418699397	225658	0	0
ReqAndReadyImplyGrant_A	418699397	225658	0	0
ReqImpliesValid_A	418699397	592292	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	0	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	225658	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	225658	0	0
T1	10184	140	0	0
T2	2023	12	0	0
T3	63950	178	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	56	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1735	0	0
T14	0	187	0	0
T15	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	225658	0	0
T1	10184	140	0	0
T2	2023	12	0	0
T3	63950	178	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	56	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1735	0	0
T14	0	187	0	0
T15	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	225658	0	0
T1	10184	140	0	0
T2	2023	12	0	0
T3	63950	178	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	56	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1735	0	0
T14	0	187	0	0
T15	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2932667	0	0
T1	10184	133	0	0
T2	2023	13	0	0
T3	63950	1272	0	0
T7	338506	66838	0	0
T8	277348	1	0	0
T9	25450	456	0	0
T10	69737	1320	0	0
T11	401697	1	0	0
T12	7636	113	0	0
T13	626316	12136	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	225658	0	0
T1	10184	140	0	0
T2	2023	12	0	0
T3	63950	178	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	56	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1735	0	0
T14	0	187	0	0
T15	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	225658	0	0
T1	10184	140	0	0
T2	2023	12	0	0
T3	63950	178	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	56	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1735	0	0
T14	0	187	0	0
T15	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	592292	0	0
T1	10184	148	0	0
T2	2023	12	0	0
T3	63950	264	0	0
T7	338506	2421	0	0
T8	277348	0	0	0
T9	25450	56	0	0
T10	69737	237	0	0
T11	401697	0	0	0
T12	7636	27	0	0
T13	626316	2599	0	0
T14	0	2289	0	0
T15	0	390	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	225658	0	0
T1	10184	140	0	0
T2	2023	12	0	0
T3	63950	178	0	0
T7	338506	201	0	0
T8	277348	0	0	0
T9	25450	56	0	0
T10	69737	194	0	0
T11	401697	0	0	0
T12	7636	14	0	0
T13	626316	1735	0	0
T14	0	187	0	0
T15	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	924754	0	0
GntImpliesValid_A	418699397	924754	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	924754	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	11068892	0	0
ReadyAndValidImplyGrant_A	418699397	924754	0	0
ReqAndReadyImplyGrant_A	418699397	924754	0	0
ReqImpliesValid_A	418699397	2203134	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	22919	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	924754	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	924754	0	0
T1	10184	597	0	0
T2	2023	49	0	0
T3	63950	836	0	0
T7	338506	797	0	0
T8	277348	910	0	0
T9	25450	154	0	0
T10	69737	701	0	0
T11	401697	1382	0	0
T12	7636	51	0	0
T13	626316	7018	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	924754	0	0
T1	10184	597	0	0
T2	2023	49	0	0
T3	63950	836	0	0
T7	338506	797	0	0
T8	277348	910	0	0
T9	25450	154	0	0
T10	69737	701	0	0
T11	401697	1382	0	0
T12	7636	51	0	0
T13	626316	7018	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	924754	0	0
T1	10184	597	0	0
T2	2023	49	0	0
T3	63950	836	0	0
T7	338506	797	0	0
T8	277348	910	0	0
T9	25450	154	0	0
T10	69737	701	0	0
T11	401697	1382	0	0
T12	7636	51	0	0
T13	626316	7018	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	11068892	0	0
T1	10184	1	0	0
T2	2023	1	0	0
T3	63950	5541	0	0
T7	338506	237097	0	0
T8	277348	2405	0	0
T9	25450	988	0	0
T10	69737	4561	0	0
T11	401697	3826	0	0
T12	7636	346	0	0
T13	626316	40649	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	924754	0	0
T1	10184	597	0	0
T2	2023	49	0	0
T3	63950	836	0	0
T7	338506	797	0	0
T8	277348	910	0	0
T9	25450	154	0	0
T10	69737	701	0	0
T11	401697	1382	0	0
T12	7636	51	0	0
T13	626316	7018	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	924754	0	0
T1	10184	597	0	0
T2	2023	49	0	0
T3	63950	836	0	0
T7	338506	797	0	0
T8	277348	910	0	0
T9	25450	154	0	0
T10	69737	701	0	0
T11	401697	1382	0	0
T12	7636	51	0	0
T13	626316	7018	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	2203134	0	0
T1	10184	597	0	0
T2	2023	49	0	0
T3	63950	1459	0	0
T7	338506	23956	0	0
T8	277348	1825	0	0
T9	25450	215	0	0
T10	69737	1206	0	0
T11	401697	2622	0	0
T12	7636	62	0	0
T13	626316	11248	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	22919	0	900
T1	10184	8	0	1
T2	2023	0	0	1
T3	63950	0	0	1
T4	0	14	0	0
T7	338506	0	0	1
T8	277348	16	0	1
T9	25450	0	0	1
T10	69737	0	0	1
T11	401697	10	0	1
T12	7636	0	0	1
T13	626316	9	0	1
T17	0	14	0	0
T18	0	11	0	0
T19	0	5	0	0
T20	0	10	0	0
T21	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	924754	0	0
T1	10184	597	0	0
T2	2023	49	0	0
T3	63950	836	0	0
T7	338506	797	0	0
T8	277348	910	0	0
T9	25450	154	0	0
T10	69737	701	0	0
T11	401697	1382	0	0
T12	7636	51	0	0
T13	626316	7018	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418699397	418572864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418699397	919755	0	0
GntImpliesValid_A	418699397	919755	0	0
GrantKnown_A	418699397	418572864	0	0
IdxKnown_A	418699397	418572864	0	0
IndexIsCorrect_A	418699397	919755	0	0
LockArbDecision_A	418699397	0	0	0
NoReadyValidNoGrant_A	418699397	350956469	0	0
ReadyAndValidImplyGrant_A	418699397	919755	0	0
ReqAndReadyImplyGrant_A	418699397	919755	0	0
ReqImpliesValid_A	418699397	13168471	0	0
ReqStaysHighUntilGranted0_M	418699397	0	0	0
RoundRobin_A	418699397	27955	0	900
ValidKnown_A	418699397	418572864	0	0
gen_data_port_assertion.DataFlow_A	418699397	919755	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	919755	0	0
T1	10184	566	0	0
T2	2023	55	0	0
T3	63950	878	0	0
T7	338506	802	0	0
T8	277348	192	0	0
T9	25450	178	0	0
T10	69737	738	0	0
T11	401697	679	0	0
T12	7636	56	0	0
T13	626316	6692	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	919755	0	0
T1	10184	566	0	0
T2	2023	55	0	0
T3	63950	878	0	0
T7	338506	802	0	0
T8	277348	192	0	0
T9	25450	178	0	0
T10	69737	738	0	0
T11	401697	679	0	0
T12	7636	56	0	0
T13	626316	6692	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	919755	0	0
T1	10184	566	0	0
T2	2023	55	0	0
T3	63950	878	0	0
T7	338506	802	0	0
T8	277348	192	0	0
T9	25450	178	0	0
T10	69737	738	0	0
T11	401697	679	0	0
T12	7636	56	0	0
T13	626316	6692	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	350956469	0	0
T1	10184	1	0	0
T2	2023	1	0	0
T3	63950	49856	0	0
T7	338506	308219	0	0
T8	277348	231037	0	0
T9	25450	21816	0	0
T10	69737	57953	0	0
T11	401697	334529	0	0
T12	7636	6628	0	0
T13	626316	521367	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	919755	0	0
T1	10184	566	0	0
T2	2023	55	0	0
T3	63950	878	0	0
T7	338506	802	0	0
T8	277348	192	0	0
T9	25450	178	0	0
T10	69737	738	0	0
T11	401697	679	0	0
T12	7636	56	0	0
T13	626316	6692	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	919755	0	0
T1	10184	566	0	0
T2	2023	55	0	0
T3	63950	878	0	0
T7	338506	802	0	0
T8	277348	192	0	0
T9	25450	178	0	0
T10	69737	738	0	0
T11	401697	679	0	0
T12	7636	56	0	0
T13	626316	6692	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	13168471	0	0
T1	10184	566	0	0
T2	2023	55	0	0
T3	63950	6395	0	0
T7	338506	296821	0	0
T8	277348	809	0	0
T9	25450	1421	0	0
T10	69737	6178	0	0
T11	401697	3074	0	0
T12	7636	341	0	0
T13	626316	54496	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	27955	0	900
T1	10184	8	0	1
T2	2023	0	0	1
T3	63950	2	0	1
T4	0	4	0	0
T7	338506	0	0	1
T8	277348	0	0	1
T9	25450	0	0	1
T10	69737	2	0	1
T11	401697	0	0	1
T12	7636	0	0	1
T13	626316	10	0	1
T16	0	81	0	0
T17	0	13	0	0
T18	0	13	0	0
T19	0	3	0	0
T20	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	418572864	0	0
T1	10184	10129	0	0
T2	2023	1982	0	0
T3	63950	63920	0	0
T7	338506	338498	0	0
T8	277348	277341	0	0
T9	25450	25383	0	0
T10	69737	69704	0	0
T11	401697	401694	0	0
T12	7636	7594	0	0
T13	626316	626249	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418699397	919755	0	0
T1	10184	566	0	0
T2	2023	55	0	0
T3	63950	878	0	0
T7	338506	802	0	0
T8	277348	192	0	0
T9	25450	178	0	0
T10	69737	738	0	0
T11	401697	679	0	0
T12	7636	56	0	0
T13	626316	6692	0	0