Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1641467	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261841

1

T1

6

T2

18

T3

1103

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	644555	1			T1	21		T2	49		T3	2799
values[0x0]	612807	1			T1	2		T2	19		T3	2609
values[0x1]	645946	1			T1	14		T2	64		T3	2758

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1269732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

633576

1

T1

11

T2

55

T3

2714

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30335	1			T1	3		T2	1		T3	117
valid_sources[0x01]	29783	1			T2	4		T3	95		T9	46
valid_sources[0x02]	30722	1			T2	1		T3	163		T9	48
valid_sources[0x03]	31194	1			T2	1		T3	84		T9	30
valid_sources[0x04]	29455	1			T1	1		T2	2		T3	125
valid_sources[0x05]	29189	1			T2	4		T3	140		T9	37
valid_sources[0x06]	29207	1			T1	1		T2	2		T3	101
valid_sources[0x07]	30331	1			T3	70		T9	38		T8	16
valid_sources[0x08]	30651	1			T1	1		T2	4		T3	108
valid_sources[0x09]	29572	1			T1	1		T3	129		T9	33
valid_sources[0x0a]	30202	1			T2	1		T3	115		T9	29
valid_sources[0x0b]	30597	1			T1	1		T2	3		T3	103
valid_sources[0x0c]	28851	1			T1	1		T2	2		T3	102
valid_sources[0x0d]	30069	1			T1	1		T3	323		T9	27
valid_sources[0x0e]	30344	1			T1	1		T2	1		T3	129
valid_sources[0x0f]	30698	1			T2	3		T3	169		T9	41
valid_sources[0x10]	29338	1			T1	1		T2	3		T3	109
valid_sources[0x11]	29161	1			T2	2		T3	180		T9	31
valid_sources[0x12]	30156	1			T1	1		T2	1		T3	134
valid_sources[0x13]	29304	1			T1	1		T2	1		T3	116
valid_sources[0x14]	29196	1			T2	2		T3	111		T9	42
valid_sources[0x15]	29576	1			T1	1		T2	1		T3	208
valid_sources[0x16]	30323	1			T2	3		T3	95		T9	36
valid_sources[0x17]	28916	1			T2	1		T3	145		T9	38
valid_sources[0x18]	29095	1			T2	3		T3	120		T9	38
valid_sources[0x19]	30243	1			T1	1		T2	4		T3	178
valid_sources[0x1a]	30027	1			T2	1		T3	139		T9	52
valid_sources[0x1b]	30733	1			T2	2		T3	108		T9	36
valid_sources[0x1c]	30348	1			T2	2		T3	109		T9	41
valid_sources[0x1d]	29706	1			T2	2		T3	113		T9	34
valid_sources[0x1e]	29166	1			T2	1		T3	98		T9	55
valid_sources[0x1f]	29841	1			T1	1		T2	3		T3	138
valid_sources[0x20]	29735	1			T3	143		T9	33		T8	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27129

1

T1

2

T2

1

T3

107

values[0x0]

all_enables

biggest_size

207377

1

T1

2

T2

10

T3

887

values[0x1]

all_enables

biggest_size

27335

1

T1

2

T2

7

T3

109

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1654233	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

268825

1

T1

5

T2

11

T3

1283

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	658112	1			T1	16		T2	55		T3	3055
values[0x0]	608490	1			T1	3		T2	10		T3	2984
values[0x1]	656456	1			T1	16		T2	54		T3	2998

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1270883	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

652175

1

T1

18

T2

42

T3

3056

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30038	1			T2	1		T3	135		T9	46
valid_sources[0x01]	30174	1			T1	1		T3	125		T9	46
valid_sources[0x02]	31035	1			T2	2		T3	159		T9	46
valid_sources[0x03]	30210	1			T3	130		T9	44		T8	17
valid_sources[0x04]	29642	1			T2	1		T3	131		T9	51
valid_sources[0x05]	30548	1			T2	1		T3	129		T9	34
valid_sources[0x06]	29975	1			T1	1		T3	122		T9	54
valid_sources[0x07]	30193	1			T2	4		T3	146		T9	34
valid_sources[0x08]	30300	1			T2	5		T3	141		T9	41
valid_sources[0x09]	30169	1			T2	2		T3	146		T9	52
valid_sources[0x0a]	29890	1			T1	2		T2	2		T3	127
valid_sources[0x0b]	30047	1			T1	1		T2	10		T3	115
valid_sources[0x0c]	29584	1			T3	111		T9	40		T8	12
valid_sources[0x0d]	29815	1			T1	1		T2	1		T3	215
valid_sources[0x0e]	30362	1			T3	133		T9	39		T8	24
valid_sources[0x0f]	30021	1			T1	2		T3	135		T9	49
valid_sources[0x10]	29642	1			T2	1		T3	126		T9	45
valid_sources[0x11]	29513	1			T2	9		T3	159		T9	53
valid_sources[0x12]	29709	1			T3	134		T9	48		T8	14
valid_sources[0x13]	30019	1			T3	155		T9	39		T8	19
valid_sources[0x14]	30172	1			T2	4		T3	148		T9	47
valid_sources[0x15]	30565	1			T1	4		T3	229		T9	44
valid_sources[0x16]	30296	1			T2	2		T3	142		T9	37
valid_sources[0x17]	29886	1			T2	2		T3	161		T9	48
valid_sources[0x18]	30654	1			T1	1		T3	140		T9	47
valid_sources[0x19]	30123	1			T2	2		T3	151		T9	40
valid_sources[0x1a]	29577	1			T3	151		T9	49		T8	26
valid_sources[0x1b]	30252	1			T1	1		T3	118		T9	53
valid_sources[0x1c]	30117	1			T1	3		T2	1		T3	127
valid_sources[0x1d]	30863	1			T2	4		T3	169		T9	47
valid_sources[0x1e]	29172	1			T1	1		T2	6		T3	125
valid_sources[0x1f]	30427	1			T1	1		T2	2		T3	114
valid_sources[0x20]	30889	1			T1	1		T2	5		T3	109

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28178

1

T1

1

T2

1

T3

117

values[0x0]

all_enables

biggest_size

212857

1

T1

2

T2

3

T3

1034

values[0x1]

all_enables

biggest_size

27790

1

T1

2

T2

7

T3

132

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1655951	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264011

1

T1

5

T2

15

T3

1082

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	650235	1			T1	15		T2	62		T3	2633
values[0x0]	618288	1			T1	1		T2	6		T3	2560
values[0x1]	651439	1			T1	15		T2	58		T3	2716

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1280095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

639867

1

T1

13

T2

48

T3

2582

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29316	1			T2	3		T3	137		T9	50
valid_sources[0x01]	30187	1			T3	134		T9	47		T8	16
valid_sources[0x02]	29628	1			T1	1		T2	3		T3	86
valid_sources[0x03]	29633	1			T2	1		T3	137		T9	49
valid_sources[0x04]	29930	1			T1	1		T2	2		T3	36
valid_sources[0x05]	29004	1			T3	24		T9	57		T8	14
valid_sources[0x06]	29070	1			T2	3		T3	42		T9	51
valid_sources[0x07]	30259	1			T2	2		T3	184		T9	45
valid_sources[0x08]	30030	1			T2	4		T3	260		T9	37
valid_sources[0x09]	29513	1			T2	2		T3	158		T9	54
valid_sources[0x0a]	28832	1			T1	1		T3	109		T9	33
valid_sources[0x0b]	30103	1			T2	3		T3	179		T9	50
valid_sources[0x0c]	29216	1			T1	3		T2	1		T3	66
valid_sources[0x0d]	30339	1			T1	2		T2	2		T3	184
valid_sources[0x0e]	30263	1			T2	3		T3	350		T9	55
valid_sources[0x0f]	30447	1			T2	1		T3	227		T9	37
valid_sources[0x10]	30260	1			T1	1		T2	1		T3	26
valid_sources[0x11]	29446	1			T1	2		T2	1		T3	166
valid_sources[0x12]	29512	1			T3	116		T9	33		T8	24
valid_sources[0x13]	30189	1			T1	1		T2	1		T3	96
valid_sources[0x14]	30532	1			T2	2		T3	246		T9	46
valid_sources[0x15]	30491	1			T2	2		T3	306		T9	27
valid_sources[0x16]	30181	1			T2	3		T3	118		T9	43
valid_sources[0x17]	31089	1			T1	1		T2	2		T3	103
valid_sources[0x18]	29638	1			T2	7		T3	72		T9	38
valid_sources[0x19]	31053	1			T1	1		T3	132		T9	40
valid_sources[0x1a]	28915	1			T1	1		T3	77		T9	54
valid_sources[0x1b]	30747	1			T1	2		T2	1		T3	79
valid_sources[0x1c]	31056	1			T2	4		T3	29		T9	56
valid_sources[0x1d]	31226	1			T2	3		T3	375		T9	49
valid_sources[0x1e]	29766	1			T1	1		T2	1		T3	148
valid_sources[0x1f]	29345	1			T1	1		T3	87		T9	39
valid_sources[0x20]	30125	1			T2	3		T3	117		T9	47

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27657

1

T1

3

T2

6

T3

102

values[0x0]

all_enables

biggest_size

208608

1

T1

1

T2

5

T3

866

values[0x1]

all_enables

biggest_size

27746

1

T1

1

T2

4

T3

114