Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8065067	0	0
GntImpliesValid_A	2147483647	8065067	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8065067	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	485820585	0	0
ReadyAndValidImplyGrant_A	2147483647	8065067	0	0
ReqAndReadyImplyGrant_A	2147483647	8065067	0	0
ReqImpliesValid_A	2147483647	37192753	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50655	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8065067	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	402144	401520	0	0
T2	229248	229032	0	0
T3	926280	912744	0	0
T7	26952	23928	0	0
T8	16802904	16796016	0	0
T9	393168	391824	0	0
T10	57864	56256	0	0
T11	42936	42744	0	0
T12	99096	98664	0	0
T13	259104	258624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8065067	0	0
T1	402144	1190	0	0
T2	229248	4223	0	0
T3	926280	20348	0	0
T7	26952	59	0	0
T8	16802904	64763	0	0
T9	393168	8077	0	0
T10	57864	343	0	0
T11	42936	484	0	0
T12	99096	1778	0	0
T13	259104	6061	0	0
T14	0	432	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8065067	0	0
T1	402144	1190	0	0
T2	229248	4223	0	0
T3	926280	20348	0	0
T7	26952	59	0	0
T8	16802904	64763	0	0
T9	393168	8077	0	0
T10	57864	343	0	0
T11	42936	484	0	0
T12	99096	1778	0	0
T13	259104	6061	0	0
T14	0	432	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	402144	401520	0	0
T2	229248	229032	0	0
T3	926280	912744	0	0
T7	26952	23928	0	0
T8	16802904	16796016	0	0
T9	393168	391824	0	0
T10	57864	56256	0	0
T11	42936	42744	0	0
T12	99096	98664	0	0
T13	259104	258624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	402144	401520	0	0
T2	229248	229032	0	0
T3	926280	912744	0	0
T7	26952	23928	0	0
T8	16802904	16796016	0	0
T9	393168	391824	0	0
T10	57864	56256	0	0
T11	42936	42744	0	0
T12	99096	98664	0	0
T13	259104	258624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8065067	0	0
T1	402144	1190	0	0
T2	229248	4223	0	0
T3	926280	20348	0	0
T7	26952	59	0	0
T8	16802904	64763	0	0
T9	393168	8077	0	0
T10	57864	343	0	0
T11	42936	484	0	0
T12	99096	1778	0	0
T13	259104	6061	0	0
T14	0	432	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	485820585	0	0
T1	402144	22366	0	0
T2	229248	4528	0	0
T3	926280	21570	0	0
T7	26952	1244	0	0
T8	16802904	913876	0	0
T9	393168	12057	0	0
T10	57864	830	0	0
T11	42936	485	0	0
T12	99096	1888	0	0
T13	259104	7733	0	0
T14	0	693	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8065067	0	0
T1	402144	1190	0	0
T2	229248	4223	0	0
T3	926280	20348	0	0
T7	26952	59	0	0
T8	16802904	64763	0	0
T9	393168	8077	0	0
T10	57864	343	0	0
T11	42936	484	0	0
T12	99096	1778	0	0
T13	259104	6061	0	0
T14	0	432	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8065067	0	0
T1	402144	1190	0	0
T2	229248	4223	0	0
T3	926280	20348	0	0
T7	26952	59	0	0
T8	16802904	64763	0	0
T9	393168	8077	0	0
T10	57864	343	0	0
T11	42936	484	0	0
T12	99096	1778	0	0
T13	259104	6061	0	0
T14	0	432	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37192753	0	0
T1	402144	2384	0	0
T2	229248	4613	0	0
T3	926280	27630	0	0
T7	26952	165	0	0
T8	16802904	325393	0	0
T9	393168	9719	0	0
T10	57864	413	0	0
T11	42936	541	0	0
T12	99096	1938	0	0
T13	259104	7186	0	0
T14	0	529	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50655	0	21600
T2	19104	12	0	2
T3	77190	34	0	2
T7	2246	0	0	2
T8	1400242	72	0	2
T9	32764	32	0	2
T10	4822	0	0	2
T11	3578	0	0	2
T12	8258	5	0	2
T13	21592	22	0	2
T14	104460	0	0	2
T15	0	15	0	0
T16	0	19	0	0
T17	0	27	0	0
T18	0	28	0	0
T19	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	402144	401520	0	0
T2	229248	229032	0	0
T3	926280	912744	0	0
T7	26952	23928	0	0
T8	16802904	16796016	0	0
T9	393168	391824	0	0
T10	57864	56256	0	0
T11	42936	42744	0	0
T12	99096	98664	0	0
T13	259104	258624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8065067	0	0
T1	402144	1190	0	0
T2	229248	4223	0	0
T3	926280	20348	0	0
T7	26952	59	0	0
T8	16802904	64763	0	0
T9	393168	8077	0	0
T10	57864	343	0	0
T11	42936	484	0	0
T12	99096	1778	0	0
T13	259104	6061	0	0
T14	0	432	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	912804	0	0
GntImpliesValid_A	443855068	912804	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	912804	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	13241106	0	0
ReadyAndValidImplyGrant_A	443855068	912804	0	0
ReqAndReadyImplyGrant_A	443855068	912804	0	0
ReqImpliesValid_A	443855068	2697371	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	912804	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	912804	0	0
T1	16756	131	0	0
T2	9552	461	0	0
T3	38595	2845	0	0
T7	1123	12	0	0
T8	700121	6723	0	0
T9	16382	930	0	0
T10	2411	30	0	0
T11	1789	41	0	0
T12	4129	196	0	0
T13	10796	705	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	912804	0	0
T1	16756	131	0	0
T2	9552	461	0	0
T3	38595	2845	0	0
T7	1123	12	0	0
T8	700121	6723	0	0
T9	16382	930	0	0
T10	2411	30	0	0
T11	1789	41	0	0
T12	4129	196	0	0
T13	10796	705	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	912804	0	0
T1	16756	131	0	0
T2	9552	461	0	0
T3	38595	2845	0	0
T7	1123	12	0	0
T8	700121	6723	0	0
T9	16382	930	0	0
T10	2411	30	0	0
T11	1789	41	0	0
T12	4129	196	0	0
T13	10796	705	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	13241106	0	0
T1	16756	908	0	0
T2	9552	386	0	0
T3	38595	1720	0	0
T7	1123	68	0	0
T8	700121	42268	0	0
T9	16382	668	0	0
T10	2411	25	0	0
T11	1789	34	0	0
T12	4129	163	0	0
T13	10796	511	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	912804	0	0
T1	16756	131	0	0
T2	9552	461	0	0
T3	38595	2845	0	0
T7	1123	12	0	0
T8	700121	6723	0	0
T9	16382	930	0	0
T10	2411	30	0	0
T11	1789	41	0	0
T12	4129	196	0	0
T13	10796	705	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	912804	0	0
T1	16756	131	0	0
T2	9552	461	0	0
T3	38595	2845	0	0
T7	1123	12	0	0
T8	700121	6723	0	0
T9	16382	930	0	0
T10	2411	30	0	0
T11	1789	41	0	0
T12	4129	196	0	0
T13	10796	705	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	2697371	0	0
T1	16756	206	0	0
T2	9552	537	0	0
T3	38595	3978	0	0
T7	1123	29	0	0
T8	700121	21713	0	0
T9	16382	1193	0	0
T10	2411	36	0	0
T11	1789	49	0	0
T12	4129	230	0	0
T13	10796	900	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	912804	0	0
T1	16756	131	0	0
T2	9552	461	0	0
T3	38595	2845	0	0
T7	1123	12	0	0
T8	700121	6723	0	0
T9	16382	930	0	0
T10	2411	30	0	0
T11	1789	41	0	0
T12	4129	196	0	0
T13	10796	705	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	903059	0	0
GntImpliesValid_A	443855068	903059	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	903059	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	13095460	0	0
ReadyAndValidImplyGrant_A	443855068	903059	0	0
ReqAndReadyImplyGrant_A	443855068	903059	0	0
ReqImpliesValid_A	443855068	2672637	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	903059	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	903059	0	0
T1	16756	142	0	0
T2	9552	485	0	0
T3	38595	2193	0	0
T7	1123	6	0	0
T8	700121	7647	0	0
T9	16382	927	0	0
T10	2411	33	0	0
T11	1789	65	0	0
T12	4129	188	0	0
T13	10796	665	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	903059	0	0
T1	16756	142	0	0
T2	9552	485	0	0
T3	38595	2193	0	0
T7	1123	6	0	0
T8	700121	7647	0	0
T9	16382	927	0	0
T10	2411	33	0	0
T11	1789	65	0	0
T12	4129	188	0	0
T13	10796	665	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	903059	0	0
T1	16756	142	0	0
T2	9552	485	0	0
T3	38595	2193	0	0
T7	1123	6	0	0
T8	700121	7647	0	0
T9	16382	927	0	0
T10	2411	33	0	0
T11	1789	65	0	0
T12	4129	188	0	0
T13	10796	665	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	13095460	0	0
T1	16756	1146	0	0
T2	9552	397	0	0
T3	38595	1744	0	0
T7	1123	58	0	0
T8	700121	45889	0	0
T9	16382	674	0	0
T10	2411	28	0	0
T11	1789	52	0	0
T12	4129	154	0	0
T13	10796	518	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	903059	0	0
T1	16756	142	0	0
T2	9552	485	0	0
T3	38595	2193	0	0
T7	1123	6	0	0
T8	700121	7647	0	0
T9	16382	927	0	0
T10	2411	33	0	0
T11	1789	65	0	0
T12	4129	188	0	0
T13	10796	665	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	903059	0	0
T1	16756	142	0	0
T2	9552	485	0	0
T3	38595	2193	0	0
T7	1123	6	0	0
T8	700121	7647	0	0
T9	16382	927	0	0
T10	2411	33	0	0
T11	1789	65	0	0
T12	4129	188	0	0
T13	10796	665	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	2672637	0	0
T1	16756	211	0	0
T2	9552	574	0	0
T3	38595	2650	0	0
T7	1123	6	0	0
T8	700121	26823	0	0
T9	16382	1181	0	0
T10	2411	39	0	0
T11	1789	79	0	0
T12	4129	223	0	0
T13	10796	813	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	903059	0	0
T1	16756	142	0	0
T2	9552	485	0	0
T3	38595	2193	0	0
T7	1123	6	0	0
T8	700121	7647	0	0
T9	16382	927	0	0
T10	2411	33	0	0
T11	1789	65	0	0
T12	4129	188	0	0
T13	10796	665	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	236802	0	0
GntImpliesValid_A	443855068	236802	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	236802	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3208881	0	0
ReadyAndValidImplyGrant_A	443855068	236802	0	0
ReqAndReadyImplyGrant_A	443855068	236802	0	0
ReqImpliesValid_A	443855068	644249	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	236802	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	236802	0	0
T1	16756	43	0	0
T2	9552	113	0	0
T3	38595	765	0	0
T7	1123	1	0	0
T8	700121	2252	0	0
T9	16382	217	0	0
T10	2411	4	0	0
T11	1789	7	0	0
T12	4129	50	0	0
T13	10796	173	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	236802	0	0
T1	16756	43	0	0
T2	9552	113	0	0
T3	38595	765	0	0
T7	1123	1	0	0
T8	700121	2252	0	0
T9	16382	217	0	0
T10	2411	4	0	0
T11	1789	7	0	0
T12	4129	50	0	0
T13	10796	173	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	236802	0	0
T1	16756	43	0	0
T2	9552	113	0	0
T3	38595	765	0	0
T7	1123	1	0	0
T8	700121	2252	0	0
T9	16382	217	0	0
T10	2411	4	0	0
T11	1789	7	0	0
T12	4129	50	0	0
T13	10796	173	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3208881	0	0
T1	16756	278	0	0
T2	9552	109	0	0
T3	38595	679	0	0
T7	1123	4	0	0
T8	700121	9247	0	0
T9	16382	208	0	0
T10	2411	5	0	0
T11	1789	8	0	0
T12	4129	46	0	0
T13	10796	162	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	236802	0	0
T1	16756	43	0	0
T2	9552	113	0	0
T3	38595	765	0	0
T7	1123	1	0	0
T8	700121	2252	0	0
T9	16382	217	0	0
T10	2411	4	0	0
T11	1789	7	0	0
T12	4129	50	0	0
T13	10796	173	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	236802	0	0
T1	16756	43	0	0
T2	9552	113	0	0
T3	38595	765	0	0
T7	1123	1	0	0
T8	700121	2252	0	0
T9	16382	217	0	0
T10	2411	4	0	0
T11	1789	7	0	0
T12	4129	50	0	0
T13	10796	173	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	644249	0	0
T1	16756	50	0	0
T2	9552	118	0	0
T3	38595	859	0	0
T7	1123	1	0	0
T8	700121	14097	0	0
T9	16382	227	0	0
T10	2411	4	0	0
T11	1789	7	0	0
T12	4129	55	0	0
T13	10796	185	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	236802	0	0
T1	16756	43	0	0
T2	9552	113	0	0
T3	38595	765	0	0
T7	1123	1	0	0
T8	700121	2252	0	0
T9	16382	217	0	0
T10	2411	4	0	0
T11	1789	7	0	0
T12	4129	50	0	0
T13	10796	173	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	223691	0	0
GntImpliesValid_A	443855068	223691	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	223691	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3220559	0	0
ReadyAndValidImplyGrant_A	443855068	223691	0	0
ReqAndReadyImplyGrant_A	443855068	223691	0	0
ReqImpliesValid_A	443855068	599128	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	223691	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	223691	0	0
T1	16756	31	0	0
T2	9552	109	0	0
T3	38595	361	0	0
T7	1123	3	0	0
T8	700121	1214	0	0
T9	16382	237	0	0
T10	2411	10	0	0
T11	1789	16	0	0
T12	4129	51	0	0
T13	10796	172	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	223691	0	0
T1	16756	31	0	0
T2	9552	109	0	0
T3	38595	361	0	0
T7	1123	3	0	0
T8	700121	1214	0	0
T9	16382	237	0	0
T10	2411	10	0	0
T11	1789	16	0	0
T12	4129	51	0	0
T13	10796	172	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	223691	0	0
T1	16756	31	0	0
T2	9552	109	0	0
T3	38595	361	0	0
T7	1123	3	0	0
T8	700121	1214	0	0
T9	16382	237	0	0
T10	2411	10	0	0
T11	1789	16	0	0
T12	4129	51	0	0
T13	10796	172	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3220559	0	0
T1	16756	278	0	0
T2	9552	100	0	0
T3	38595	354	0	0
T7	1123	23	0	0
T8	700121	7827	0	0
T9	16382	228	0	0
T10	2411	11	0	0
T11	1789	14	0	0
T12	4129	48	0	0
T13	10796	159	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	223691	0	0
T1	16756	31	0	0
T2	9552	109	0	0
T3	38595	361	0	0
T7	1123	3	0	0
T8	700121	1214	0	0
T9	16382	237	0	0
T10	2411	10	0	0
T11	1789	16	0	0
T12	4129	51	0	0
T13	10796	172	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	223691	0	0
T1	16756	31	0	0
T2	9552	109	0	0
T3	38595	361	0	0
T7	1123	3	0	0
T8	700121	1214	0	0
T9	16382	237	0	0
T10	2411	10	0	0
T11	1789	16	0	0
T12	4129	51	0	0
T13	10796	172	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	599128	0	0
T1	16756	35	0	0
T2	9552	119	0	0
T3	38595	376	0	0
T7	1123	9	0	0
T8	700121	3589	0	0
T9	16382	247	0	0
T10	2411	10	0	0
T11	1789	19	0	0
T12	4129	55	0	0
T13	10796	186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	223691	0	0
T1	16756	31	0	0
T2	9552	109	0	0
T3	38595	361	0	0
T7	1123	3	0	0
T8	700121	1214	0	0
T9	16382	237	0	0
T10	2411	10	0	0
T11	1789	16	0	0
T12	4129	51	0	0
T13	10796	172	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	215685	0	0
GntImpliesValid_A	443855068	215685	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	215685	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	5648105	0	0
ReadyAndValidImplyGrant_A	443855068	215685	0	0
ReqAndReadyImplyGrant_A	443855068	215685	0	0
ReqImpliesValid_A	443855068	1254825	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	215685	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	215685	0	0
T1	16756	21	0	0
T2	9552	110	0	0
T3	38595	354	0	0
T7	1123	1	0	0
T8	700121	1612	0	0
T9	16382	205	0	0
T10	2411	15	0	0
T11	1789	9	0	0
T12	4129	49	0	0
T13	10796	157	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	215685	0	0
T1	16756	21	0	0
T2	9552	110	0	0
T3	38595	354	0	0
T7	1123	1	0	0
T8	700121	1612	0	0
T9	16382	205	0	0
T10	2411	15	0	0
T11	1789	9	0	0
T12	4129	49	0	0
T13	10796	157	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	215685	0	0
T1	16756	21	0	0
T2	9552	110	0	0
T3	38595	354	0	0
T7	1123	1	0	0
T8	700121	1612	0	0
T9	16382	205	0	0
T10	2411	15	0	0
T11	1789	9	0	0
T12	4129	49	0	0
T13	10796	157	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	5648105	0	0
T1	16756	274	0	0
T2	9552	551	0	0
T3	38595	1787	0	0
T7	1123	26	0	0
T8	700121	13674	0	0
T9	16382	1239	0	0
T10	2411	136	0	0
T11	1789	31	0	0
T12	4129	193	0	0
T13	10796	1885	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	215685	0	0
T1	16756	21	0	0
T2	9552	110	0	0
T3	38595	354	0	0
T7	1123	1	0	0
T8	700121	1612	0	0
T9	16382	205	0	0
T10	2411	15	0	0
T11	1789	9	0	0
T12	4129	49	0	0
T13	10796	157	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	215685	0	0
T1	16756	21	0	0
T2	9552	110	0	0
T3	38595	354	0	0
T7	1123	1	0	0
T8	700121	1612	0	0
T9	16382	205	0	0
T10	2411	15	0	0
T11	1789	9	0	0
T12	4129	49	0	0
T13	10796	157	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	1254825	0	0
T1	16756	74	0	0
T2	9552	140	0	0
T3	38595	495	0	0
T7	1123	1	0	0
T8	700121	17922	0	0
T9	16382	324	0	0
T10	2411	33	0	0
T11	1789	9	0	0
T12	4129	76	0	0
T13	10796	368	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	215685	0	0
T1	16756	21	0	0
T2	9552	110	0	0
T3	38595	354	0	0
T7	1123	1	0	0
T8	700121	1612	0	0
T9	16382	205	0	0
T10	2411	15	0	0
T11	1789	9	0	0
T12	4129	49	0	0
T13	10796	157	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	225279	0	0
GntImpliesValid_A	443855068	225279	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	225279	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	5415303	0	0
ReadyAndValidImplyGrant_A	443855068	225279	0	0
ReqAndReadyImplyGrant_A	443855068	225279	0	0
ReqImpliesValid_A	443855068	1422535	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	225279	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	225279	0	0
T1	16756	41	0	0
T2	9552	92	0	0
T3	38595	531	0	0
T7	1123	0	0	0
T8	700121	2260	0	0
T9	16382	190	0	0
T10	2411	11	0	0
T11	1789	13	0	0
T12	4129	50	0	0
T13	10796	154	0	0
T14	0	86	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	225279	0	0
T1	16756	41	0	0
T2	9552	92	0	0
T3	38595	531	0	0
T7	1123	0	0	0
T8	700121	2260	0	0
T9	16382	190	0	0
T10	2411	11	0	0
T11	1789	13	0	0
T12	4129	50	0	0
T13	10796	154	0	0
T14	0	86	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	225279	0	0
T1	16756	41	0	0
T2	9552	92	0	0
T3	38595	531	0	0
T7	1123	0	0	0
T8	700121	2260	0	0
T9	16382	190	0	0
T10	2411	11	0	0
T11	1789	13	0	0
T12	4129	50	0	0
T13	10796	154	0	0
T14	0	86	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	5415303	0	0
T1	16756	343	0	0
T2	9552	307	0	0
T3	38595	3407	0	0
T7	1123	0	0	0
T8	700121	17532	0	0
T9	16382	1472	0	0
T10	2411	233	0	0
T11	1789	46	0	0
T12	4129	171	0	0
T13	10796	596	0	0
T14	0	693	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	225279	0	0
T1	16756	41	0	0
T2	9552	92	0	0
T3	38595	531	0	0
T7	1123	0	0	0
T8	700121	2260	0	0
T9	16382	190	0	0
T10	2411	11	0	0
T11	1789	13	0	0
T12	4129	50	0	0
T13	10796	154	0	0
T14	0	86	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	225279	0	0
T1	16756	41	0	0
T2	9552	92	0	0
T3	38595	531	0	0
T7	1123	0	0	0
T8	700121	2260	0	0
T9	16382	190	0	0
T10	2411	11	0	0
T11	1789	13	0	0
T12	4129	50	0	0
T13	10796	154	0	0
T14	0	86	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	1422535	0	0
T1	16756	54	0	0
T2	9552	106	0	0
T3	38595	2357	0	0
T7	1123	0	0	0
T8	700121	17942	0	0
T9	16382	335	0	0
T10	2411	11	0	0
T11	1789	33	0	0
T12	4129	60	0	0
T13	10796	226	0	0
T14	0	115	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	225279	0	0
T1	16756	41	0	0
T2	9552	92	0	0
T3	38595	531	0	0
T7	1123	0	0	0
T8	700121	2260	0	0
T9	16382	190	0	0
T10	2411	11	0	0
T11	1789	13	0	0
T12	4129	50	0	0
T13	10796	154	0	0
T14	0	86	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	224278	0	0
GntImpliesValid_A	443855068	224278	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	224278	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	5741301	0	0
ReadyAndValidImplyGrant_A	443855068	224278	0	0
ReqAndReadyImplyGrant_A	443855068	224278	0	0
ReqImpliesValid_A	443855068	1289805	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	224278	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	224278	0	0
T1	16756	20	0	0
T2	9552	106	0	0
T3	38595	1039	0	0
T7	1123	2	0	0
T8	700121	1653	0	0
T9	16382	242	0	0
T10	2411	7	0	0
T11	1789	9	0	0
T12	4129	45	0	0
T13	10796	163	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	224278	0	0
T1	16756	20	0	0
T2	9552	106	0	0
T3	38595	1039	0	0
T7	1123	2	0	0
T8	700121	1653	0	0
T9	16382	242	0	0
T10	2411	7	0	0
T11	1789	9	0	0
T12	4129	45	0	0
T13	10796	163	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	224278	0	0
T1	16756	20	0	0
T2	9552	106	0	0
T3	38595	1039	0	0
T7	1123	2	0	0
T8	700121	1653	0	0
T9	16382	242	0	0
T10	2411	7	0	0
T11	1789	9	0	0
T12	4129	45	0	0
T13	10796	163	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	5741301	0	0
T1	16756	245	0	0
T2	9552	353	0	0
T3	38595	4419	0	0
T7	1123	10	0	0
T8	700121	17064	0	0
T9	16382	1389	0	0
T10	2411	41	0	0
T11	1789	31	0	0
T12	4129	258	0	0
T13	10796	638	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	224278	0	0
T1	16756	20	0	0
T2	9552	106	0	0
T3	38595	1039	0	0
T7	1123	2	0	0
T8	700121	1653	0	0
T9	16382	242	0	0
T10	2411	7	0	0
T11	1789	9	0	0
T12	4129	45	0	0
T13	10796	163	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	224278	0	0
T1	16756	20	0	0
T2	9552	106	0	0
T3	38595	1039	0	0
T7	1123	2	0	0
T8	700121	1653	0	0
T9	16382	242	0	0
T10	2411	7	0	0
T11	1789	9	0	0
T12	4129	45	0	0
T13	10796	163	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	1289805	0	0
T1	16756	20	0	0
T2	9552	124	0	0
T3	38595	2443	0	0
T7	1123	2	0	0
T8	700121	7021	0	0
T9	16382	472	0	0
T10	2411	7	0	0
T11	1789	9	0	0
T12	4129	55	0	0
T13	10796	255	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	224278	0	0
T1	16756	20	0	0
T2	9552	106	0	0
T3	38595	1039	0	0
T7	1123	2	0	0
T8	700121	1653	0	0
T9	16382	242	0	0
T10	2411	7	0	0
T11	1789	9	0	0
T12	4129	45	0	0
T13	10796	163	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	218180	0	0
GntImpliesValid_A	443855068	218180	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	218180	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	5525816	0	0
ReadyAndValidImplyGrant_A	443855068	218180	0	0
ReqAndReadyImplyGrant_A	443855068	218180	0	0
ReqImpliesValid_A	443855068	1290845	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	218180	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	218180	0	0
T1	16756	32	0	0
T2	9552	124	0	0
T3	38595	360	0	0
T7	1123	2	0	0
T8	700121	2910	0	0
T9	16382	194	0	0
T10	2411	18	0	0
T11	1789	19	0	0
T12	4129	43	0	0
T13	10796	162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	218180	0	0
T1	16756	32	0	0
T2	9552	124	0	0
T3	38595	360	0	0
T7	1123	2	0	0
T8	700121	2910	0	0
T9	16382	194	0	0
T10	2411	18	0	0
T11	1789	19	0	0
T12	4129	43	0	0
T13	10796	162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	218180	0	0
T1	16756	32	0	0
T2	9552	124	0	0
T3	38595	360	0	0
T7	1123	2	0	0
T8	700121	2910	0	0
T9	16382	194	0	0
T10	2411	18	0	0
T11	1789	19	0	0
T12	4129	43	0	0
T13	10796	162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	5525816	0	0
T1	16756	603	0	0
T2	9552	653	0	0
T3	38595	1716	0	0
T7	1123	30	0	0
T8	700121	19332	0	0
T9	16382	3233	0	0
T10	2411	200	0	0
T11	1789	81	0	0
T12	4129	161	0	0
T13	10796	1036	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	218180	0	0
T1	16756	32	0	0
T2	9552	124	0	0
T3	38595	360	0	0
T7	1123	2	0	0
T8	700121	2910	0	0
T9	16382	194	0	0
T10	2411	18	0	0
T11	1789	19	0	0
T12	4129	43	0	0
T13	10796	162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	218180	0	0
T1	16756	32	0	0
T2	9552	124	0	0
T3	38595	360	0	0
T7	1123	2	0	0
T8	700121	2910	0	0
T9	16382	194	0	0
T10	2411	18	0	0
T11	1789	19	0	0
T12	4129	43	0	0
T13	10796	162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	1290845	0	0
T1	16756	40	0	0
T2	9552	191	0	0
T3	38595	464	0	0
T7	1123	11	0	0
T8	700121	35594	0	0
T9	16382	638	0	0
T10	2411	54	0	0
T11	1789	22	0	0
T12	4129	45	0	0
T13	10796	407	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	218180	0	0
T1	16756	32	0	0
T2	9552	124	0	0
T3	38595	360	0	0
T7	1123	2	0	0
T8	700121	2910	0	0
T9	16382	194	0	0
T10	2411	18	0	0
T11	1789	19	0	0
T12	4129	43	0	0
T13	10796	162	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	226084	0	0
GntImpliesValid_A	443855068	226084	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	226084	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3188246	0	0
ReadyAndValidImplyGrant_A	443855068	226084	0	0
ReqAndReadyImplyGrant_A	443855068	226084	0	0
ReqImpliesValid_A	443855068	648293	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	226084	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226084	0	0
T1	16756	39	0	0
T2	9552	112	0	0
T3	38595	345	0	0
T7	1123	1	0	0
T8	700121	3099	0	0
T9	16382	225	0	0
T10	2411	8	0	0
T11	1789	18	0	0
T12	4129	47	0	0
T13	10796	154	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226084	0	0
T1	16756	39	0	0
T2	9552	112	0	0
T3	38595	345	0	0
T7	1123	1	0	0
T8	700121	3099	0	0
T9	16382	225	0	0
T10	2411	8	0	0
T11	1789	18	0	0
T12	4129	47	0	0
T13	10796	154	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226084	0	0
T1	16756	39	0	0
T2	9552	112	0	0
T3	38595	345	0	0
T7	1123	1	0	0
T8	700121	3099	0	0
T9	16382	225	0	0
T10	2411	8	0	0
T11	1789	18	0	0
T12	4129	47	0	0
T13	10796	154	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3188246	0	0
T1	16756	288	0	0
T2	9552	106	0	0
T3	38595	341	0	0
T7	1123	17	0	0
T8	700121	14701	0	0
T9	16382	215	0	0
T10	2411	8	0	0
T11	1789	17	0	0
T12	4129	47	0	0
T13	10796	146	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226084	0	0
T1	16756	39	0	0
T2	9552	112	0	0
T3	38595	345	0	0
T7	1123	1	0	0
T8	700121	3099	0	0
T9	16382	225	0	0
T10	2411	8	0	0
T11	1789	18	0	0
T12	4129	47	0	0
T13	10796	154	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226084	0	0
T1	16756	39	0	0
T2	9552	112	0	0
T3	38595	345	0	0
T7	1123	1	0	0
T8	700121	3099	0	0
T9	16382	225	0	0
T10	2411	8	0	0
T11	1789	18	0	0
T12	4129	47	0	0
T13	10796	154	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	648293	0	0
T1	16756	57	0	0
T2	9552	119	0	0
T3	38595	357	0	0
T7	1123	1	0	0
T8	700121	8387	0	0
T9	16382	236	0	0
T10	2411	9	0	0
T11	1789	20	0	0
T12	4129	48	0	0
T13	10796	163	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226084	0	0
T1	16756	39	0	0
T2	9552	112	0	0
T3	38595	345	0	0
T7	1123	1	0	0
T8	700121	3099	0	0
T9	16382	225	0	0
T10	2411	8	0	0
T11	1789	18	0	0
T12	4129	47	0	0
T13	10796	154	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	212465	0	0
GntImpliesValid_A	443855068	212465	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	212465	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3220667	0	0
ReadyAndValidImplyGrant_A	443855068	212465	0	0
ReqAndReadyImplyGrant_A	443855068	212465	0	0
ReqImpliesValid_A	443855068	589822	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	212465	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	212465	0	0
T1	16756	27	0	0
T2	9552	124	0	0
T3	38595	369	0	0
T7	1123	3	0	0
T8	700121	2150	0	0
T9	16382	273	0	0
T10	2411	13	0	0
T11	1789	8	0	0
T12	4129	46	0	0
T13	10796	139	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	212465	0	0
T1	16756	27	0	0
T2	9552	124	0	0
T3	38595	369	0	0
T7	1123	3	0	0
T8	700121	2150	0	0
T9	16382	273	0	0
T10	2411	13	0	0
T11	1789	8	0	0
T12	4129	46	0	0
T13	10796	139	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	212465	0	0
T1	16756	27	0	0
T2	9552	124	0	0
T3	38595	369	0	0
T7	1123	3	0	0
T8	700121	2150	0	0
T9	16382	273	0	0
T10	2411	13	0	0
T11	1789	8	0	0
T12	4129	46	0	0
T13	10796	139	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3220667	0	0
T1	16756	164	0	0
T2	9552	116	0	0
T3	38595	365	0	0
T7	1123	32	0	0
T8	700121	11709	0	0
T9	16382	263	0	0
T10	2411	14	0	0
T11	1789	9	0	0
T12	4129	44	0	0
T13	10796	133	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	212465	0	0
T1	16756	27	0	0
T2	9552	124	0	0
T3	38595	369	0	0
T7	1123	3	0	0
T8	700121	2150	0	0
T9	16382	273	0	0
T10	2411	13	0	0
T11	1789	8	0	0
T12	4129	46	0	0
T13	10796	139	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	212465	0	0
T1	16756	27	0	0
T2	9552	124	0	0
T3	38595	369	0	0
T7	1123	3	0	0
T8	700121	2150	0	0
T9	16382	273	0	0
T10	2411	13	0	0
T11	1789	8	0	0
T12	4129	46	0	0
T13	10796	139	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	589822	0	0
T1	16756	29	0	0
T2	9552	133	0	0
T3	38595	381	0	0
T7	1123	3	0	0
T8	700121	9673	0	0
T9	16382	284	0	0
T10	2411	13	0	0
T11	1789	8	0	0
T12	4129	49	0	0
T13	10796	146	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	212465	0	0
T1	16756	27	0	0
T2	9552	124	0	0
T3	38595	369	0	0
T7	1123	3	0	0
T8	700121	2150	0	0
T9	16382	273	0	0
T10	2411	13	0	0
T11	1789	8	0	0
T12	4129	46	0	0
T13	10796	139	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	228572	0	0
GntImpliesValid_A	443855068	228572	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	228572	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3240097	0	0
ReadyAndValidImplyGrant_A	443855068	228572	0	0
ReqAndReadyImplyGrant_A	443855068	228572	0	0
ReqImpliesValid_A	443855068	606538	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	228572	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	228572	0	0
T1	16756	30	0	0
T2	9552	105	0	0
T3	38595	338	0	0
T7	1123	1	0	0
T8	700121	2220	0	0
T9	16382	200	0	0
T10	2411	10	0	0
T11	1789	10	0	0
T12	4129	45	0	0
T13	10796	162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	228572	0	0
T1	16756	30	0	0
T2	9552	105	0	0
T3	38595	338	0	0
T7	1123	1	0	0
T8	700121	2220	0	0
T9	16382	200	0	0
T10	2411	10	0	0
T11	1789	10	0	0
T12	4129	45	0	0
T13	10796	162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	228572	0	0
T1	16756	30	0	0
T2	9552	105	0	0
T3	38595	338	0	0
T7	1123	1	0	0
T8	700121	2220	0	0
T9	16382	200	0	0
T10	2411	10	0	0
T11	1789	10	0	0
T12	4129	45	0	0
T13	10796	162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3240097	0	0
T1	16756	236	0	0
T2	9552	103	0	0
T3	38595	331	0	0
T7	1123	11	0	0
T8	700121	6796	0	0
T9	16382	195	0	0
T10	2411	11	0	0
T11	1789	10	0	0
T12	4129	43	0	0
T13	10796	154	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	228572	0	0
T1	16756	30	0	0
T2	9552	105	0	0
T3	38595	338	0	0
T7	1123	1	0	0
T8	700121	2220	0	0
T9	16382	200	0	0
T10	2411	10	0	0
T11	1789	10	0	0
T12	4129	45	0	0
T13	10796	162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	228572	0	0
T1	16756	30	0	0
T2	9552	105	0	0
T3	38595	338	0	0
T7	1123	1	0	0
T8	700121	2220	0	0
T9	16382	200	0	0
T10	2411	10	0	0
T11	1789	10	0	0
T12	4129	45	0	0
T13	10796	162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	606538	0	0
T1	16756	34	0	0
T2	9552	108	0	0
T3	38595	353	0	0
T7	1123	1	0	0
T8	700121	16497	0	0
T9	16382	206	0	0
T10	2411	10	0	0
T11	1789	11	0	0
T12	4129	48	0	0
T13	10796	171	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	228572	0	0
T1	16756	30	0	0
T2	9552	105	0	0
T3	38595	338	0	0
T7	1123	1	0	0
T8	700121	2220	0	0
T9	16382	200	0	0
T10	2411	10	0	0
T11	1789	10	0	0
T12	4129	45	0	0
T13	10796	162	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	227109	0	0
GntImpliesValid_A	443855068	227109	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	227109	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3242615	0	0
ReadyAndValidImplyGrant_A	443855068	227109	0	0
ReqAndReadyImplyGrant_A	443855068	227109	0	0
ReqImpliesValid_A	443855068	659575	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	227109	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227109	0	0
T1	16756	38	0	0
T2	9552	117	0	0
T3	38595	325	0	0
T7	1123	2	0	0
T8	700121	1659	0	0
T9	16382	223	0	0
T10	2411	6	0	0
T11	1789	11	0	0
T12	4129	66	0	0
T13	10796	184	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227109	0	0
T1	16756	38	0	0
T2	9552	117	0	0
T3	38595	325	0	0
T7	1123	2	0	0
T8	700121	1659	0	0
T9	16382	223	0	0
T10	2411	6	0	0
T11	1789	11	0	0
T12	4129	66	0	0
T13	10796	184	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227109	0	0
T1	16756	38	0	0
T2	9552	117	0	0
T3	38595	325	0	0
T7	1123	2	0	0
T8	700121	1659	0	0
T9	16382	223	0	0
T10	2411	6	0	0
T11	1789	11	0	0
T12	4129	66	0	0
T13	10796	184	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3242615	0	0
T1	16756	287	0	0
T2	9552	113	0	0
T3	38595	328	0	0
T7	1123	22	0	0
T8	700121	8545	0	0
T9	16382	206	0	0
T10	2411	7	0	0
T11	1789	10	0	0
T12	4129	64	0	0
T13	10796	171	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227109	0	0
T1	16756	38	0	0
T2	9552	117	0	0
T3	38595	325	0	0
T7	1123	2	0	0
T8	700121	1659	0	0
T9	16382	223	0	0
T10	2411	6	0	0
T11	1789	11	0	0
T12	4129	66	0	0
T13	10796	184	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227109	0	0
T1	16756	38	0	0
T2	9552	117	0	0
T3	38595	325	0	0
T7	1123	2	0	0
T8	700121	1659	0	0
T9	16382	223	0	0
T10	2411	6	0	0
T11	1789	11	0	0
T12	4129	66	0	0
T13	10796	184	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	659575	0	0
T1	16756	41	0	0
T2	9552	122	0	0
T3	38595	330	0	0
T7	1123	2	0	0
T8	700121	3981	0	0
T9	16382	241	0	0
T10	2411	6	0	0
T11	1789	13	0	0
T12	4129	69	0	0
T13	10796	198	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227109	0	0
T1	16756	38	0	0
T2	9552	117	0	0
T3	38595	325	0	0
T7	1123	2	0	0
T8	700121	1659	0	0
T9	16382	223	0	0
T10	2411	6	0	0
T11	1789	11	0	0
T12	4129	66	0	0
T13	10796	184	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	213481	0	0
GntImpliesValid_A	443855068	213481	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	213481	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3218247	0	0
ReadyAndValidImplyGrant_A	443855068	213481	0	0
ReqAndReadyImplyGrant_A	443855068	213481	0	0
ReqImpliesValid_A	443855068	549909	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	213481	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	213481	0	0
T1	16756	28	0	0
T2	9552	104	0	0
T3	38595	776	0	0
T7	1123	1	0	0
T8	700121	1183	0	0
T9	16382	217	0	0
T10	2411	13	0	0
T11	1789	13	0	0
T12	4129	51	0	0
T13	10796	163	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	213481	0	0
T1	16756	28	0	0
T2	9552	104	0	0
T3	38595	776	0	0
T7	1123	1	0	0
T8	700121	1183	0	0
T9	16382	217	0	0
T10	2411	13	0	0
T11	1789	13	0	0
T12	4129	51	0	0
T13	10796	163	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	213481	0	0
T1	16756	28	0	0
T2	9552	104	0	0
T3	38595	776	0	0
T7	1123	1	0	0
T8	700121	1183	0	0
T9	16382	217	0	0
T10	2411	13	0	0
T11	1789	13	0	0
T12	4129	51	0	0
T13	10796	163	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3218247	0	0
T1	16756	208	0	0
T2	9552	102	0	0
T3	38595	346	0	0
T7	1123	10	0	0
T8	700121	5910	0	0
T9	16382	207	0	0
T10	2411	14	0	0
T11	1789	13	0	0
T12	4129	49	0	0
T13	10796	158	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	213481	0	0
T1	16756	28	0	0
T2	9552	104	0	0
T3	38595	776	0	0
T7	1123	1	0	0
T8	700121	1183	0	0
T9	16382	217	0	0
T10	2411	13	0	0
T11	1789	13	0	0
T12	4129	51	0	0
T13	10796	163	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	213481	0	0
T1	16756	28	0	0
T2	9552	104	0	0
T3	38595	776	0	0
T7	1123	1	0	0
T8	700121	1183	0	0
T9	16382	217	0	0
T10	2411	13	0	0
T11	1789	13	0	0
T12	4129	51	0	0
T13	10796	163	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	549909	0	0
T1	16756	28	0	0
T2	9552	107	0	0
T3	38595	1214	0	0
T7	1123	1	0	0
T8	700121	5796	0	0
T9	16382	228	0	0
T10	2411	13	0	0
T11	1789	14	0	0
T12	4129	54	0	0
T13	10796	169	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	213481	0	0
T1	16756	28	0	0
T2	9552	104	0	0
T3	38595	776	0	0
T7	1123	1	0	0
T8	700121	1183	0	0
T9	16382	217	0	0
T10	2411	13	0	0
T11	1789	13	0	0
T12	4129	51	0	0
T13	10796	163	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	209424	0	0
GntImpliesValid_A	443855068	209424	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	209424	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3227063	0	0
ReadyAndValidImplyGrant_A	443855068	209424	0	0
ReqAndReadyImplyGrant_A	443855068	209424	0	0
ReqImpliesValid_A	443855068	574217	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	209424	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	209424	0	0
T1	16756	28	0	0
T2	9552	133	0	0
T3	38595	376	0	0
T7	1123	2	0	0
T8	700121	1120	0	0
T9	16382	209	0	0
T10	2411	14	0	0
T11	1789	14	0	0
T12	4129	40	0	0
T13	10796	177	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	209424	0	0
T1	16756	28	0	0
T2	9552	133	0	0
T3	38595	376	0	0
T7	1123	2	0	0
T8	700121	1120	0	0
T9	16382	209	0	0
T10	2411	14	0	0
T11	1789	14	0	0
T12	4129	40	0	0
T13	10796	177	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	209424	0	0
T1	16756	28	0	0
T2	9552	133	0	0
T3	38595	376	0	0
T7	1123	2	0	0
T8	700121	1120	0	0
T9	16382	209	0	0
T10	2411	14	0	0
T11	1789	14	0	0
T12	4129	40	0	0
T13	10796	177	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3227063	0	0
T1	16756	183	0	0
T2	9552	125	0	0
T3	38595	373	0	0
T7	1123	12	0	0
T8	700121	5991	0	0
T9	16382	196	0	0
T10	2411	15	0	0
T11	1789	15	0	0
T12	4129	39	0	0
T13	10796	155	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	209424	0	0
T1	16756	28	0	0
T2	9552	133	0	0
T3	38595	376	0	0
T7	1123	2	0	0
T8	700121	1120	0	0
T9	16382	209	0	0
T10	2411	14	0	0
T11	1789	14	0	0
T12	4129	40	0	0
T13	10796	177	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	209424	0	0
T1	16756	28	0	0
T2	9552	133	0	0
T3	38595	376	0	0
T7	1123	2	0	0
T8	700121	1120	0	0
T9	16382	209	0	0
T10	2411	14	0	0
T11	1789	14	0	0
T12	4129	40	0	0
T13	10796	177	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	574217	0	0
T1	16756	42	0	0
T2	9552	142	0	0
T3	38595	387	0	0
T7	1123	2	0	0
T8	700121	2569	0	0
T9	16382	223	0	0
T10	2411	14	0	0
T11	1789	14	0	0
T12	4129	42	0	0
T13	10796	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	209424	0	0
T1	16756	28	0	0
T2	9552	133	0	0
T3	38595	376	0	0
T7	1123	2	0	0
T8	700121	1120	0	0
T9	16382	209	0	0
T10	2411	14	0	0
T11	1789	14	0	0
T12	4129	40	0	0
T13	10796	177	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	221748	0	0
GntImpliesValid_A	443855068	221748	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	221748	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3289983	0	0
ReadyAndValidImplyGrant_A	443855068	221748	0	0
ReqAndReadyImplyGrant_A	443855068	221748	0	0
ReqImpliesValid_A	443855068	618214	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	221748	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	221748	0	0
T1	16756	21	0	0
T2	9552	124	0	0
T3	38595	841	0	0
T7	1123	1	0	0
T8	700121	1139	0	0
T9	16382	213	0	0
T10	2411	12	0	0
T11	1789	18	0	0
T12	4129	51	0	0
T13	10796	170	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	221748	0	0
T1	16756	21	0	0
T2	9552	124	0	0
T3	38595	841	0	0
T7	1123	1	0	0
T8	700121	1139	0	0
T9	16382	213	0	0
T10	2411	12	0	0
T11	1789	18	0	0
T12	4129	51	0	0
T13	10796	170	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	221748	0	0
T1	16756	21	0	0
T2	9552	124	0	0
T3	38595	841	0	0
T7	1123	1	0	0
T8	700121	1139	0	0
T9	16382	213	0	0
T10	2411	12	0	0
T11	1789	18	0	0
T12	4129	51	0	0
T13	10796	170	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3289983	0	0
T1	16756	188	0	0
T2	9552	121	0	0
T3	38595	629	0	0
T7	1123	18	0	0
T8	700121	6907	0	0
T9	16382	202	0	0
T10	2411	13	0	0
T11	1789	19	0	0
T12	4129	49	0	0
T13	10796	158	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	221748	0	0
T1	16756	21	0	0
T2	9552	124	0	0
T3	38595	841	0	0
T7	1123	1	0	0
T8	700121	1139	0	0
T9	16382	213	0	0
T10	2411	12	0	0
T11	1789	18	0	0
T12	4129	51	0	0
T13	10796	170	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	221748	0	0
T1	16756	21	0	0
T2	9552	124	0	0
T3	38595	841	0	0
T7	1123	1	0	0
T8	700121	1139	0	0
T9	16382	213	0	0
T10	2411	12	0	0
T11	1789	18	0	0
T12	4129	51	0	0
T13	10796	170	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	618214	0	0
T1	16756	31	0	0
T2	9552	128	0	0
T3	38595	1061	0	0
T7	1123	1	0	0
T8	700121	2264	0	0
T9	16382	225	0	0
T10	2411	12	0	0
T11	1789	18	0	0
T12	4129	54	0	0
T13	10796	183	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	221748	0	0
T1	16756	21	0	0
T2	9552	124	0	0
T3	38595	841	0	0
T7	1123	1	0	0
T8	700121	1139	0	0
T9	16382	213	0	0
T10	2411	12	0	0
T11	1789	18	0	0
T12	4129	51	0	0
T13	10796	170	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	204535	0	0
GntImpliesValid_A	443855068	204535	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	204535	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3155556	0	0
ReadyAndValidImplyGrant_A	443855068	204535	0	0
ReqAndReadyImplyGrant_A	443855068	204535	0	0
ReqImpliesValid_A	443855068	525795	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	204535	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	204535	0	0
T1	16756	34	0	0
T2	9552	117	0	0
T3	38595	345	0	0
T7	1123	0	0	0
T8	700121	2082	0	0
T9	16382	226	0	0
T10	2411	16	0	0
T11	1789	11	0	0
T12	4129	36	0	0
T13	10796	158	0	0
T14	0	88	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	204535	0	0
T1	16756	34	0	0
T2	9552	117	0	0
T3	38595	345	0	0
T7	1123	0	0	0
T8	700121	2082	0	0
T9	16382	226	0	0
T10	2411	16	0	0
T11	1789	11	0	0
T12	4129	36	0	0
T13	10796	158	0	0
T14	0	88	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	204535	0	0
T1	16756	34	0	0
T2	9552	117	0	0
T3	38595	345	0	0
T7	1123	0	0	0
T8	700121	2082	0	0
T9	16382	226	0	0
T10	2411	16	0	0
T11	1789	11	0	0
T12	4129	36	0	0
T13	10796	158	0	0
T14	0	88	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3155556	0	0
T1	16756	220	0	0
T2	9552	109	0	0
T3	38595	341	0	0
T7	1123	2	0	0
T8	700121	6423	0	0
T9	16382	220	0	0
T10	2411	16	0	0
T11	1789	11	0	0
T12	4129	35	0	0
T13	10796	155	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	204535	0	0
T1	16756	34	0	0
T2	9552	117	0	0
T3	38595	345	0	0
T7	1123	0	0	0
T8	700121	2082	0	0
T9	16382	226	0	0
T10	2411	16	0	0
T11	1789	11	0	0
T12	4129	36	0	0
T13	10796	158	0	0
T14	0	88	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	204535	0	0
T1	16756	34	0	0
T2	9552	117	0	0
T3	38595	345	0	0
T7	1123	0	0	0
T8	700121	2082	0	0
T9	16382	226	0	0
T10	2411	16	0	0
T11	1789	11	0	0
T12	4129	36	0	0
T13	10796	158	0	0
T14	0	88	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	525795	0	0
T1	16756	46	0	0
T2	9552	126	0	0
T3	38595	357	0	0
T7	1123	0	0	0
T8	700121	15654	0	0
T9	16382	233	0	0
T10	2411	17	0	0
T11	1789	12	0	0
T12	4129	38	0	0
T13	10796	162	0	0
T14	0	97	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	204535	0	0
T1	16756	34	0	0
T2	9552	117	0	0
T3	38595	345	0	0
T7	1123	0	0	0
T8	700121	2082	0	0
T9	16382	226	0	0
T10	2411	16	0	0
T11	1789	11	0	0
T12	4129	36	0	0
T13	10796	158	0	0
T14	0	88	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	247132	0	0
GntImpliesValid_A	443855068	247132	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	247132	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3325256	0	0
ReadyAndValidImplyGrant_A	443855068	247132	0	0
ReqAndReadyImplyGrant_A	443855068	247132	0	0
ReqImpliesValid_A	443855068	698911	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	247132	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	247132	0	0
T1	16756	55	0	0
T2	9552	184	0	0
T3	38595	421	0	0
T7	1123	1	0	0
T8	700121	2335	0	0
T9	16382	231	0	0
T10	2411	9	0	0
T11	1789	12	0	0
T12	4129	87	0	0
T13	10796	188	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	247132	0	0
T1	16756	55	0	0
T2	9552	184	0	0
T3	38595	421	0	0
T7	1123	1	0	0
T8	700121	2335	0	0
T9	16382	231	0	0
T10	2411	9	0	0
T11	1789	12	0	0
T12	4129	87	0	0
T13	10796	188	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	247132	0	0
T1	16756	55	0	0
T2	9552	184	0	0
T3	38595	421	0	0
T7	1123	1	0	0
T8	700121	2335	0	0
T9	16382	231	0	0
T10	2411	9	0	0
T11	1789	12	0	0
T12	4129	87	0	0
T13	10796	188	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3325256	0	0
T1	16756	367	0	0
T2	9552	178	0	0
T3	38595	411	0	0
T7	1123	6	0	0
T8	700121	12523	0	0
T9	16382	214	0	0
T10	2411	9	0	0
T11	1789	13	0	0
T12	4129	82	0	0
T13	10796	180	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	247132	0	0
T1	16756	55	0	0
T2	9552	184	0	0
T3	38595	421	0	0
T7	1123	1	0	0
T8	700121	2335	0	0
T9	16382	231	0	0
T10	2411	9	0	0
T11	1789	12	0	0
T12	4129	87	0	0
T13	10796	188	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	247132	0	0
T1	16756	55	0	0
T2	9552	184	0	0
T3	38595	421	0	0
T7	1123	1	0	0
T8	700121	2335	0	0
T9	16382	231	0	0
T10	2411	9	0	0
T11	1789	12	0	0
T12	4129	87	0	0
T13	10796	188	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	698911	0	0
T1	16756	65	0	0
T2	9552	191	0	0
T3	38595	439	0	0
T7	1123	1	0	0
T8	700121	5917	0	0
T9	16382	249	0	0
T10	2411	10	0	0
T11	1789	12	0	0
T12	4129	93	0	0
T13	10796	197	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	247132	0	0
T1	16756	55	0	0
T2	9552	184	0	0
T3	38595	421	0	0
T7	1123	1	0	0
T8	700121	2335	0	0
T9	16382	231	0	0
T10	2411	9	0	0
T11	1789	12	0	0
T12	4129	87	0	0
T13	10796	188	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	227824	0	0
GntImpliesValid_A	443855068	227824	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	227824	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3213027	0	0
ReadyAndValidImplyGrant_A	443855068	227824	0	0
ReqAndReadyImplyGrant_A	443855068	227824	0	0
ReqImpliesValid_A	443855068	640407	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	227824	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227824	0	0
T1	16756	33	0	0
T2	9552	124	0	0
T3	38595	881	0	0
T7	1123	0	0	0
T8	700121	665	0	0
T9	16382	221	0	0
T10	2411	6	0	0
T11	1789	7	0	0
T12	4129	56	0	0
T13	10796	149	0	0
T14	0	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227824	0	0
T1	16756	33	0	0
T2	9552	124	0	0
T3	38595	881	0	0
T7	1123	0	0	0
T8	700121	665	0	0
T9	16382	221	0	0
T10	2411	6	0	0
T11	1789	7	0	0
T12	4129	56	0	0
T13	10796	149	0	0
T14	0	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227824	0	0
T1	16756	33	0	0
T2	9552	124	0	0
T3	38595	881	0	0
T7	1123	0	0	0
T8	700121	665	0	0
T9	16382	221	0	0
T10	2411	6	0	0
T11	1789	7	0	0
T12	4129	56	0	0
T13	10796	149	0	0
T14	0	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3213027	0	0
T1	16756	249	0	0
T2	9552	121	0	0
T3	38595	430	0	0
T7	1123	2	0	0
T8	700121	4942	0	0
T9	16382	209	0	0
T10	2411	6	0	0
T11	1789	8	0	0
T12	4129	54	0	0
T13	10796	143	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227824	0	0
T1	16756	33	0	0
T2	9552	124	0	0
T3	38595	881	0	0
T7	1123	0	0	0
T8	700121	665	0	0
T9	16382	221	0	0
T10	2411	6	0	0
T11	1789	7	0	0
T12	4129	56	0	0
T13	10796	149	0	0
T14	0	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227824	0	0
T1	16756	33	0	0
T2	9552	124	0	0
T3	38595	881	0	0
T7	1123	0	0	0
T8	700121	665	0	0
T9	16382	221	0	0
T10	2411	6	0	0
T11	1789	7	0	0
T12	4129	56	0	0
T13	10796	149	0	0
T14	0	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	640407	0	0
T1	16756	33	0	0
T2	9552	128	0	0
T3	38595	1340	0	0
T7	1123	0	0	0
T8	700121	755	0	0
T9	16382	234	0	0
T10	2411	7	0	0
T11	1789	7	0	0
T12	4129	59	0	0
T13	10796	156	0	0
T14	0	121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	227824	0	0
T1	16756	33	0	0
T2	9552	124	0	0
T3	38595	881	0	0
T7	1123	0	0	0
T8	700121	665	0	0
T9	16382	221	0	0
T10	2411	6	0	0
T11	1789	7	0	0
T12	4129	56	0	0
T13	10796	149	0	0
T14	0	91	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	226387	0	0
GntImpliesValid_A	443855068	226387	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	226387	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3244965	0	0
ReadyAndValidImplyGrant_A	443855068	226387	0	0
ReqAndReadyImplyGrant_A	443855068	226387	0	0
ReqImpliesValid_A	443855068	641694	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	226387	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226387	0	0
T1	16756	26	0	0
T2	9552	137	0	0
T3	38595	1177	0	0
T7	1123	0	0	0
T8	700121	1118	0	0
T9	16382	218	0	0
T10	2411	3	0	0
T11	1789	14	0	0
T12	4129	52	0	0
T13	10796	167	0	0
T14	0	95	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226387	0	0
T1	16756	26	0	0
T2	9552	137	0	0
T3	38595	1177	0	0
T7	1123	0	0	0
T8	700121	1118	0	0
T9	16382	218	0	0
T10	2411	3	0	0
T11	1789	14	0	0
T12	4129	52	0	0
T13	10796	167	0	0
T14	0	95	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226387	0	0
T1	16756	26	0	0
T2	9552	137	0	0
T3	38595	1177	0	0
T7	1123	0	0	0
T8	700121	1118	0	0
T9	16382	218	0	0
T10	2411	3	0	0
T11	1789	14	0	0
T12	4129	52	0	0
T13	10796	167	0	0
T14	0	95	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3244965	0	0
T1	16756	189	0	0
T2	9552	135	0	0
T3	38595	776	0	0
T7	1123	2	0	0
T8	700121	5707	0	0
T9	16382	202	0	0
T10	2411	4	0	0
T11	1789	15	0	0
T12	4129	51	0	0
T13	10796	157	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226387	0	0
T1	16756	26	0	0
T2	9552	137	0	0
T3	38595	1177	0	0
T7	1123	0	0	0
T8	700121	1118	0	0
T9	16382	218	0	0
T10	2411	3	0	0
T11	1789	14	0	0
T12	4129	52	0	0
T13	10796	167	0	0
T14	0	95	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226387	0	0
T1	16756	26	0	0
T2	9552	137	0	0
T3	38595	1177	0	0
T7	1123	0	0	0
T8	700121	1118	0	0
T9	16382	218	0	0
T10	2411	3	0	0
T11	1789	14	0	0
T12	4129	52	0	0
T13	10796	167	0	0
T14	0	95	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	641694	0	0
T1	16756	26	0	0
T2	9552	140	0	0
T3	38595	1586	0	0
T7	1123	0	0	0
T8	700121	5400	0	0
T9	16382	235	0	0
T10	2411	3	0	0
T11	1789	14	0	0
T12	4129	54	0	0
T13	10796	178	0	0
T14	0	121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	226387	0	0
T1	16756	26	0	0
T2	9552	137	0	0
T3	38595	1177	0	0
T7	1123	0	0	0
T8	700121	1118	0	0
T9	16382	218	0	0
T10	2411	3	0	0
T11	1789	14	0	0
T12	4129	52	0	0
T13	10796	167	0	0
T14	0	95	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	222833	0	0
GntImpliesValid_A	443855068	222833	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	222833	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3154093	0	0
ReadyAndValidImplyGrant_A	443855068	222833	0	0
ReqAndReadyImplyGrant_A	443855068	222833	0	0
ReqImpliesValid_A	443855068	592126	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	222833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	222833	0	0
T1	16756	28	0	0
T2	9552	110	0	0
T3	38595	837	0	0
T7	1123	1	0	0
T8	700121	642	0	0
T9	16382	249	0	0
T10	2411	8	0	0
T11	1789	13	0	0
T12	4129	41	0	0
T13	10796	186	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	222833	0	0
T1	16756	28	0	0
T2	9552	110	0	0
T3	38595	837	0	0
T7	1123	1	0	0
T8	700121	642	0	0
T9	16382	249	0	0
T10	2411	8	0	0
T11	1789	13	0	0
T12	4129	41	0	0
T13	10796	186	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	222833	0	0
T1	16756	28	0	0
T2	9552	110	0	0
T3	38595	837	0	0
T7	1123	1	0	0
T8	700121	642	0	0
T9	16382	249	0	0
T10	2411	8	0	0
T11	1789	13	0	0
T12	4129	41	0	0
T13	10796	186	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3154093	0	0
T1	16756	212	0	0
T2	9552	101	0	0
T3	38595	363	0	0
T7	1123	5	0	0
T8	700121	4585	0	0
T9	16382	240	0	0
T10	2411	9	0	0
T11	1789	13	0	0
T12	4129	42	0	0
T13	10796	173	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	222833	0	0
T1	16756	28	0	0
T2	9552	110	0	0
T3	38595	837	0	0
T7	1123	1	0	0
T8	700121	642	0	0
T9	16382	249	0	0
T10	2411	8	0	0
T11	1789	13	0	0
T12	4129	41	0	0
T13	10796	186	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	222833	0	0
T1	16756	28	0	0
T2	9552	110	0	0
T3	38595	837	0	0
T7	1123	1	0	0
T8	700121	642	0	0
T9	16382	249	0	0
T10	2411	8	0	0
T11	1789	13	0	0
T12	4129	41	0	0
T13	10796	186	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	592126	0	0
T1	16756	28	0	0
T2	9552	120	0	0
T3	38595	1319	0	0
T7	1123	1	0	0
T8	700121	828	0	0
T9	16382	259	0	0
T10	2411	8	0	0
T11	1789	14	0	0
T12	4129	41	0	0
T13	10796	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	222833	0	0
T1	16756	28	0	0
T2	9552	110	0	0
T3	38595	837	0	0
T7	1123	1	0	0
T8	700121	642	0	0
T9	16382	249	0	0
T10	2411	8	0	0
T11	1789	13	0	0
T12	4129	41	0	0
T13	10796	186	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	219712	0	0
GntImpliesValid_A	443855068	219712	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	219712	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3234780	0	0
ReadyAndValidImplyGrant_A	443855068	219712	0	0
ReqAndReadyImplyGrant_A	443855068	219712	0	0
ReqImpliesValid_A	443855068	612634	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	219712	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219712	0	0
T1	16756	44	0	0
T2	9552	130	0	0
T3	38595	348	0	0
T7	1123	0	0	0
T8	700121	2888	0	0
T9	16382	212	0	0
T10	2411	10	0	0
T11	1789	21	0	0
T12	4129	48	0	0
T13	10796	156	0	0
T14	0	72	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219712	0	0
T1	16756	44	0	0
T2	9552	130	0	0
T3	38595	348	0	0
T7	1123	0	0	0
T8	700121	2888	0	0
T9	16382	212	0	0
T10	2411	10	0	0
T11	1789	21	0	0
T12	4129	48	0	0
T13	10796	156	0	0
T14	0	72	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219712	0	0
T1	16756	44	0	0
T2	9552	130	0	0
T3	38595	348	0	0
T7	1123	0	0	0
T8	700121	2888	0	0
T9	16382	212	0	0
T10	2411	10	0	0
T11	1789	21	0	0
T12	4129	48	0	0
T13	10796	156	0	0
T14	0	72	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3234780	0	0
T1	16756	311	0	0
T2	9552	127	0	0
T3	38595	346	0	0
T7	1123	2	0	0
T8	700121	12528	0	0
T9	16382	205	0	0
T10	2411	11	0	0
T11	1789	21	0	0
T12	4129	48	0	0
T13	10796	152	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219712	0	0
T1	16756	44	0	0
T2	9552	130	0	0
T3	38595	348	0	0
T7	1123	0	0	0
T8	700121	2888	0	0
T9	16382	212	0	0
T10	2411	10	0	0
T11	1789	21	0	0
T12	4129	48	0	0
T13	10796	156	0	0
T14	0	72	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219712	0	0
T1	16756	44	0	0
T2	9552	130	0	0
T3	38595	348	0	0
T7	1123	0	0	0
T8	700121	2888	0	0
T9	16382	212	0	0
T10	2411	10	0	0
T11	1789	21	0	0
T12	4129	48	0	0
T13	10796	156	0	0
T14	0	72	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	612634	0	0
T1	16756	52	0	0
T2	9552	134	0	0
T3	38595	358	0	0
T7	1123	0	0	0
T8	700121	8626	0	0
T9	16382	220	0	0
T10	2411	10	0	0
T11	1789	22	0	0
T12	4129	49	0	0
T13	10796	161	0	0
T14	0	75	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219712	0	0
T1	16756	44	0	0
T2	9552	130	0	0
T3	38595	348	0	0
T7	1123	0	0	0
T8	700121	2888	0	0
T9	16382	212	0	0
T10	2411	10	0	0
T11	1789	21	0	0
T12	4129	48	0	0
T13	10796	156	0	0
T14	0	72	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	219628	0	0
GntImpliesValid_A	443855068	219628	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	219628	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	3235153	0	0
ReadyAndValidImplyGrant_A	443855068	219628	0	0
ReqAndReadyImplyGrant_A	443855068	219628	0	0
ReqImpliesValid_A	443855068	621357	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	0	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	219628	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219628	0	0
T1	16756	32	0	0
T2	9552	116	0	0
T3	38595	353	0	0
T7	1123	3	0	0
T8	700121	1609	0	0
T9	16382	180	0	0
T10	2411	11	0	0
T11	1789	11	0	0
T12	4129	45	0	0
T13	10796	195	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219628	0	0
T1	16756	32	0	0
T2	9552	116	0	0
T3	38595	353	0	0
T7	1123	3	0	0
T8	700121	1609	0	0
T9	16382	180	0	0
T10	2411	11	0	0
T11	1789	11	0	0
T12	4129	45	0	0
T13	10796	195	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219628	0	0
T1	16756	32	0	0
T2	9552	116	0	0
T3	38595	353	0	0
T7	1123	3	0	0
T8	700121	1609	0	0
T9	16382	180	0	0
T10	2411	11	0	0
T11	1789	11	0	0
T12	4129	45	0	0
T13	10796	195	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	3235153	0	0
T1	16756	258	0	0
T2	9552	113	0	0
T3	38595	355	0	0
T7	1123	21	0	0
T8	700121	6612	0	0
T9	16382	170	0	0
T10	2411	12	0	0
T11	1789	12	0	0
T12	4129	45	0	0
T13	10796	191	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219628	0	0
T1	16756	32	0	0
T2	9552	116	0	0
T3	38595	353	0	0
T7	1123	3	0	0
T8	700121	1609	0	0
T9	16382	180	0	0
T10	2411	11	0	0
T11	1789	11	0	0
T12	4129	45	0	0
T13	10796	195	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219628	0	0
T1	16756	32	0	0
T2	9552	116	0	0
T3	38595	353	0	0
T7	1123	3	0	0
T8	700121	1609	0	0
T9	16382	180	0	0
T10	2411	11	0	0
T11	1789	11	0	0
T12	4129	45	0	0
T13	10796	195	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	621357	0	0
T1	16756	32	0	0
T2	9552	120	0	0
T3	38595	358	0	0
T7	1123	3	0	0
T8	700121	10009	0	0
T9	16382	191	0	0
T10	2411	11	0	0
T11	1789	11	0	0
T12	4129	46	0	0
T13	10796	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	219628	0	0
T1	16756	32	0	0
T2	9552	116	0	0
T3	38595	353	0	0
T7	1123	3	0	0
T8	700121	1609	0	0
T9	16382	180	0	0
T10	2411	11	0	0
T11	1789	11	0	0
T12	4129	45	0	0
T13	10796	195	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T14
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T14

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T14
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	902701	0	0
GntImpliesValid_A	443855068	902701	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	902701	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	12360155	0	0
ReadyAndValidImplyGrant_A	443855068	902701	0	0
ReqAndReadyImplyGrant_A	443855068	902701	0	0
ReqImpliesValid_A	443855068	2486502	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	20661	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	902701	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	902701	0	0
T1	16756	140	0	0
T2	9552	467	0	0
T3	38595	2092	0	0
T7	1123	6	0	0
T8	700121	7822	0	0
T9	16382	942	0	0
T10	2411	39	0	0
T11	1789	70	0	0
T12	4129	190	0	0
T13	10796	669	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	902701	0	0
T1	16756	140	0	0
T2	9552	467	0	0
T3	38595	2092	0	0
T7	1123	6	0	0
T8	700121	7822	0	0
T9	16382	942	0	0
T10	2411	39	0	0
T11	1789	70	0	0
T12	4129	190	0	0
T13	10796	669	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	902701	0	0
T1	16756	140	0	0
T2	9552	467	0	0
T3	38595	2092	0	0
T7	1123	6	0	0
T8	700121	7822	0	0
T9	16382	942	0	0
T10	2411	39	0	0
T11	1789	70	0	0
T12	4129	190	0	0
T13	10796	669	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	12360155	0	0
T1	16756	898	0	0
T2	9552	1	0	0
T3	38595	8	0	0
T7	1123	27	0	0
T8	700121	40038	0	0
T9	16382	1	0	0
T10	2411	1	0	0
T11	1789	1	0	0
T12	4129	1	0	0
T13	10796	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	902701	0	0
T1	16756	140	0	0
T2	9552	467	0	0
T3	38595	2092	0	0
T7	1123	6	0	0
T8	700121	7822	0	0
T9	16382	942	0	0
T10	2411	39	0	0
T11	1789	70	0	0
T12	4129	190	0	0
T13	10796	669	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	902701	0	0
T1	16756	140	0	0
T2	9552	467	0	0
T3	38595	2092	0	0
T7	1123	6	0	0
T8	700121	7822	0	0
T9	16382	942	0	0
T10	2411	39	0	0
T11	1789	70	0	0
T12	4129	190	0	0
T13	10796	669	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	2486502	0	0
T1	16756	221	0	0
T2	9552	467	0	0
T3	38595	2092	0	0
T7	1123	6	0	0
T8	700121	28521	0	0
T9	16382	942	0	0
T10	2411	39	0	0
T11	1789	70	0	0
T12	4129	190	0	0
T13	10796	669	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	20661	0	900
T2	9552	8	0	1
T3	38595	18	0	1
T7	1123	0	0	1
T8	700121	45	0	1
T9	16382	18	0	1
T10	2411	0	0	1
T11	1789	0	0	1
T12	4129	2	0	1
T13	10796	13	0	1
T14	52230	0	0	1
T15	0	1	0	0
T16	0	8	0	0
T17	0	27	0	0
T18	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	902701	0	0
T1	16756	140	0	0
T2	9552	467	0	0
T3	38595	2092	0	0
T7	1123	6	0	0
T8	700121	7822	0	0
T9	16382	942	0	0
T10	2411	39	0	0
T11	1789	70	0	0
T12	4129	190	0	0
T13	10796	669	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443855068	443749633	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443855068	895654	0	0
GntImpliesValid_A	443855068	895654	0	0
GrantKnown_A	443855068	443749633	0	0
IdxKnown_A	443855068	443749633	0	0
IndexIsCorrect_A	443855068	895654	0	0
LockArbDecision_A	443855068	0	0	0
NoReadyValidNoGrant_A	443855068	373174151	0	0
ReadyAndValidImplyGrant_A	443855068	895654	0	0
ReqAndReadyImplyGrant_A	443855068	895654	0	0
ReqImpliesValid_A	443855068	14255364	0	0
ReqStaysHighUntilGranted0_M	443855068	0	0	0
RoundRobin_A	443855068	29994	0	900
ValidKnown_A	443855068	443749633	0	0
gen_data_port_assertion.DataFlow_A	443855068	895654	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	895654	0	0
T1	16756	126	0	0
T2	9552	419	0	0
T3	38595	2076	0	0
T7	1123	10	0	0
T8	700121	6761	0	0
T9	16382	896	0	0
T10	2411	37	0	0
T11	1789	54	0	0
T12	4129	205	0	0
T13	10796	693	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	895654	0	0
T1	16756	126	0	0
T2	9552	419	0	0
T3	38595	2076	0	0
T7	1123	10	0	0
T8	700121	6761	0	0
T9	16382	896	0	0
T10	2411	37	0	0
T11	1789	54	0	0
T12	4129	205	0	0
T13	10796	693	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	895654	0	0
T1	16756	126	0	0
T2	9552	419	0	0
T3	38595	2076	0	0
T7	1123	10	0	0
T8	700121	6761	0	0
T9	16382	896	0	0
T10	2411	37	0	0
T11	1789	54	0	0
T12	4129	205	0	0
T13	10796	693	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	373174151	0	0
T1	16756	14033	0	0
T2	9552	1	0	0
T3	38595	1	0	0
T7	1123	836	0	0
T8	700121	587126	0	0
T9	16382	1	0	0
T10	2411	1	0	0
T11	1789	1	0	0
T12	4129	1	0	0
T13	10796	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	895654	0	0
T1	16756	126	0	0
T2	9552	419	0	0
T3	38595	2076	0	0
T7	1123	10	0	0
T8	700121	6761	0	0
T9	16382	896	0	0
T10	2411	37	0	0
T11	1789	54	0	0
T12	4129	205	0	0
T13	10796	693	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	895654	0	0
T1	16756	126	0	0
T2	9552	419	0	0
T3	38595	2076	0	0
T7	1123	10	0	0
T8	700121	6761	0	0
T9	16382	896	0	0
T10	2411	37	0	0
T11	1789	54	0	0
T12	4129	205	0	0
T13	10796	693	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	14255364	0	0
T1	16756	929	0	0
T2	9552	419	0	0
T3	38595	2076	0	0
T7	1123	84	0	0
T8	700121	55815	0	0
T9	16382	896	0	0
T10	2411	37	0	0
T11	1789	54	0	0
T12	4129	205	0	0
T13	10796	693	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	29994	0	900
T2	9552	4	0	1
T3	38595	16	0	1
T7	1123	0	0	1
T8	700121	27	0	1
T9	16382	14	0	1
T10	2411	0	0	1
T11	1789	0	0	1
T12	4129	3	0	1
T13	10796	9	0	1
T14	52230	0	0	1
T15	0	14	0	0
T16	0	11	0	0
T18	0	16	0	0
T19	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	443749633	0	0
T1	16756	16730	0	0
T2	9552	9543	0	0
T3	38595	38031	0	0
T7	1123	997	0	0
T8	700121	699834	0	0
T9	16382	16326	0	0
T10	2411	2344	0	0
T11	1789	1781	0	0
T12	4129	4111	0	0
T13	10796	10776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443855068	895654	0	0
T1	16756	126	0	0
T2	9552	419	0	0
T3	38595	2076	0	0
T7	1123	10	0	0
T8	700121	6761	0	0
T9	16382	896	0	0
T10	2411	37	0	0
T11	1789	54	0	0
T12	4129	205	0	0
T13	10796	693	0	0