Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1565957 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 248712 1 T1 408 T2 6 T3 512


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 615505 1 T1 914 T2 29 T3 1338
values[0x0] 583840 1 T1 928 T2 6 T3 1273
values[0x1] 615324 1 T1 907 T2 28 T3 1323


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1210741 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 603928 1 T1 944 T2 24 T3 1307


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28339 1 T1 42 T3 64 T8 5
valid_sources[0x01] 28726 1 T1 53 T2 3 T3 74
valid_sources[0x02] 28653 1 T1 28 T2 1 T3 63
valid_sources[0x03] 28706 1 T1 54 T3 70 T7 48
valid_sources[0x04] 27928 1 T1 47 T2 2 T3 55
valid_sources[0x05] 28519 1 T1 53 T3 54 T8 33
valid_sources[0x06] 28413 1 T1 40 T2 2 T3 67
valid_sources[0x07] 27949 1 T1 53 T2 3 T3 61
valid_sources[0x08] 28661 1 T1 46 T3 56 T8 88
valid_sources[0x09] 28590 1 T1 43 T2 1 T3 66
valid_sources[0x0a] 28649 1 T1 32 T2 1 T3 57
valid_sources[0x0b] 28695 1 T1 53 T3 55 T8 32
valid_sources[0x0c] 27965 1 T1 41 T3 62 T9 54
valid_sources[0x0d] 28845 1 T1 32 T3 54 T8 78
valid_sources[0x0e] 27447 1 T1 59 T2 2 T3 61
valid_sources[0x0f] 29304 1 T1 37 T3 58 T8 34
valid_sources[0x10] 27673 1 T1 42 T3 69 T8 30
valid_sources[0x11] 27815 1 T1 46 T3 58 T8 15
valid_sources[0x12] 28480 1 T1 47 T2 2 T3 71
valid_sources[0x13] 28800 1 T1 30 T2 2 T3 49
valid_sources[0x14] 28485 1 T1 33 T2 2 T3 61
valid_sources[0x15] 27118 1 T1 48 T2 2 T3 67
valid_sources[0x16] 28155 1 T1 38 T3 59 T8 8
valid_sources[0x17] 27572 1 T1 50 T2 1 T3 52
valid_sources[0x18] 29767 1 T1 47 T2 2 T3 54
valid_sources[0x19] 28594 1 T1 33 T2 1 T3 68
valid_sources[0x1a] 28704 1 T1 26 T2 1 T3 62
valid_sources[0x1b] 28480 1 T1 37 T2 1 T3 64
valid_sources[0x1c] 28165 1 T1 46 T3 46 T8 9
valid_sources[0x1d] 28317 1 T1 23 T2 1 T3 61
valid_sources[0x1e] 28567 1 T1 33 T2 3 T3 62
valid_sources[0x1f] 28145 1 T1 55 T3 67 T8 22
valid_sources[0x20] 27966 1 T1 47 T3 58 T7 3


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25919 1 T1 41 T3 56 T7 2
values[0x0] all_enables biggest_size 196792 1 T1 333 T2 4 T3 409
values[0x1] all_enables biggest_size 26001 1 T1 34 T2 2 T3 47


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1576895 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 256291 1 T1 368 T2 9 T3 492


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 627344 1 T1 851 T2 40 T3 1196
values[0x0] 579054 1 T1 874 T2 12 T3 1123
values[0x1] 626788 1 T1 857 T2 28 T3 1208


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1211565 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 621621 1 T1 869 T2 29 T3 1181


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28837 1 T1 38 T2 1 T3 43
valid_sources[0x01] 28434 1 T1 50 T3 42 T7 6
valid_sources[0x02] 29004 1 T1 42 T2 1 T3 60
valid_sources[0x03] 28415 1 T1 34 T2 2 T3 56
valid_sources[0x04] 28775 1 T1 23 T2 3 T3 62
valid_sources[0x05] 28484 1 T1 36 T2 1 T3 47
valid_sources[0x06] 28765 1 T1 45 T3 61 T7 1
valid_sources[0x07] 28419 1 T1 33 T2 1 T3 60
valid_sources[0x08] 29076 1 T1 35 T2 1 T3 81
valid_sources[0x09] 28382 1 T1 44 T2 1 T3 61
valid_sources[0x0a] 28853 1 T1 34 T2 3 T3 58
valid_sources[0x0b] 28876 1 T1 39 T2 2 T3 51
valid_sources[0x0c] 28590 1 T1 35 T2 4 T3 48
valid_sources[0x0d] 28835 1 T1 43 T3 60 T7 3
valid_sources[0x0e] 28770 1 T1 53 T2 4 T3 76
valid_sources[0x0f] 28937 1 T1 38 T2 1 T3 38
valid_sources[0x10] 28510 1 T1 55 T2 2 T3 55
valid_sources[0x11] 28559 1 T1 49 T2 4 T3 50
valid_sources[0x12] 29004 1 T1 33 T3 41 T7 2
valid_sources[0x13] 28718 1 T1 54 T2 2 T3 61
valid_sources[0x14] 28914 1 T1 40 T2 3 T3 50
valid_sources[0x15] 28939 1 T1 44 T3 67 T7 1
valid_sources[0x16] 28339 1 T1 40 T2 1 T3 54
valid_sources[0x17] 28115 1 T1 47 T2 2 T3 54
valid_sources[0x18] 28419 1 T1 36 T2 1 T3 42
valid_sources[0x19] 29681 1 T1 34 T3 56 T7 4
valid_sources[0x1a] 28593 1 T1 37 T2 2 T3 58
valid_sources[0x1b] 28631 1 T1 43 T2 1 T3 52
valid_sources[0x1c] 28825 1 T1 41 T2 1 T3 48
valid_sources[0x1d] 29069 1 T1 34 T2 2 T3 66
valid_sources[0x1e] 29295 1 T1 56 T3 58 T7 1
valid_sources[0x1f] 28587 1 T1 53 T2 2 T3 61
valid_sources[0x20] 28973 1 T1 38 T3 64 T7 3


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26838 1 T1 45 T2 2 T3 54
values[0x0] all_enables biggest_size 202761 1 T1 279 T2 6 T3 392
values[0x1] all_enables biggest_size 26692 1 T1 44 T2 1 T3 46


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1571395 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 250207 1 T1 393 T2 5 T3 527


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 618136 1 T1 932 T2 32 T3 1252
values[0x0] 585805 1 T1 901 T2 3 T3 1155
values[0x1] 617661 1 T1 872 T2 37 T3 1220


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1214702 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 606900 1 T1 906 T2 20 T3 1280


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28864 1 T1 30 T2 4 T3 62
valid_sources[0x01] 28512 1 T1 39 T2 3 T3 60
valid_sources[0x02] 28041 1 T1 28 T2 1 T3 58
valid_sources[0x03] 28142 1 T1 49 T2 1 T3 70
valid_sources[0x04] 29588 1 T1 38 T3 56 T8 23
valid_sources[0x05] 29650 1 T1 44 T3 59 T7 5
valid_sources[0x06] 29276 1 T1 58 T3 70 T8 46
valid_sources[0x07] 28433 1 T1 27 T3 56 T8 42
valid_sources[0x08] 28500 1 T1 47 T2 1 T3 41
valid_sources[0x09] 28204 1 T1 48 T2 1 T3 67
valid_sources[0x0a] 29209 1 T1 44 T2 2 T3 53
valid_sources[0x0b] 28741 1 T1 45 T2 2 T3 59
valid_sources[0x0c] 28940 1 T1 42 T3 53 T7 1
valid_sources[0x0d] 29201 1 T1 54 T3 59 T7 2
valid_sources[0x0e] 28669 1 T1 39 T2 1 T3 57
valid_sources[0x0f] 28903 1 T1 41 T2 3 T3 52
valid_sources[0x10] 28909 1 T1 40 T3 65 T7 1
valid_sources[0x11] 27985 1 T1 41 T2 1 T3 51
valid_sources[0x12] 28369 1 T1 53 T3 61 T7 3
valid_sources[0x13] 27477 1 T1 40 T2 1 T3 55
valid_sources[0x14] 29364 1 T1 57 T2 2 T3 53
valid_sources[0x15] 28518 1 T1 43 T2 2 T3 53
valid_sources[0x16] 27404 1 T1 46 T3 58 T7 4
valid_sources[0x17] 27463 1 T1 28 T3 48 T8 33
valid_sources[0x18] 28387 1 T1 33 T3 56 T8 53
valid_sources[0x19] 29098 1 T1 39 T3 53 T7 3
valid_sources[0x1a] 28409 1 T1 36 T2 1 T3 59
valid_sources[0x1b] 27114 1 T1 31 T2 2 T3 58
valid_sources[0x1c] 29169 1 T1 50 T3 55 T8 15
valid_sources[0x1d] 27567 1 T1 46 T2 1 T3 65
valid_sources[0x1e] 28698 1 T1 44 T2 1 T3 59
valid_sources[0x1f] 28345 1 T1 49 T2 2 T3 62
valid_sources[0x20] 28686 1 T1 36 T2 3 T3 53


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26005 1 T1 46 T2 2 T3 54
values[0x0] all_enables biggest_size 198173 1 T1 308 T2 3 T3 411
values[0x1] all_enables biggest_size 26029 1 T1 39 T3 62 T7 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%