Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7682486	0	0
GntImpliesValid_A	2147483647	7682486	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7682486	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	477697190	0	0
ReadyAndValidImplyGrant_A	2147483647	7682486	0	0
ReqAndReadyImplyGrant_A	2147483647	7682486	0	0
ReqImpliesValid_A	2147483647	34755399	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46557	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7682486	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1715856	1715448	0	0
T2	174408	173808	0	0
T3	10991448	10991304	0	0
T7	10283928	10283448	0	0
T8	2050944	2039184	0	0
T9	1563768	1562688	0	0
T10	57744	56112	0	0
T11	309672	308208	0	0
T12	1850136	1849080	0	0
T13	11599512	11597760	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7682486	0	0
T1	1715856	8032	0	0
T2	174408	4423	0	0
T3	10991448	11084	0	0
T7	10283928	414	0	0
T8	2050944	6112	0	0
T9	1563768	4087	0	0
T10	57744	435	0	0
T11	309672	477	0	0
T12	1850136	8275	0	0
T13	11599512	468	0	0
T14	0	15256	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7682486	0	0
T1	1715856	8032	0	0
T2	174408	4423	0	0
T3	10991448	11084	0	0
T7	10283928	414	0	0
T8	2050944	6112	0	0
T9	1563768	4087	0	0
T10	57744	435	0	0
T11	309672	477	0	0
T12	1850136	8275	0	0
T13	11599512	468	0	0
T14	0	15256	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1715856	1715448	0	0
T2	174408	173808	0	0
T3	10991448	10991304	0	0
T7	10283928	10283448	0	0
T8	2050944	2039184	0	0
T9	1563768	1562688	0	0
T10	57744	56112	0	0
T11	309672	308208	0	0
T12	1850136	1849080	0	0
T13	11599512	11597760	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1715856	1715448	0	0
T2	174408	173808	0	0
T3	10991448	10991304	0	0
T7	10283928	10283448	0	0
T8	2050944	2039184	0	0
T9	1563768	1562688	0	0
T10	57744	56112	0	0
T11	309672	308208	0	0
T12	1850136	1849080	0	0
T13	11599512	11597760	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7682486	0	0
T1	1715856	8032	0	0
T2	174408	4423	0	0
T3	10991448	11084	0	0
T7	10283928	414	0	0
T8	2050944	6112	0	0
T9	1563768	4087	0	0
T10	57744	435	0	0
T11	309672	477	0	0
T12	1850136	8275	0	0
T13	11599512	468	0	0
T14	0	15256	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	477697190	0	0
T1	1715856	112577	0	0
T2	174408	4983	0	0
T3	10991448	424852	0	0
T7	10283928	538739	0	0
T8	2050944	115022	0	0
T9	1563768	91108	0	0
T10	57744	766	0	0
T11	309672	15160	0	0
T12	1850136	120480	0	0
T13	11599512	603236	0	0
T14	0	12845	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7682486	0	0
T1	1715856	8032	0	0
T2	174408	4423	0	0
T3	10991448	11084	0	0
T7	10283928	414	0	0
T8	2050944	6112	0	0
T9	1563768	4087	0	0
T10	57744	435	0	0
T11	309672	477	0	0
T12	1850136	8275	0	0
T13	11599512	468	0	0
T14	0	15256	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7682486	0	0
T1	1715856	8032	0	0
T2	174408	4423	0	0
T3	10991448	11084	0	0
T7	10283928	414	0	0
T8	2050944	6112	0	0
T9	1563768	4087	0	0
T10	57744	435	0	0
T11	309672	477	0	0
T12	1850136	8275	0	0
T13	11599512	468	0	0
T14	0	15256	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34755399	0	0
T1	1715856	18018	0	0
T2	174408	5117	0	0
T3	10991448	28631	0	0
T7	10283928	25454	0	0
T8	2050944	13219	0	0
T9	1563768	8597	0	0
T10	57744	497	0	0
T11	309672	1403	0	0
T12	1850136	19409	0	0
T13	11599512	24349	0	0
T14	0	26682	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46557	0	21600
T1	71494	1	0	1
T2	14534	19	0	2
T3	915954	15	0	2
T7	856994	0	0	2
T8	170912	23	0	2
T9	130314	0	0	2
T10	4812	0	0	2
T11	25806	0	0	2
T12	154178	1	0	2
T13	966626	0	0	2
T14	117848	1546	0	1
T15	0	25	0	0
T16	0	5	0	0
T17	0	2	0	0
T18	0	1103	0	0
T19	0	379	0	0
T20	0	13	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1715856	1715448	0	0
T2	174408	173808	0	0
T3	10991448	10991304	0	0
T7	10283928	10283448	0	0
T8	2050944	2039184	0	0
T9	1563768	1562688	0	0
T10	57744	56112	0	0
T11	309672	308208	0	0
T12	1850136	1849080	0	0
T13	11599512	11597760	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7682486	0	0
T1	1715856	8032	0	0
T2	174408	4423	0	0
T3	10991448	11084	0	0
T7	10283928	414	0	0
T8	2050944	6112	0	0
T9	1563768	4087	0	0
T10	57744	435	0	0
T11	309672	477	0	0
T12	1850136	8275	0	0
T13	11599512	468	0	0
T14	0	15256	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	838995	0	0
GntImpliesValid_A	442939900	838995	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	838995	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	12074973	0	0
ReadyAndValidImplyGrant_A	442939900	838995	0	0
ReqAndReadyImplyGrant_A	442939900	838995	0	0
ReqImpliesValid_A	442939900	2371686	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	838995	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	838995	0	0
T1	71494	928	0	0
T2	7267	508	0	0
T3	457977	822	0	0
T7	428497	39	0	0
T8	85456	675	0	0
T9	65157	423	0	0
T10	2406	42	0	0
T11	12903	85	0	0
T12	77089	907	0	0
T13	483313	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	838995	0	0
T1	71494	928	0	0
T2	7267	508	0	0
T3	457977	822	0	0
T7	428497	39	0	0
T8	85456	675	0	0
T9	65157	423	0	0
T10	2406	42	0	0
T11	12903	85	0	0
T12	77089	907	0	0
T13	483313	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	838995	0	0
T1	71494	928	0	0
T2	7267	508	0	0
T3	457977	822	0	0
T7	428497	39	0	0
T8	85456	675	0	0
T9	65157	423	0	0
T10	2406	42	0	0
T11	12903	85	0	0
T12	77089	907	0	0
T13	483313	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	12074973	0	0
T1	71494	6483	0	0
T2	7267	368	0	0
T3	457977	3421	0	0
T7	428497	12225	0	0
T8	85456	4916	0	0
T9	65157	3119	0	0
T10	2406	33	0	0
T11	12903	613	0	0
T12	77089	6681	0	0
T13	483313	15138	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	838995	0	0
T1	71494	928	0	0
T2	7267	508	0	0
T3	457977	822	0	0
T7	428497	39	0	0
T8	85456	675	0	0
T9	65157	423	0	0
T10	2406	42	0	0
T11	12903	85	0	0
T12	77089	907	0	0
T13	483313	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	838995	0	0
T1	71494	928	0	0
T2	7267	508	0	0
T3	457977	822	0	0
T7	428497	39	0	0
T8	85456	675	0	0
T9	65157	423	0	0
T10	2406	42	0	0
T11	12903	85	0	0
T12	77089	907	0	0
T13	483313	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2371686	0	0
T1	71494	1578	0	0
T2	7267	649	0	0
T3	457977	1179	0	0
T7	428497	366	0	0
T8	85456	896	0	0
T9	65157	671	0	0
T10	2406	52	0	0
T11	12903	114	0	0
T12	77089	1657	0	0
T13	483313	1015	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	838995	0	0
T1	71494	928	0	0
T2	7267	508	0	0
T3	457977	822	0	0
T7	428497	39	0	0
T8	85456	675	0	0
T9	65157	423	0	0
T10	2406	42	0	0
T11	12903	85	0	0
T12	77089	907	0	0
T13	483313	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	862314	0	0
GntImpliesValid_A	442939900	862314	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	862314	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	12117792	0	0
ReadyAndValidImplyGrant_A	442939900	862314	0	0
ReqAndReadyImplyGrant_A	442939900	862314	0	0
ReqImpliesValid_A	442939900	2464153	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	862314	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	862314	0	0
T1	71494	822	0	0
T2	7267	475	0	0
T3	457977	835	0	0
T7	428497	46	0	0
T8	85456	654	0	0
T9	65157	443	0	0
T10	2406	39	0	0
T11	12903	54	0	0
T12	77089	925	0	0
T13	483313	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	862314	0	0
T1	71494	822	0	0
T2	7267	475	0	0
T3	457977	835	0	0
T7	428497	46	0	0
T8	85456	654	0	0
T9	65157	443	0	0
T10	2406	39	0	0
T11	12903	54	0	0
T12	77089	925	0	0
T13	483313	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	862314	0	0
T1	71494	822	0	0
T2	7267	475	0	0
T3	457977	835	0	0
T7	428497	46	0	0
T8	85456	654	0	0
T9	65157	443	0	0
T10	2406	39	0	0
T11	12903	54	0	0
T12	77089	925	0	0
T13	483313	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	12117792	0	0
T1	71494	5995	0	0
T2	7267	340	0	0
T3	457977	3421	0	0
T7	428497	13954	0	0
T8	85456	4872	0	0
T9	65157	3356	0	0
T10	2406	31	0	0
T11	12903	430	0	0
T12	77089	5876	0	0
T13	483313	14964	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	862314	0	0
T1	71494	822	0	0
T2	7267	475	0	0
T3	457977	835	0	0
T7	428497	46	0	0
T8	85456	654	0	0
T9	65157	443	0	0
T10	2406	39	0	0
T11	12903	54	0	0
T12	77089	925	0	0
T13	483313	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	862314	0	0
T1	71494	822	0	0
T2	7267	475	0	0
T3	457977	835	0	0
T7	428497	46	0	0
T8	85456	654	0	0
T9	65157	443	0	0
T10	2406	39	0	0
T11	12903	54	0	0
T12	77089	925	0	0
T13	483313	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2464153	0	0
T1	71494	1627	0	0
T2	7267	611	0	0
T3	457977	1220	0	0
T7	428497	1358	0	0
T8	85456	981	0	0
T9	65157	591	0	0
T10	2406	48	0	0
T11	12903	80	0	0
T12	77089	1719	0	0
T13	483313	377	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	862314	0	0
T1	71494	822	0	0
T2	7267	475	0	0
T3	457977	835	0	0
T7	428497	46	0	0
T8	85456	654	0	0
T9	65157	443	0	0
T10	2406	39	0	0
T11	12903	54	0	0
T12	77089	925	0	0
T13	483313	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	207727	0	0
GntImpliesValid_A	442939900	207727	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	207727	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	2933227	0	0
ReadyAndValidImplyGrant_A	442939900	207727	0	0
ReqAndReadyImplyGrant_A	442939900	207727	0	0
ReqImpliesValid_A	442939900	548367	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	207727	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207727	0	0
T1	71494	224	0	0
T2	7267	105	0	0
T3	457977	1030	0	0
T7	428497	9	0	0
T8	85456	222	0	0
T9	65157	108	0	0
T10	2406	24	0	0
T11	12903	16	0	0
T12	77089	243	0	0
T13	483313	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207727	0	0
T1	71494	224	0	0
T2	7267	105	0	0
T3	457977	1030	0	0
T7	428497	9	0	0
T8	85456	222	0	0
T9	65157	108	0	0
T10	2406	24	0	0
T11	12903	16	0	0
T12	77089	243	0	0
T13	483313	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207727	0	0
T1	71494	224	0	0
T2	7267	105	0	0
T3	457977	1030	0	0
T7	428497	9	0	0
T8	85456	222	0	0
T9	65157	108	0	0
T10	2406	24	0	0
T11	12903	16	0	0
T12	77089	243	0	0
T13	483313	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2933227	0	0
T1	71494	1690	0	0
T2	7267	102	0	0
T3	457977	3392	0	0
T7	428497	3727	0	0
T8	85456	1528	0	0
T9	65157	766	0	0
T10	2406	23	0	0
T11	12903	107	0	0
T12	77089	1941	0	0
T13	483313	3312	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207727	0	0
T1	71494	224	0	0
T2	7267	105	0	0
T3	457977	1030	0	0
T7	428497	9	0	0
T8	85456	222	0	0
T9	65157	108	0	0
T10	2406	24	0	0
T11	12903	16	0	0
T12	77089	243	0	0
T13	483313	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207727	0	0
T1	71494	224	0	0
T2	7267	105	0	0
T3	457977	1030	0	0
T7	428497	9	0	0
T8	85456	222	0	0
T9	65157	108	0	0
T10	2406	24	0	0
T11	12903	16	0	0
T12	77089	243	0	0
T13	483313	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	548367	0	0
T1	71494	294	0	0
T2	7267	109	0	0
T3	457977	2319	0	0
T7	428497	9	0	0
T8	85456	288	0	0
T9	65157	130	0	0
T10	2406	26	0	0
T11	12903	16	0	0
T12	77089	359	0	0
T13	483313	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207727	0	0
T1	71494	224	0	0
T2	7267	105	0	0
T3	457977	1030	0	0
T7	428497	9	0	0
T8	85456	222	0	0
T9	65157	108	0	0
T10	2406	24	0	0
T11	12903	16	0	0
T12	77089	243	0	0
T13	483313	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	205153	0	0
GntImpliesValid_A	442939900	205153	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	205153	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	2933065	0	0
ReadyAndValidImplyGrant_A	442939900	205153	0	0
ReqAndReadyImplyGrant_A	442939900	205153	0	0
ReqImpliesValid_A	442939900	535888	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	205153	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	205153	0	0
T1	71494	219	0	0
T2	7267	118	0	0
T3	457977	480	0	0
T7	428497	15	0	0
T8	85456	149	0	0
T9	65157	117	0	0
T10	2406	17	0	0
T11	12903	12	0	0
T12	77089	225	0	0
T13	483313	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	205153	0	0
T1	71494	219	0	0
T2	7267	118	0	0
T3	457977	480	0	0
T7	428497	15	0	0
T8	85456	149	0	0
T9	65157	117	0	0
T10	2406	17	0	0
T11	12903	12	0	0
T12	77089	225	0	0
T13	483313	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	205153	0	0
T1	71494	219	0	0
T2	7267	118	0	0
T3	457977	480	0	0
T7	428497	15	0	0
T8	85456	149	0	0
T9	65157	117	0	0
T10	2406	17	0	0
T11	12903	12	0	0
T12	77089	225	0	0
T13	483313	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2933065	0	0
T1	71494	1527	0	0
T2	7267	107	0	0
T3	457977	1585	0	0
T7	428497	4638	0	0
T8	85456	1169	0	0
T9	65157	869	0	0
T10	2406	18	0	0
T11	12903	72	0	0
T12	77089	1603	0	0
T13	483313	3682	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	205153	0	0
T1	71494	219	0	0
T2	7267	118	0	0
T3	457977	480	0	0
T7	428497	15	0	0
T8	85456	149	0	0
T9	65157	117	0	0
T10	2406	17	0	0
T11	12903	12	0	0
T12	77089	225	0	0
T13	483313	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	205153	0	0
T1	71494	219	0	0
T2	7267	118	0	0
T3	457977	480	0	0
T7	428497	15	0	0
T8	85456	149	0	0
T9	65157	117	0	0
T10	2406	17	0	0
T11	12903	12	0	0
T12	77089	225	0	0
T13	483313	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	535888	0	0
T1	71494	313	0	0
T2	7267	130	0	0
T3	457977	1146	0	0
T7	428497	881	0	0
T8	85456	166	0	0
T9	65157	159	0	0
T10	2406	17	0	0
T11	12903	12	0	0
T12	77089	316	0	0
T13	483313	498	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	205153	0	0
T1	71494	219	0	0
T2	7267	118	0	0
T3	457977	480	0	0
T7	428497	15	0	0
T8	85456	149	0	0
T9	65157	117	0	0
T10	2406	17	0	0
T11	12903	12	0	0
T12	77089	225	0	0
T13	483313	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	204493	0	0
GntImpliesValid_A	442939900	204493	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	204493	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	6219332	0	0
ReadyAndValidImplyGrant_A	442939900	204493	0	0
ReqAndReadyImplyGrant_A	442939900	204493	0	0
ReqImpliesValid_A	442939900	1302407	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	204493	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	204493	0	0
T1	71494	228	0	0
T2	7267	131	0	0
T3	457977	477	0	0
T7	428497	15	0	0
T8	85456	143	0	0
T9	65157	113	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	220	0	0
T13	483313	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	204493	0	0
T1	71494	228	0	0
T2	7267	131	0	0
T3	457977	477	0	0
T7	428497	15	0	0
T8	85456	143	0	0
T9	65157	113	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	220	0	0
T13	483313	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	204493	0	0
T1	71494	228	0	0
T2	7267	131	0	0
T3	457977	477	0	0
T7	428497	15	0	0
T8	85456	143	0	0
T9	65157	113	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	220	0	0
T13	483313	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	6219332	0	0
T1	71494	1296	0	0
T2	7267	546	0	0
T3	457977	3793	0	0
T7	428497	1512	0	0
T8	85456	4006	0	0
T9	65157	1790	0	0
T10	2406	53	0	0
T11	12903	124	0	0
T12	77089	2532	0	0
T13	483313	7646	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	204493	0	0
T1	71494	228	0	0
T2	7267	131	0	0
T3	457977	477	0	0
T7	428497	15	0	0
T8	85456	143	0	0
T9	65157	113	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	220	0	0
T13	483313	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	204493	0	0
T1	71494	228	0	0
T2	7267	131	0	0
T3	457977	477	0	0
T7	428497	15	0	0
T8	85456	143	0	0
T9	65157	113	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	220	0	0
T13	483313	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	1302407	0	0
T1	71494	299	0	0
T2	7267	195	0	0
T3	457977	2015	0	0
T7	428497	15	0	0
T8	85456	305	0	0
T9	65157	188	0	0
T10	2406	27	0	0
T11	12903	28	0	0
T12	77089	355	0	0
T13	483313	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	204493	0	0
T1	71494	228	0	0
T2	7267	131	0	0
T3	457977	477	0	0
T7	428497	15	0	0
T8	85456	143	0	0
T9	65157	113	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	220	0	0
T13	483313	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	217816	0	0
GntImpliesValid_A	442939900	217816	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	217816	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	4692550	0	0
ReadyAndValidImplyGrant_A	442939900	217816	0	0
ReqAndReadyImplyGrant_A	442939900	217816	0	0
ReqImpliesValid_A	442939900	1277035	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	217816	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	217816	0	0
T1	71494	226	0	0
T2	7267	141	0	0
T3	457977	486	0	0
T7	428497	7	0	0
T8	85456	149	0	0
T9	65157	110	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	217816	0	0
T1	71494	226	0	0
T2	7267	141	0	0
T3	457977	486	0	0
T7	428497	7	0	0
T8	85456	149	0	0
T9	65157	110	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	217816	0	0
T1	71494	226	0	0
T2	7267	141	0	0
T3	457977	486	0	0
T7	428497	7	0	0
T8	85456	149	0	0
T9	65157	110	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	4692550	0	0
T1	71494	1667	0	0
T2	7267	769	0	0
T3	457977	3928	0	0
T7	428497	4104	0	0
T8	85456	2290	0	0
T9	65157	4004	0	0
T10	2406	170	0	0
T11	12903	724	0	0
T12	77089	2892	0	0
T13	483313	6062	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	217816	0	0
T1	71494	226	0	0
T2	7267	141	0	0
T3	457977	486	0	0
T7	428497	7	0	0
T8	85456	149	0	0
T9	65157	110	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	217816	0	0
T1	71494	226	0	0
T2	7267	141	0	0
T3	457977	486	0	0
T7	428497	7	0	0
T8	85456	149	0	0
T9	65157	110	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	1277035	0	0
T1	71494	317	0	0
T2	7267	217	0	0
T3	457977	2034	0	0
T7	428497	7	0	0
T8	85456	157	0	0
T9	65157	325	0	0
T10	2406	14	0	0
T11	12903	256	0	0
T12	77089	387	0	0
T13	483313	824	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	217816	0	0
T1	71494	226	0	0
T2	7267	141	0	0
T3	457977	486	0	0
T7	428497	7	0	0
T8	85456	149	0	0
T9	65157	110	0	0
T10	2406	14	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	218413	0	0
GntImpliesValid_A	442939900	218413	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	218413	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	5169342	0	0
ReadyAndValidImplyGrant_A	442939900	218413	0	0
ReqAndReadyImplyGrant_A	442939900	218413	0	0
ReqImpliesValid_A	442939900	1240227	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	218413	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218413	0	0
T1	71494	234	0	0
T2	7267	138	0	0
T3	457977	1073	0	0
T7	428497	15	0	0
T8	85456	181	0	0
T9	65157	125	0	0
T10	2406	15	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218413	0	0
T1	71494	234	0	0
T2	7267	138	0	0
T3	457977	1073	0	0
T7	428497	15	0	0
T8	85456	181	0	0
T9	65157	125	0	0
T10	2406	15	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218413	0	0
T1	71494	234	0	0
T2	7267	138	0	0
T3	457977	1073	0	0
T7	428497	15	0	0
T8	85456	181	0	0
T9	65157	125	0	0
T10	2406	15	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	5169342	0	0
T1	71494	1340	0	0
T2	7267	578	0	0
T3	457977	8027	0	0
T7	428497	10175	0	0
T8	85456	1261	0	0
T9	65157	4315	0	0
T10	2406	211	0	0
T11	12903	377	0	0
T12	77089	2565	0	0
T13	483313	6358	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218413	0	0
T1	71494	234	0	0
T2	7267	138	0	0
T3	457977	1073	0	0
T7	428497	15	0	0
T8	85456	181	0	0
T9	65157	125	0	0
T10	2406	15	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218413	0	0
T1	71494	234	0	0
T2	7267	138	0	0
T3	457977	1073	0	0
T7	428497	15	0	0
T8	85456	181	0	0
T9	65157	125	0	0
T10	2406	15	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	1240227	0	0
T1	71494	272	0	0
T2	7267	213	0	0
T3	457977	3881	0	0
T7	428497	15	0	0
T8	85456	216	0	0
T9	65157	263	0	0
T10	2406	28	0	0
T11	12903	12	0	0
T12	77089	373	0	0
T13	483313	428	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218413	0	0
T1	71494	234	0	0
T2	7267	138	0	0
T3	457977	1073	0	0
T7	428497	15	0	0
T8	85456	181	0	0
T9	65157	125	0	0
T10	2406	15	0	0
T11	12903	12	0	0
T12	77089	217	0	0
T13	483313	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	213369	0	0
GntImpliesValid_A	442939900	213369	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	213369	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	5537330	0	0
ReadyAndValidImplyGrant_A	442939900	213369	0	0
ReqAndReadyImplyGrant_A	442939900	213369	0	0
ReqImpliesValid_A	442939900	1217249	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	213369	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213369	0	0
T1	71494	217	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	179	0	0
T9	65157	112	0	0
T10	2406	8	0	0
T11	12903	10	0	0
T12	77089	258	0	0
T13	483313	7	0	0
T14	0	1912	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213369	0	0
T1	71494	217	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	179	0	0
T9	65157	112	0	0
T10	2406	8	0	0
T11	12903	10	0	0
T12	77089	258	0	0
T13	483313	7	0	0
T14	0	1912	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213369	0	0
T1	71494	217	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	179	0	0
T9	65157	112	0	0
T10	2406	8	0	0
T11	12903	10	0	0
T12	77089	258	0	0
T13	483313	7	0	0
T14	0	1912	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	5537330	0	0
T1	71494	4587	0	0
T2	7267	488	0	0
T3	457977	0	0	0
T7	428497	1820	0	0
T8	85456	4511	0	0
T9	65157	1323	0	0
T10	2406	32	0	0
T11	12903	140	0	0
T12	77089	2929	0	0
T13	483313	4314	0	0
T14	0	12845	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213369	0	0
T1	71494	217	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	179	0	0
T9	65157	112	0	0
T10	2406	8	0	0
T11	12903	10	0	0
T12	77089	258	0	0
T13	483313	7	0	0
T14	0	1912	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213369	0	0
T1	71494	217	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	179	0	0
T9	65157	112	0	0
T10	2406	8	0	0
T11	12903	10	0	0
T12	77089	258	0	0
T13	483313	7	0	0
T14	0	1912	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	1217249	0	0
T1	71494	624	0	0
T2	7267	200	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	412	0	0
T9	65157	140	0	0
T10	2406	15	0	0
T11	12903	21	0	0
T12	77089	433	0	0
T13	483313	7	0	0
T14	0	10862	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213369	0	0
T1	71494	217	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	179	0	0
T9	65157	112	0	0
T10	2406	8	0	0
T11	12903	10	0	0
T12	77089	258	0	0
T13	483313	7	0	0
T14	0	1912	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	201916	0	0
GntImpliesValid_A	442939900	201916	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	201916	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	3035070	0	0
ReadyAndValidImplyGrant_A	442939900	201916	0	0
ReqAndReadyImplyGrant_A	442939900	201916	0	0
ReqImpliesValid_A	442939900	570689	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	201916	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	201916	0	0
T1	71494	208	0	0
T2	7267	130	0	0
T3	457977	950	0	0
T7	428497	11	0	0
T8	85456	148	0	0
T9	65157	124	0	0
T10	2406	9	0	0
T11	12903	7	0	0
T12	77089	232	0	0
T13	483313	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	201916	0	0
T1	71494	208	0	0
T2	7267	130	0	0
T3	457977	950	0	0
T7	428497	11	0	0
T8	85456	148	0	0
T9	65157	124	0	0
T10	2406	9	0	0
T11	12903	7	0	0
T12	77089	232	0	0
T13	483313	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	201916	0	0
T1	71494	208	0	0
T2	7267	130	0	0
T3	457977	950	0	0
T7	428497	11	0	0
T8	85456	148	0	0
T9	65157	124	0	0
T10	2406	9	0	0
T11	12903	7	0	0
T12	77089	232	0	0
T13	483313	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	3035070	0	0
T1	71494	1632	0	0
T2	7267	127	0	0
T3	457977	3125	0	0
T7	428497	3473	0	0
T8	85456	1122	0	0
T9	65157	945	0	0
T10	2406	10	0	0
T11	12903	39	0	0
T12	77089	1768	0	0
T13	483313	3893	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	201916	0	0
T1	71494	208	0	0
T2	7267	130	0	0
T3	457977	950	0	0
T7	428497	11	0	0
T8	85456	148	0	0
T9	65157	124	0	0
T10	2406	9	0	0
T11	12903	7	0	0
T12	77089	232	0	0
T13	483313	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	201916	0	0
T1	71494	208	0	0
T2	7267	130	0	0
T3	457977	950	0	0
T7	428497	11	0	0
T8	85456	148	0	0
T9	65157	124	0	0
T10	2406	9	0	0
T11	12903	7	0	0
T12	77089	232	0	0
T13	483313	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	570689	0	0
T1	71494	297	0	0
T2	7267	134	0	0
T3	457977	2317	0	0
T7	428497	11	0	0
T8	85456	179	0	0
T9	65157	152	0	0
T10	2406	9	0	0
T11	12903	16	0	0
T12	77089	338	0	0
T13	483313	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	201916	0	0
T1	71494	208	0	0
T2	7267	130	0	0
T3	457977	950	0	0
T7	428497	11	0	0
T8	85456	148	0	0
T9	65157	124	0	0
T10	2406	9	0	0
T11	12903	7	0	0
T12	77089	232	0	0
T13	483313	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	200736	0	0
GntImpliesValid_A	442939900	200736	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	200736	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	2999438	0	0
ReadyAndValidImplyGrant_A	442939900	200736	0	0
ReqAndReadyImplyGrant_A	442939900	200736	0	0
ReqImpliesValid_A	442939900	547391	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	200736	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	200736	0	0
T1	71494	256	0	0
T2	7267	126	0	0
T3	457977	0	0	0
T7	428497	6	0	0
T8	85456	156	0	0
T9	65157	95	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	237	0	0
T13	483313	15	0	0
T14	0	990	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	200736	0	0
T1	71494	256	0	0
T2	7267	126	0	0
T3	457977	0	0	0
T7	428497	6	0	0
T8	85456	156	0	0
T9	65157	95	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	237	0	0
T13	483313	15	0	0
T14	0	990	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	200736	0	0
T1	71494	256	0	0
T2	7267	126	0	0
T3	457977	0	0	0
T7	428497	6	0	0
T8	85456	156	0	0
T9	65157	95	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	237	0	0
T13	483313	15	0	0
T14	0	990	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2999438	0	0
T1	71494	1862	0	0
T2	7267	119	0	0
T3	457977	1	0	0
T7	428497	2261	0	0
T8	85456	1183	0	0
T9	65157	660	0	0
T10	2406	12	0	0
T11	12903	98	0	0
T12	77089	1839	0	0
T13	483313	4511	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	200736	0	0
T1	71494	256	0	0
T2	7267	126	0	0
T3	457977	0	0	0
T7	428497	6	0	0
T8	85456	156	0	0
T9	65157	95	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	237	0	0
T13	483313	15	0	0
T14	0	990	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	200736	0	0
T1	71494	256	0	0
T2	7267	126	0	0
T3	457977	0	0	0
T7	428497	6	0	0
T8	85456	156	0	0
T9	65157	95	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	237	0	0
T13	483313	15	0	0
T14	0	990	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	547391	0	0
T1	71494	398	0	0
T2	7267	134	0	0
T3	457977	0	0	0
T7	428497	6	0	0
T8	85456	184	0	0
T9	65157	104	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	344	0	0
T13	483313	826	0	0
T14	0	1012	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	200736	0	0
T1	71494	256	0	0
T2	7267	126	0	0
T3	457977	0	0	0
T7	428497	6	0	0
T8	85456	156	0	0
T9	65157	95	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	237	0	0
T13	483313	15	0	0
T14	0	990	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	202461	0	0
GntImpliesValid_A	442939900	202461	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	202461	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	2977159	0	0
ReadyAndValidImplyGrant_A	442939900	202461	0	0
ReqAndReadyImplyGrant_A	442939900	202461	0	0
ReqImpliesValid_A	442939900	536177	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	202461	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	202461	0	0
T1	71494	244	0	0
T2	7267	131	0	0
T3	457977	474	0	0
T7	428497	11	0	0
T8	85456	137	0	0
T9	65157	109	0	0
T10	2406	15	0	0
T11	12903	15	0	0
T12	77089	208	0	0
T13	483313	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	202461	0	0
T1	71494	244	0	0
T2	7267	131	0	0
T3	457977	474	0	0
T7	428497	11	0	0
T8	85456	137	0	0
T9	65157	109	0	0
T10	2406	15	0	0
T11	12903	15	0	0
T12	77089	208	0	0
T13	483313	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	202461	0	0
T1	71494	244	0	0
T2	7267	131	0	0
T3	457977	474	0	0
T7	428497	11	0	0
T8	85456	137	0	0
T9	65157	109	0	0
T10	2406	15	0	0
T11	12903	15	0	0
T12	77089	208	0	0
T13	483313	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2977159	0	0
T1	71494	1725	0	0
T2	7267	121	0	0
T3	457977	1502	0	0
T7	428497	4138	0	0
T8	85456	873	0	0
T9	65157	771	0	0
T10	2406	15	0	0
T11	12903	101	0	0
T12	77089	1622	0	0
T13	483313	3547	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	202461	0	0
T1	71494	244	0	0
T2	7267	131	0	0
T3	457977	474	0	0
T7	428497	11	0	0
T8	85456	137	0	0
T9	65157	109	0	0
T10	2406	15	0	0
T11	12903	15	0	0
T12	77089	208	0	0
T13	483313	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	202461	0	0
T1	71494	244	0	0
T2	7267	131	0	0
T3	457977	474	0	0
T7	428497	11	0	0
T8	85456	137	0	0
T9	65157	109	0	0
T10	2406	15	0	0
T11	12903	15	0	0
T12	77089	208	0	0
T13	483313	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	536177	0	0
T1	71494	384	0	0
T2	7267	142	0	0
T3	457977	1142	0	0
T7	428497	11	0	0
T8	85456	152	0	0
T9	65157	131	0	0
T10	2406	16	0	0
T11	12903	15	0	0
T12	77089	270	0	0
T13	483313	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	202461	0	0
T1	71494	244	0	0
T2	7267	131	0	0
T3	457977	474	0	0
T7	428497	11	0	0
T8	85456	137	0	0
T9	65157	109	0	0
T10	2406	15	0	0
T11	12903	15	0	0
T12	77089	208	0	0
T13	483313	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	219384	0	0
GntImpliesValid_A	442939900	219384	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	219384	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	3006308	0	0
ReadyAndValidImplyGrant_A	442939900	219384	0	0
ReqAndReadyImplyGrant_A	442939900	219384	0	0
ReqImpliesValid_A	442939900	607407	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	219384	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	219384	0	0
T1	71494	209	0	0
T2	7267	139	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	151	0	0
T9	65157	100	0	0
T10	2406	12	0	0
T11	12903	9	0	0
T12	77089	227	0	0
T13	483313	12	0	0
T14	0	2134	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	219384	0	0
T1	71494	209	0	0
T2	7267	139	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	151	0	0
T9	65157	100	0	0
T10	2406	12	0	0
T11	12903	9	0	0
T12	77089	227	0	0
T13	483313	12	0	0
T14	0	2134	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	219384	0	0
T1	71494	209	0	0
T2	7267	139	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	151	0	0
T9	65157	100	0	0
T10	2406	12	0	0
T11	12903	9	0	0
T12	77089	227	0	0
T13	483313	12	0	0
T14	0	2134	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	3006308	0	0
T1	71494	1453	0	0
T2	7267	128	0	0
T3	457977	1	0	0
T7	428497	6817	0	0
T8	85456	1218	0	0
T9	65157	681	0	0
T10	2406	11	0	0
T11	12903	67	0	0
T12	77089	1595	0	0
T13	483313	4413	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	219384	0	0
T1	71494	209	0	0
T2	7267	139	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	151	0	0
T9	65157	100	0	0
T10	2406	12	0	0
T11	12903	9	0	0
T12	77089	227	0	0
T13	483313	12	0	0
T14	0	2134	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	219384	0	0
T1	71494	209	0	0
T2	7267	139	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	151	0	0
T9	65157	100	0	0
T10	2406	12	0	0
T11	12903	9	0	0
T12	77089	227	0	0
T13	483313	12	0	0
T14	0	2134	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	607407	0	0
T1	71494	332	0	0
T2	7267	151	0	0
T3	457977	0	0	0
T7	428497	85	0	0
T8	85456	173	0	0
T9	65157	111	0	0
T10	2406	14	0	0
T11	12903	20	0	0
T12	77089	312	0	0
T13	483313	578	0	0
T14	0	2825	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	219384	0	0
T1	71494	209	0	0
T2	7267	139	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	151	0	0
T9	65157	100	0	0
T10	2406	12	0	0
T11	12903	9	0	0
T12	77089	227	0	0
T13	483313	12	0	0
T14	0	2134	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	215266	0	0
GntImpliesValid_A	442939900	215266	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	215266	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	3084778	0	0
ReadyAndValidImplyGrant_A	442939900	215266	0	0
ReqAndReadyImplyGrant_A	442939900	215266	0	0
ReqImpliesValid_A	442939900	632792	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	215266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	215266	0	0
T1	71494	227	0	0
T2	7267	119	0	0
T3	457977	579	0	0
T7	428497	18	0	0
T8	85456	151	0	0
T9	65157	117	0	0
T10	2406	10	0	0
T11	12903	10	0	0
T12	77089	209	0	0
T13	483313	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	215266	0	0
T1	71494	227	0	0
T2	7267	119	0	0
T3	457977	579	0	0
T7	428497	18	0	0
T8	85456	151	0	0
T9	65157	117	0	0
T10	2406	10	0	0
T11	12903	10	0	0
T12	77089	209	0	0
T13	483313	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	215266	0	0
T1	71494	227	0	0
T2	7267	119	0	0
T3	457977	579	0	0
T7	428497	18	0	0
T8	85456	151	0	0
T9	65157	117	0	0
T10	2406	10	0	0
T11	12903	10	0	0
T12	77089	209	0	0
T13	483313	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	3084778	0	0
T1	71494	1657	0	0
T2	7267	114	0	0
T3	457977	1961	0	0
T7	428497	8007	0	0
T8	85456	1133	0	0
T9	65157	903	0	0
T10	2406	10	0	0
T11	12903	71	0	0
T12	77089	1624	0	0
T13	483313	2690	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	215266	0	0
T1	71494	227	0	0
T2	7267	119	0	0
T3	457977	579	0	0
T7	428497	18	0	0
T8	85456	151	0	0
T9	65157	117	0	0
T10	2406	10	0	0
T11	12903	10	0	0
T12	77089	209	0	0
T13	483313	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	215266	0	0
T1	71494	227	0	0
T2	7267	119	0	0
T3	457977	579	0	0
T7	428497	18	0	0
T8	85456	151	0	0
T9	65157	117	0	0
T10	2406	10	0	0
T11	12903	10	0	0
T12	77089	209	0	0
T13	483313	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	632792	0	0
T1	71494	304	0	0
T2	7267	125	0	0
T3	457977	1265	0	0
T7	428497	768	0	0
T8	85456	152	0	0
T9	65157	167	0	0
T10	2406	11	0	0
T11	12903	12	0	0
T12	77089	256	0	0
T13	483313	583	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	215266	0	0
T1	71494	227	0	0
T2	7267	119	0	0
T3	457977	579	0	0
T7	428497	18	0	0
T8	85456	151	0	0
T9	65157	117	0	0
T10	2406	10	0	0
T11	12903	10	0	0
T12	77089	209	0	0
T13	483313	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	218301	0	0
GntImpliesValid_A	442939900	218301	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	218301	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	2949600	0	0
ReadyAndValidImplyGrant_A	442939900	218301	0	0
ReqAndReadyImplyGrant_A	442939900	218301	0	0
ReqImpliesValid_A	442939900	589009	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	218301	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218301	0	0
T1	71494	202	0	0
T2	7267	119	0	0
T3	457977	963	0	0
T7	428497	13	0	0
T8	85456	139	0	0
T9	65157	120	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	230	0	0
T13	483313	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218301	0	0
T1	71494	202	0	0
T2	7267	119	0	0
T3	457977	963	0	0
T7	428497	13	0	0
T8	85456	139	0	0
T9	65157	120	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	230	0	0
T13	483313	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218301	0	0
T1	71494	202	0	0
T2	7267	119	0	0
T3	457977	963	0	0
T7	428497	13	0	0
T8	85456	139	0	0
T9	65157	120	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	230	0	0
T13	483313	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2949600	0	0
T1	71494	1309	0	0
T2	7267	108	0	0
T3	457977	3103	0	0
T7	428497	4506	0	0
T8	85456	1015	0	0
T9	65157	932	0	0
T10	2406	12	0	0
T11	12903	84	0	0
T12	77089	1738	0	0
T13	483313	6096	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218301	0	0
T1	71494	202	0	0
T2	7267	119	0	0
T3	457977	963	0	0
T7	428497	13	0	0
T8	85456	139	0	0
T9	65157	120	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	230	0	0
T13	483313	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218301	0	0
T1	71494	202	0	0
T2	7267	119	0	0
T3	457977	963	0	0
T7	428497	13	0	0
T8	85456	139	0	0
T9	65157	120	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	230	0	0
T13	483313	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	589009	0	0
T1	71494	259	0	0
T2	7267	131	0	0
T3	457977	2393	0	0
T7	428497	13	0	0
T8	85456	143	0	0
T9	65157	174	0	0
T10	2406	11	0	0
T11	12903	13	0	0
T12	77089	337	0	0
T13	483313	333	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	218301	0	0
T1	71494	202	0	0
T2	7267	119	0	0
T3	457977	963	0	0
T7	428497	13	0	0
T8	85456	139	0	0
T9	65157	120	0	0
T10	2406	11	0	0
T11	12903	11	0	0
T12	77089	230	0	0
T13	483313	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	220102	0	0
GntImpliesValid_A	442939900	220102	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	220102	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	2963843	0	0
ReadyAndValidImplyGrant_A	442939900	220102	0	0
ReqAndReadyImplyGrant_A	442939900	220102	0	0
ReqImpliesValid_A	442939900	559453	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	220102	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	220102	0	0
T1	71494	244	0	0
T2	7267	130	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	157	0	0
T9	65157	111	0	0
T10	2406	18	0	0
T11	12903	12	0	0
T12	77089	237	0	0
T13	483313	12	0	0
T14	0	2448	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	220102	0	0
T1	71494	244	0	0
T2	7267	130	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	157	0	0
T9	65157	111	0	0
T10	2406	18	0	0
T11	12903	12	0	0
T12	77089	237	0	0
T13	483313	12	0	0
T14	0	2448	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	220102	0	0
T1	71494	244	0	0
T2	7267	130	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	157	0	0
T9	65157	111	0	0
T10	2406	18	0	0
T11	12903	12	0	0
T12	77089	237	0	0
T13	483313	12	0	0
T14	0	2448	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2963843	0	0
T1	71494	1867	0	0
T2	7267	127	0	0
T3	457977	1	0	0
T7	428497	4088	0	0
T8	85456	1218	0	0
T9	65157	892	0	0
T10	2406	17	0	0
T11	12903	105	0	0
T12	77089	1897	0	0
T13	483313	5062	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	220102	0	0
T1	71494	244	0	0
T2	7267	130	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	157	0	0
T9	65157	111	0	0
T10	2406	18	0	0
T11	12903	12	0	0
T12	77089	237	0	0
T13	483313	12	0	0
T14	0	2448	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	220102	0	0
T1	71494	244	0	0
T2	7267	130	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	157	0	0
T9	65157	111	0	0
T10	2406	18	0	0
T11	12903	12	0	0
T12	77089	237	0	0
T13	483313	12	0	0
T14	0	2448	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	559453	0	0
T1	71494	341	0	0
T2	7267	134	0	0
T3	457977	0	0	0
T7	428497	74	0	0
T8	85456	172	0	0
T9	65157	137	0	0
T10	2406	20	0	0
T11	12903	19	0	0
T12	77089	286	0	0
T13	483313	587	0	0
T14	0	3550	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	220102	0	0
T1	71494	244	0	0
T2	7267	130	0	0
T3	457977	0	0	0
T7	428497	12	0	0
T8	85456	157	0	0
T9	65157	111	0	0
T10	2406	18	0	0
T11	12903	12	0	0
T12	77089	237	0	0
T13	483313	12	0	0
T14	0	2448	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	213652	0	0
GntImpliesValid_A	442939900	213652	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	213652	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	2954130	0	0
ReadyAndValidImplyGrant_A	442939900	213652	0	0
ReqAndReadyImplyGrant_A	442939900	213652	0	0
ReqImpliesValid_A	442939900	531586	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	213652	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213652	0	0
T1	71494	211	0	0
T2	7267	100	0	0
T3	457977	0	0	0
T7	428497	8	0	0
T8	85456	142	0	0
T9	65157	127	0	0
T10	2406	16	0	0
T11	12903	12	0	0
T12	77089	226	0	0
T13	483313	13	0	0
T14	0	944	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213652	0	0
T1	71494	211	0	0
T2	7267	100	0	0
T3	457977	0	0	0
T7	428497	8	0	0
T8	85456	142	0	0
T9	65157	127	0	0
T10	2406	16	0	0
T11	12903	12	0	0
T12	77089	226	0	0
T13	483313	13	0	0
T14	0	944	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213652	0	0
T1	71494	211	0	0
T2	7267	100	0	0
T3	457977	0	0	0
T7	428497	8	0	0
T8	85456	142	0	0
T9	65157	127	0	0
T10	2406	16	0	0
T11	12903	12	0	0
T12	77089	226	0	0
T13	483313	13	0	0
T14	0	944	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2954130	0	0
T1	71494	1635	0	0
T2	7267	100	0	0
T3	457977	1	0	0
T7	428497	4009	0	0
T8	85456	1073	0	0
T9	65157	1000	0	0
T10	2406	17	0	0
T11	12903	95	0	0
T12	77089	1694	0	0
T13	483313	4590	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213652	0	0
T1	71494	211	0	0
T2	7267	100	0	0
T3	457977	0	0	0
T7	428497	8	0	0
T8	85456	142	0	0
T9	65157	127	0	0
T10	2406	16	0	0
T11	12903	12	0	0
T12	77089	226	0	0
T13	483313	13	0	0
T14	0	944	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213652	0	0
T1	71494	211	0	0
T2	7267	100	0	0
T3	457977	0	0	0
T7	428497	8	0	0
T8	85456	142	0	0
T9	65157	127	0	0
T10	2406	16	0	0
T11	12903	12	0	0
T12	77089	226	0	0
T13	483313	13	0	0
T14	0	944	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	531586	0	0
T1	71494	350	0	0
T2	7267	101	0	0
T3	457977	0	0	0
T7	428497	8	0	0
T8	85456	186	0	0
T9	65157	163	0	0
T10	2406	16	0	0
T11	12903	12	0	0
T12	77089	270	0	0
T13	483313	726	0	0
T14	0	962	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	213652	0	0
T1	71494	211	0	0
T2	7267	100	0	0
T3	457977	0	0	0
T7	428497	8	0	0
T8	85456	142	0	0
T9	65157	127	0	0
T10	2406	16	0	0
T11	12903	12	0	0
T12	77089	226	0	0
T13	483313	13	0	0
T14	0	944	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	228955	0	0
GntImpliesValid_A	442939900	228955	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	228955	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	3014702	0	0
ReadyAndValidImplyGrant_A	442939900	228955	0	0
ReqAndReadyImplyGrant_A	442939900	228955	0	0
ReqImpliesValid_A	442939900	578734	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	228955	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	228955	0	0
T1	71494	237	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	161	0	0
T9	65157	193	0	0
T10	2406	14	0	0
T11	12903	9	0	0
T12	77089	248	0	0
T13	483313	16	0	0
T14	0	1163	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	228955	0	0
T1	71494	237	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	161	0	0
T9	65157	193	0	0
T10	2406	14	0	0
T11	12903	9	0	0
T12	77089	248	0	0
T13	483313	16	0	0
T14	0	1163	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	228955	0	0
T1	71494	237	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	161	0	0
T9	65157	193	0	0
T10	2406	14	0	0
T11	12903	9	0	0
T12	77089	248	0	0
T13	483313	16	0	0
T14	0	1163	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	3014702	0	0
T1	71494	1749	0	0
T2	7267	108	0	0
T3	457977	1	0	0
T7	428497	4335	0	0
T8	85456	1197	0	0
T9	65157	1579	0	0
T10	2406	15	0	0
T11	12903	60	0	0
T12	77089	1740	0	0
T13	483313	5008	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	228955	0	0
T1	71494	237	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	161	0	0
T9	65157	193	0	0
T10	2406	14	0	0
T11	12903	9	0	0
T12	77089	248	0	0
T13	483313	16	0	0
T14	0	1163	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	228955	0	0
T1	71494	237	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	161	0	0
T9	65157	193	0	0
T10	2406	14	0	0
T11	12903	9	0	0
T12	77089	248	0	0
T13	483313	16	0	0
T14	0	1163	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	578734	0	0
T1	71494	369	0	0
T2	7267	125	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	191	0	0
T9	65157	251	0	0
T10	2406	14	0	0
T11	12903	20	0	0
T12	77089	388	0	0
T13	483313	16	0	0
T14	0	1199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	228955	0	0
T1	71494	237	0	0
T2	7267	116	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	161	0	0
T9	65157	193	0	0
T10	2406	14	0	0
T11	12903	9	0	0
T12	77089	248	0	0
T13	483313	16	0	0
T14	0	1163	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	206164	0	0
GntImpliesValid_A	442939900	206164	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	206164	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	3016488	0	0
ReadyAndValidImplyGrant_A	442939900	206164	0	0
ReqAndReadyImplyGrant_A	442939900	206164	0	0
ReqImpliesValid_A	442939900	547404	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	206164	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	206164	0	0
T1	71494	232	0	0
T2	7267	135	0	0
T3	457977	0	0	0
T7	428497	13	0	0
T8	85456	143	0	0
T9	65157	110	0	0
T10	2406	6	0	0
T11	12903	15	0	0
T12	77089	212	0	0
T13	483313	15	0	0
T14	0	1482	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	206164	0	0
T1	71494	232	0	0
T2	7267	135	0	0
T3	457977	0	0	0
T7	428497	13	0	0
T8	85456	143	0	0
T9	65157	110	0	0
T10	2406	6	0	0
T11	12903	15	0	0
T12	77089	212	0	0
T13	483313	15	0	0
T14	0	1482	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	206164	0	0
T1	71494	232	0	0
T2	7267	135	0	0
T3	457977	0	0	0
T7	428497	13	0	0
T8	85456	143	0	0
T9	65157	110	0	0
T10	2406	6	0	0
T11	12903	15	0	0
T12	77089	212	0	0
T13	483313	15	0	0
T14	0	1482	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	3016488	0	0
T1	71494	1649	0	0
T2	7267	128	0	0
T3	457977	1	0	0
T7	428497	4147	0	0
T8	85456	1075	0	0
T9	65157	783	0	0
T10	2406	7	0	0
T11	12903	107	0	0
T12	77089	1539	0	0
T13	483313	5577	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	206164	0	0
T1	71494	232	0	0
T2	7267	135	0	0
T3	457977	0	0	0
T7	428497	13	0	0
T8	85456	143	0	0
T9	65157	110	0	0
T10	2406	6	0	0
T11	12903	15	0	0
T12	77089	212	0	0
T13	483313	15	0	0
T14	0	1482	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	206164	0	0
T1	71494	232	0	0
T2	7267	135	0	0
T3	457977	0	0	0
T7	428497	13	0	0
T8	85456	143	0	0
T9	65157	110	0	0
T10	2406	6	0	0
T11	12903	15	0	0
T12	77089	212	0	0
T13	483313	15	0	0
T14	0	1482	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	547404	0	0
T1	71494	373	0	0
T2	7267	143	0	0
T3	457977	0	0	0
T7	428497	470	0	0
T8	85456	176	0	0
T9	65157	161	0	0
T10	2406	6	0	0
T11	12903	15	0	0
T12	77089	271	0	0
T13	483313	15	0	0
T14	0	1571	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	206164	0	0
T1	71494	232	0	0
T2	7267	135	0	0
T3	457977	0	0	0
T7	428497	13	0	0
T8	85456	143	0	0
T9	65157	110	0	0
T10	2406	6	0	0
T11	12903	15	0	0
T12	77089	212	0	0
T13	483313	15	0	0
T14	0	1482	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	207023	0	0
GntImpliesValid_A	442939900	207023	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	207023	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	2957433	0	0
ReadyAndValidImplyGrant_A	442939900	207023	0	0
ReqAndReadyImplyGrant_A	442939900	207023	0	0
ReqImpliesValid_A	442939900	513657	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	207023	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207023	0	0
T1	71494	240	0	0
T2	7267	109	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	142	0	0
T9	65157	125	0	0
T10	2406	17	0	0
T11	12903	14	0	0
T12	77089	227	0	0
T13	483313	15	0	0
T14	0	1639	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207023	0	0
T1	71494	240	0	0
T2	7267	109	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	142	0	0
T9	65157	125	0	0
T10	2406	17	0	0
T11	12903	14	0	0
T12	77089	227	0	0
T13	483313	15	0	0
T14	0	1639	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207023	0	0
T1	71494	240	0	0
T2	7267	109	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	142	0	0
T9	65157	125	0	0
T10	2406	17	0	0
T11	12903	14	0	0
T12	77089	227	0	0
T13	483313	15	0	0
T14	0	1639	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2957433	0	0
T1	71494	1687	0	0
T2	7267	104	0	0
T3	457977	1	0	0
T7	428497	1663	0	0
T8	85456	1061	0	0
T9	65157	865	0	0
T10	2406	18	0	0
T11	12903	100	0	0
T12	77089	1769	0	0
T13	483313	5824	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207023	0	0
T1	71494	240	0	0
T2	7267	109	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	142	0	0
T9	65157	125	0	0
T10	2406	17	0	0
T11	12903	14	0	0
T12	77089	227	0	0
T13	483313	15	0	0
T14	0	1639	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207023	0	0
T1	71494	240	0	0
T2	7267	109	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	142	0	0
T9	65157	125	0	0
T10	2406	17	0	0
T11	12903	14	0	0
T12	77089	227	0	0
T13	483313	15	0	0
T14	0	1639	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	513657	0	0
T1	71494	302	0	0
T2	7267	115	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	153	0	0
T9	65157	190	0	0
T10	2406	17	0	0
T11	12903	23	0	0
T12	77089	353	0	0
T13	483313	34	0	0
T14	0	2007	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	207023	0	0
T1	71494	240	0	0
T2	7267	109	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	142	0	0
T9	65157	125	0	0
T10	2406	17	0	0
T11	12903	14	0	0
T12	77089	227	0	0
T13	483313	15	0	0
T14	0	1639	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	212330	0	0
GntImpliesValid_A	442939900	212330	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	212330	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	2968472	0	0
ReadyAndValidImplyGrant_A	442939900	212330	0	0
ReqAndReadyImplyGrant_A	442939900	212330	0	0
ReqImpliesValid_A	442939900	603681	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	212330	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	212330	0	0
T1	71494	227	0	0
T2	7267	140	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	159	0	0
T9	65157	116	0	0
T10	2406	21	0	0
T11	12903	14	0	0
T12	77089	214	0	0
T13	483313	18	0	0
T14	0	1020	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	212330	0	0
T1	71494	227	0	0
T2	7267	140	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	159	0	0
T9	65157	116	0	0
T10	2406	21	0	0
T11	12903	14	0	0
T12	77089	214	0	0
T13	483313	18	0	0
T14	0	1020	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	212330	0	0
T1	71494	227	0	0
T2	7267	140	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	159	0	0
T9	65157	116	0	0
T10	2406	21	0	0
T11	12903	14	0	0
T12	77089	214	0	0
T13	483313	18	0	0
T14	0	1020	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2968472	0	0
T1	71494	1696	0	0
T2	7267	132	0	0
T3	457977	1	0	0
T7	428497	4103	0	0
T8	85456	1198	0	0
T9	65157	839	0	0
T10	2406	20	0	0
T11	12903	72	0	0
T12	77089	1653	0	0
T13	483313	5630	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	212330	0	0
T1	71494	227	0	0
T2	7267	140	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	159	0	0
T9	65157	116	0	0
T10	2406	21	0	0
T11	12903	14	0	0
T12	77089	214	0	0
T13	483313	18	0	0
T14	0	1020	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	212330	0	0
T1	71494	227	0	0
T2	7267	140	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	159	0	0
T9	65157	116	0	0
T10	2406	21	0	0
T11	12903	14	0	0
T12	77089	214	0	0
T13	483313	18	0	0
T14	0	1020	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	603681	0	0
T1	71494	293	0	0
T2	7267	149	0	0
T3	457977	0	0	0
T7	428497	579	0	0
T8	85456	175	0	0
T9	65157	156	0	0
T10	2406	23	0	0
T11	12903	32	0	0
T12	77089	350	0	0
T13	483313	184	0	0
T14	0	1057	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	212330	0	0
T1	71494	227	0	0
T2	7267	140	0	0
T3	457977	0	0	0
T7	428497	11	0	0
T8	85456	159	0	0
T9	65157	116	0	0
T10	2406	21	0	0
T11	12903	14	0	0
T12	77089	214	0	0
T13	483313	18	0	0
T14	0	1020	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	225613	0	0
GntImpliesValid_A	442939900	225613	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	225613	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	3041978	0	0
ReadyAndValidImplyGrant_A	442939900	225613	0	0
ReqAndReadyImplyGrant_A	442939900	225613	0	0
ReqImpliesValid_A	442939900	610488	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	225613	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	225613	0	0
T1	71494	240	0	0
T2	7267	154	0	0
T3	457977	508	0	0
T7	428497	15	0	0
T8	85456	177	0	0
T9	65157	118	0	0
T10	2406	10	0	0
T11	12903	9	0	0
T12	77089	246	0	0
T13	483313	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	225613	0	0
T1	71494	240	0	0
T2	7267	154	0	0
T3	457977	508	0	0
T7	428497	15	0	0
T8	85456	177	0	0
T9	65157	118	0	0
T10	2406	10	0	0
T11	12903	9	0	0
T12	77089	246	0	0
T13	483313	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	225613	0	0
T1	71494	240	0	0
T2	7267	154	0	0
T3	457977	508	0	0
T7	428497	15	0	0
T8	85456	177	0	0
T9	65157	118	0	0
T10	2406	10	0	0
T11	12903	9	0	0
T12	77089	246	0	0
T13	483313	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	3041978	0	0
T1	71494	1729	0	0
T2	7267	148	0	0
T3	457977	1709	0	0
T7	428497	5335	0	0
T8	85456	1378	0	0
T9	65157	847	0	0
T10	2406	11	0	0
T11	12903	71	0	0
T12	77089	1777	0	0
T13	483313	4658	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	225613	0	0
T1	71494	240	0	0
T2	7267	154	0	0
T3	457977	508	0	0
T7	428497	15	0	0
T8	85456	177	0	0
T9	65157	118	0	0
T10	2406	10	0	0
T11	12903	9	0	0
T12	77089	246	0	0
T13	483313	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	225613	0	0
T1	71494	240	0	0
T2	7267	154	0	0
T3	457977	508	0	0
T7	428497	15	0	0
T8	85456	177	0	0
T9	65157	118	0	0
T10	2406	10	0	0
T11	12903	9	0	0
T12	77089	246	0	0
T13	483313	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	610488	0	0
T1	71494	333	0	0
T2	7267	161	0	0
T3	457977	1229	0	0
T7	428497	353	0	0
T8	85456	184	0	0
T9	65157	138	0	0
T10	2406	10	0	0
T11	12903	20	0	0
T12	77089	409	0	0
T13	483313	170	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	225613	0	0
T1	71494	240	0	0
T2	7267	154	0	0
T3	457977	508	0	0
T7	428497	15	0	0
T8	85456	177	0	0
T9	65157	118	0	0
T10	2406	10	0	0
T11	12903	9	0	0
T12	77089	246	0	0
T13	483313	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	214839	0	0
GntImpliesValid_A	442939900	214839	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	214839	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	3025460	0	0
ReadyAndValidImplyGrant_A	442939900	214839	0	0
ReqAndReadyImplyGrant_A	442939900	214839	0	0
ReqImpliesValid_A	442939900	614658	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	0	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	214839	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	214839	0	0
T1	71494	221	0	0
T2	7267	123	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	152	0	0
T9	65157	104	0	0
T10	2406	17	0	0
T11	12903	10	0	0
T12	77089	219	0	0
T13	483313	15	0	0
T14	0	1524	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	214839	0	0
T1	71494	221	0	0
T2	7267	123	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	152	0	0
T9	65157	104	0	0
T10	2406	17	0	0
T11	12903	10	0	0
T12	77089	219	0	0
T13	483313	15	0	0
T14	0	1524	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	214839	0	0
T1	71494	221	0	0
T2	7267	123	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	152	0	0
T9	65157	104	0	0
T10	2406	17	0	0
T11	12903	10	0	0
T12	77089	219	0	0
T13	483313	15	0	0
T14	0	1524	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	3025460	0	0
T1	71494	1597	0	0
T2	7267	119	0	0
T3	457977	1	0	0
T7	428497	1704	0	0
T8	85456	1223	0	0
T9	65157	834	0	0
T10	2406	18	0	0
T11	12903	55	0	0
T12	77089	1624	0	0
T13	483313	5428	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	214839	0	0
T1	71494	221	0	0
T2	7267	123	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	152	0	0
T9	65157	104	0	0
T10	2406	17	0	0
T11	12903	10	0	0
T12	77089	219	0	0
T13	483313	15	0	0
T14	0	1524	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	214839	0	0
T1	71494	221	0	0
T2	7267	123	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	152	0	0
T9	65157	104	0	0
T10	2406	17	0	0
T11	12903	10	0	0
T12	77089	219	0	0
T13	483313	15	0	0
T14	0	1524	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	614658	0	0
T1	71494	317	0	0
T2	7267	128	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	173	0	0
T9	65157	140	0	0
T10	2406	17	0	0
T11	12903	17	0	0
T12	77089	308	0	0
T13	483313	15	0	0
T14	0	1637	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	214839	0	0
T1	71494	221	0	0
T2	7267	123	0	0
T3	457977	0	0	0
T7	428497	5	0	0
T8	85456	152	0	0
T9	65157	104	0	0
T10	2406	17	0	0
T11	12903	10	0	0
T12	77089	219	0	0
T13	483313	15	0	0
T14	0	1524	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	871499	0	0
GntImpliesValid_A	442939900	871499	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	871499	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	11435824	0	0
ReadyAndValidImplyGrant_A	442939900	871499	0	0
ReqAndReadyImplyGrant_A	442939900	871499	0	0
ReqImpliesValid_A	442939900	2375162	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	17898	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	871499	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	871499	0	0
T1	71494	872	0	0
T2	7267	461	0	0
T3	457977	1584	0	0
T7	428497	59	0	0
T8	85456	914	0	0
T9	65157	421	0	0
T10	2406	33	0	0
T11	12903	42	0	0
T12	77089	973	0	0
T13	483313	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	871499	0	0
T1	71494	872	0	0
T2	7267	461	0	0
T3	457977	1584	0	0
T7	428497	59	0	0
T8	85456	914	0	0
T9	65157	421	0	0
T10	2406	33	0	0
T11	12903	42	0	0
T12	77089	973	0	0
T13	483313	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	871499	0	0
T1	71494	872	0	0
T2	7267	461	0	0
T3	457977	1584	0	0
T7	428497	59	0	0
T8	85456	914	0	0
T9	65157	421	0	0
T10	2406	33	0	0
T11	12903	42	0	0
T12	77089	973	0	0
T13	483313	53	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	11435824	0	0
T1	71494	5568	0	0
T2	7267	1	0	0
T3	457977	4660	0	0
T7	428497	18304	0	0
T8	85456	4200	0	0
T9	65157	2750	0	0
T10	2406	1	0	0
T11	12903	288	0	0
T12	77089	6201	0	0
T13	483313	17268	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	871499	0	0
T1	71494	872	0	0
T2	7267	461	0	0
T3	457977	1584	0	0
T7	428497	59	0	0
T8	85456	914	0	0
T9	65157	421	0	0
T10	2406	33	0	0
T11	12903	42	0	0
T12	77089	973	0	0
T13	483313	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	871499	0	0
T1	71494	872	0	0
T2	7267	461	0	0
T3	457977	1584	0	0
T7	428497	59	0	0
T8	85456	914	0	0
T9	65157	421	0	0
T10	2406	33	0	0
T11	12903	42	0	0
T12	77089	973	0	0
T13	483313	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	2375162	0	0
T1	71494	1416	0	0
T2	7267	461	0	0
T3	457977	2728	0	0
T7	428497	2423	0	0
T8	85456	1790	0	0
T9	65157	553	0	0
T10	2406	33	0	0
T11	12903	44	0	0
T12	77089	1727	0	0
T13	483313	349	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	17898	0	900
T1	71494	1	0	1
T2	7267	5	0	1
T3	457977	15	0	1
T7	428497	0	0	1
T8	85456	22	0	1
T9	65157	0	0	1
T10	2406	0	0	1
T11	12903	0	0	1
T12	77089	0	0	1
T13	483313	0	0	1
T14	0	337	0	0
T15	0	14	0	0
T16	0	1	0	0
T18	0	590	0	0
T19	0	343	0	0
T20	0	7	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	871499	0	0
T1	71494	872	0	0
T2	7267	461	0	0
T3	457977	1584	0	0
T7	428497	59	0	0
T8	85456	914	0	0
T9	65157	421	0	0
T10	2406	33	0	0
T11	12903	42	0	0
T12	77089	973	0	0
T13	483313	53	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442939900	442810221	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442939900	855965	0	0
GntImpliesValid_A	442939900	855965	0	0
GrantKnown_A	442939900	442810221	0	0
IdxKnown_A	442939900	442810221	0	0
IndexIsCorrect_A	442939900	855965	0	0
LockArbDecision_A	442939900	0	0	0
NoReadyValidNoGrant_A	442939900	372588896	0	0
ReadyAndValidImplyGrant_A	442939900	855965	0	0
ReqAndReadyImplyGrant_A	442939900	855965	0	0
ReqImpliesValid_A	442939900	13380099	0	0
ReqStaysHighUntilGranted0_M	442939900	0	0	0
RoundRobin_A	442939900	28659	0	900
ValidKnown_A	442939900	442810221	0	0
gen_data_port_assertion.DataFlow_A	442939900	855965	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	855965	0	0
T1	71494	864	0	0
T2	7267	459	0	0
T3	457977	823	0	0
T7	428497	47	0	0
T8	85456	731	0	0
T9	65157	446	0	0
T10	2406	42	0	0
T11	12903	64	0	0
T12	77089	918	0	0
T13	483313	51	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	855965	0	0
T1	71494	864	0	0
T2	7267	459	0	0
T3	457977	823	0	0
T7	428497	47	0	0
T8	85456	731	0	0
T9	65157	446	0	0
T10	2406	42	0	0
T11	12903	64	0	0
T12	77089	918	0	0
T13	483313	51	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	855965	0	0
T1	71494	864	0	0
T2	7267	459	0	0
T3	457977	823	0	0
T7	428497	47	0	0
T8	85456	731	0	0
T9	65157	446	0	0
T10	2406	42	0	0
T11	12903	64	0	0
T12	77089	918	0	0
T13	483313	51	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	372588896	0	0
T1	71494	59177	0	0
T2	7267	1	0	0
T3	457977	381216	0	0
T7	428497	409694	0	0
T8	85456	70302	0	0
T9	65157	56285	0	0
T10	2406	1	0	0
T11	12903	11160	0	0
T12	77089	63381	0	0
T13	483313	457565	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	855965	0	0
T1	71494	864	0	0
T2	7267	459	0	0
T3	457977	823	0	0
T7	428497	47	0	0
T8	85456	731	0	0
T9	65157	446	0	0
T10	2406	42	0	0
T11	12903	64	0	0
T12	77089	918	0	0
T13	483313	51	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	855965	0	0
T1	71494	864	0	0
T2	7267	459	0	0
T3	457977	823	0	0
T7	428497	47	0	0
T8	85456	731	0	0
T9	65157	446	0	0
T10	2406	42	0	0
T11	12903	64	0	0
T12	77089	918	0	0
T13	483313	51	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	13380099	0	0
T1	71494	6626	0	0
T2	7267	459	0	0
T3	457977	3763	0	0
T7	428497	17970	0	0
T8	85456	5615	0	0
T9	65157	3402	0	0
T10	2406	42	0	0
T11	12903	575	0	0
T12	77089	7591	0	0
T13	483313	16733	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	28659	0	900
T2	7267	14	0	1
T3	457977	0	0	1
T7	428497	0	0	1
T8	85456	1	0	1
T9	65157	0	0	1
T10	2406	0	0	1
T11	12903	0	0	1
T12	77089	1	0	1
T13	483313	0	0	1
T14	117848	1209	0	1
T15	0	11	0	0
T16	0	4	0	0
T17	0	2	0	0
T18	0	513	0	0
T19	0	36	0	0
T20	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	442810221	0	0
T1	71494	71477	0	0
T2	7267	7242	0	0
T3	457977	457971	0	0
T7	428497	428477	0	0
T8	85456	84966	0	0
T9	65157	65112	0	0
T10	2406	2338	0	0
T11	12903	12842	0	0
T12	77089	77045	0	0
T13	483313	483240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442939900	855965	0	0
T1	71494	864	0	0
T2	7267	459	0	0
T3	457977	823	0	0
T7	428497	47	0	0
T8	85456	731	0	0
T9	65157	446	0	0
T10	2406	42	0	0
T11	12903	64	0	0
T12	77089	918	0	0
T13	483313	51	0	0