Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1376555	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

219057

1

T1

28

T2

16

T3

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	542127	1			T1	59		T2	50		T3	62
values[0x0]	511773	1			T1	60		T2	41		T3	68
values[0x1]	541712	1			T1	58		T2	51		T3	83

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1064656	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

530956

1

T1

59

T2

40

T3

72

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24315	1			T1	9		T3	4		T7	7
valid_sources[0x01]	25179	1			T2	2		T3	6		T7	9
valid_sources[0x02]	25450	1			T2	3		T3	3		T7	19
valid_sources[0x03]	24241	1			T2	5		T3	6		T7	26
valid_sources[0x04]	25107	1			T2	2		T3	1		T7	30
valid_sources[0x05]	25356	1			T1	9		T2	1		T3	3
valid_sources[0x06]	25034	1			T2	3		T3	5		T7	20
valid_sources[0x07]	25652	1			T3	3		T7	11		T8	44
valid_sources[0x08]	25820	1			T2	3		T3	2		T7	19
valid_sources[0x09]	24559	1			T2	1		T3	3		T7	27
valid_sources[0x0a]	24309	1			T2	1		T3	4		T7	31
valid_sources[0x0b]	24653	1			T2	1		T3	3		T7	29
valid_sources[0x0c]	25120	1			T1	2		T2	3		T3	2
valid_sources[0x0d]	24510	1			T2	2		T3	4		T7	9
valid_sources[0x0e]	25172	1			T3	3		T7	19		T8	33
valid_sources[0x0f]	25285	1			T2	1		T3	3		T7	13
valid_sources[0x10]	25802	1			T2	1		T3	3		T7	7
valid_sources[0x11]	25184	1			T1	21		T2	5		T3	5
valid_sources[0x12]	24833	1			T2	4		T3	2		T7	12
valid_sources[0x13]	24639	1			T2	6		T3	3		T7	25
valid_sources[0x14]	24955	1			T2	7		T3	3		T7	10
valid_sources[0x15]	24513	1			T2	2		T3	2		T7	34
valid_sources[0x16]	25315	1			T1	24		T2	1		T3	2
valid_sources[0x17]	26160	1			T1	5		T2	4		T3	3
valid_sources[0x18]	25789	1			T3	4		T7	21		T8	24
valid_sources[0x19]	24404	1			T3	2		T7	16		T8	42
valid_sources[0x1a]	23767	1			T2	2		T3	3		T7	16
valid_sources[0x1b]	24334	1			T2	2		T3	4		T7	8
valid_sources[0x1c]	25070	1			T2	3		T3	2		T7	24
valid_sources[0x1d]	25775	1			T1	7		T2	1		T3	2
valid_sources[0x1e]	25036	1			T2	2		T3	1		T7	9
valid_sources[0x1f]	25141	1			T2	1		T3	2		T7	16
valid_sources[0x20]	24364	1			T1	3		T2	5		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22827

1

T1

4

T3

2

T7

5

values[0x0]

all_enables

biggest_size

172992

1

T1

23

T2

14

T3

20

values[0x1]

all_enables

biggest_size

23238

1

T1

1

T2

2

T3

8

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1388718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

225535

1

T1

22

T2

29

T3

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	552718	1			T1	44		T2	59		T3	79
values[0x0]	508563	1			T1	48		T2	59		T3	75
values[0x1]	552972	1			T1	47		T2	52		T3	93

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1064614	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

549639

1

T1

50

T2

66

T3

80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25210	1			T3	3		T7	14		T8	51
valid_sources[0x01]	25172	1			T1	5		T2	5		T3	6
valid_sources[0x02]	25551	1			T1	2		T2	4		T3	3
valid_sources[0x03]	24873	1			T1	2		T2	1		T3	6
valid_sources[0x04]	25239	1			T1	4		T2	8		T3	3
valid_sources[0x05]	26088	1			T1	2		T2	1		T7	29
valid_sources[0x06]	25110	1			T1	1		T3	3		T7	14
valid_sources[0x07]	25334	1			T1	7		T3	1		T7	17
valid_sources[0x08]	25352	1			T1	4		T2	3		T3	9
valid_sources[0x09]	26207	1			T2	5		T3	1		T7	15
valid_sources[0x0a]	25231	1			T1	3		T2	1		T3	2
valid_sources[0x0b]	24653	1			T1	5		T2	1		T3	3
valid_sources[0x0c]	24680	1			T1	2		T2	2		T3	1
valid_sources[0x0d]	24831	1			T1	3		T2	2		T3	4
valid_sources[0x0e]	25554	1			T1	2		T2	1		T3	5
valid_sources[0x0f]	25212	1			T1	2		T2	5		T3	2
valid_sources[0x10]	25199	1			T1	2		T2	6		T3	2
valid_sources[0x11]	24755	1			T1	1		T2	2		T3	4
valid_sources[0x12]	25497	1			T1	3		T2	5		T3	2
valid_sources[0x13]	26026	1			T1	1		T2	2		T3	6
valid_sources[0x14]	24994	1			T1	1		T2	6		T3	8
valid_sources[0x15]	25373	1			T1	1		T2	3		T3	3
valid_sources[0x16]	25343	1			T1	4		T2	2		T3	3
valid_sources[0x17]	25540	1			T1	1		T2	5		T3	3
valid_sources[0x18]	25330	1			T1	1		T3	6		T7	10
valid_sources[0x19]	25010	1			T1	2		T2	3		T3	4
valid_sources[0x1a]	24899	1			T1	1		T2	1		T3	2
valid_sources[0x1b]	25430	1			T2	4		T3	5		T7	19
valid_sources[0x1c]	24845	1			T1	4		T3	3		T7	20
valid_sources[0x1d]	25021	1			T1	1		T2	5		T3	5
valid_sources[0x1e]	25304	1			T1	3		T2	4		T3	5
valid_sources[0x1f]	24387	1			T1	1		T2	5		T3	5
valid_sources[0x20]	25281	1			T3	7		T7	24		T8	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23547

1

T1

2

T2

3

T3

5

values[0x0]

all_enables

biggest_size

178209

1

T1

17

T2

22

T3

22

values[0x1]

all_enables

biggest_size

23779

1

T1

3

T2

4

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1386522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

220572

1

T1

15

T2

23

T3

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	545255	1			T1	49		T2	44		T3	84
values[0x0]	515890	1			T1	49		T2	46		T3	91
values[0x1]	545949	1			T1	68		T2	47		T3	112

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1071280	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

535814

1

T1

52

T2

44

T3

102

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24697	1			T1	2		T3	4		T7	7
valid_sources[0x01]	25011	1			T1	2		T2	4		T3	7
valid_sources[0x02]	25393	1			T1	3		T2	12		T3	3
valid_sources[0x03]	25482	1			T1	1		T2	6		T3	4
valid_sources[0x04]	25281	1			T1	1		T2	1		T3	8
valid_sources[0x05]	25389	1			T1	5		T2	2		T3	4
valid_sources[0x06]	24805	1			T1	4		T3	6		T7	18
valid_sources[0x07]	24668	1			T3	5		T7	18		T8	7
valid_sources[0x08]	26015	1			T1	1		T3	8		T7	15
valid_sources[0x09]	24697	1			T1	2		T2	5		T3	5
valid_sources[0x0a]	25357	1			T1	2		T3	3		T7	12
valid_sources[0x0b]	25629	1			T1	3		T3	4		T7	16
valid_sources[0x0c]	24904	1			T2	4		T3	3		T7	13
valid_sources[0x0d]	24951	1			T1	1		T2	9		T3	3
valid_sources[0x0e]	25252	1			T1	1		T3	3		T7	8
valid_sources[0x0f]	26003	1			T1	3		T3	2		T7	21
valid_sources[0x10]	25472	1			T1	2		T3	4		T7	29
valid_sources[0x11]	24814	1			T1	6		T2	3		T3	3
valid_sources[0x12]	25438	1			T1	4		T3	4		T7	19
valid_sources[0x13]	25710	1			T1	1		T2	4		T3	4
valid_sources[0x14]	24672	1			T1	1		T2	4		T3	2
valid_sources[0x15]	24836	1			T1	5		T2	2		T3	4
valid_sources[0x16]	25145	1			T1	3		T3	6		T7	13
valid_sources[0x17]	24808	1			T1	1		T2	1		T3	7
valid_sources[0x18]	25351	1			T1	5		T3	6		T7	10
valid_sources[0x19]	25302	1			T1	3		T2	4		T3	4
valid_sources[0x1a]	24792	1			T1	4		T3	6		T7	27
valid_sources[0x1b]	25207	1			T1	3		T2	9		T3	2
valid_sources[0x1c]	23881	1			T1	1		T3	4		T7	25
valid_sources[0x1d]	25271	1			T1	5		T3	9		T7	10
valid_sources[0x1e]	24483	1			T1	3		T2	1		T3	3
valid_sources[0x1f]	24581	1			T1	4		T3	2		T7	16
valid_sources[0x20]	24522	1			T1	2		T3	8		T7	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23246

1

T1

2

T2

4

T3

8

values[0x0]

all_enables

biggest_size

174062

1

T1

12

T2

18

T3

31

values[0x1]

all_enables

biggest_size

23264

1

T1

1

T2

1

T3

9