Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7065243	0	0
GntImpliesValid_A	2147483647	7065243	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7065243	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	441914085	0	0
ReadyAndValidImplyGrant_A	2147483647	7065243	0	0
ReqAndReadyImplyGrant_A	2147483647	7065243	0	0
ReqImpliesValid_A	2147483647	30699912	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	36169	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7065243	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12139104	12138864	0	0
T2	9640272	9639048	0	0
T3	9312144	9311256	0	0
T4	2886432	2884776	0	0
T7	485064	484464	0	0
T8	9130176	9130008	0	0
T9	109176	107664	0	0
T10	913392	905880	0	0
T11	1644264	1642536	0	0
T12	2339400	2330112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7065243	0	0
T1	12139104	482	0	0
T2	9640272	449	0	0
T3	9312144	747	0	0
T4	2886432	11446	0	0
T7	485064	1583	0	0
T8	9130176	6800	0	0
T9	109176	1843	0	0
T10	913392	4610	0	0
T11	1644264	39341	0	0
T12	2339400	45152	0	0
T13	0	263	0	0
T14	0	101	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7065243	0	0
T1	12139104	482	0	0
T2	9640272	449	0	0
T3	9312144	747	0	0
T4	2886432	11446	0	0
T7	485064	1583	0	0
T8	9130176	6800	0	0
T9	109176	1843	0	0
T10	913392	4610	0	0
T11	1644264	39341	0	0
T12	2339400	45152	0	0
T13	0	263	0	0
T14	0	101	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12139104	12138864	0	0
T2	9640272	9639048	0	0
T3	9312144	9311256	0	0
T4	2886432	2884776	0	0
T7	485064	484464	0	0
T8	9130176	9130008	0	0
T9	109176	107664	0	0
T10	913392	905880	0	0
T11	1644264	1642536	0	0
T12	2339400	2330112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12139104	12138864	0	0
T2	9640272	9639048	0	0
T3	9312144	9311256	0	0
T4	2886432	2884776	0	0
T7	485064	484464	0	0
T8	9130176	9130008	0	0
T9	109176	107664	0	0
T10	913392	905880	0	0
T11	1644264	1642536	0	0
T12	2339400	2330112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7065243	0	0
T1	12139104	482	0	0
T2	9640272	449	0	0
T3	9312144	747	0	0
T4	2886432	11446	0	0
T7	485064	1583	0	0
T8	9130176	6800	0	0
T9	109176	1843	0	0
T10	913392	4610	0	0
T11	1644264	39341	0	0
T12	2339400	45152	0	0
T13	0	263	0	0
T14	0	101	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	441914085	0	0
T1	12139104	635104	0	0
T2	9640272	509720	0	0
T3	9312144	328312	0	0
T4	2886432	132183	0	0
T7	485064	27762	0	0
T8	9130176	3071351	0	0
T9	109176	3271	0	0
T10	913392	55940	0	0
T11	1644264	32586	0	0
T12	2339400	47453	0	0
T13	0	163	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7065243	0	0
T1	12139104	482	0	0
T2	9640272	449	0	0
T3	9312144	747	0	0
T4	2886432	11446	0	0
T7	485064	1583	0	0
T8	9130176	6800	0	0
T9	109176	1843	0	0
T10	913392	4610	0	0
T11	1644264	39341	0	0
T12	2339400	45152	0	0
T13	0	263	0	0
T14	0	101	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7065243	0	0
T1	12139104	482	0	0
T2	9640272	449	0	0
T3	9312144	747	0	0
T4	2886432	11446	0	0
T7	485064	1583	0	0
T8	9130176	6800	0	0
T9	109176	1843	0	0
T10	913392	4610	0	0
T11	1644264	39341	0	0
T12	2339400	45152	0	0
T13	0	263	0	0
T14	0	101	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	30699912	0	0
T1	12139104	15228	0	0
T2	9640272	29123	0	0
T3	9312144	3062	0	0
T4	2886432	95291	0	0
T7	485064	3257	0	0
T8	9130176	533499	0	0
T9	109176	2203	0	0
T10	913392	12613	0	0
T11	1644264	54911	0	0
T12	2339400	70681	0	0
T13	0	316	0	0
T14	0	120	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36169	0	21600
T4	240536	15	0	2
T9	9098	6	0	2
T10	76116	0	0	2
T11	137022	793	0	2
T12	194950	1102	0	2
T13	3690	0	0	2
T14	551022	0	0	2
T15	34848	36	0	2
T16	0	2	0	0
T17	0	173	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	11	0	0
T21	0	15	0	0
T22	0	9	0	0
T23	18206	0	0	2
T24	5624	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12139104	12138864	0	0
T2	9640272	9639048	0	0
T3	9312144	9311256	0	0
T4	2886432	2884776	0	0
T7	485064	484464	0	0
T8	9130176	9130008	0	0
T9	109176	107664	0	0
T10	913392	905880	0	0
T11	1644264	1642536	0	0
T12	2339400	2330112	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7065243	0	0
T1	12139104	482	0	0
T2	9640272	449	0	0
T3	9312144	747	0	0
T4	2886432	11446	0	0
T7	485064	1583	0	0
T8	9130176	6800	0	0
T9	109176	1843	0	0
T10	913392	4610	0	0
T11	1644264	39341	0	0
T12	2339400	45152	0	0
T13	0	263	0	0
T14	0	101	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	798541	0	0
GntImpliesValid_A	411143232	798541	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	798541	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	10812375	0	0
ReadyAndValidImplyGrant_A	411143232	798541	0	0
ReqAndReadyImplyGrant_A	411143232	798541	0	0
ReqImpliesValid_A	411143232	2261648	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	798541	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	798541	0	0
T1	505796	58	0	0
T2	401678	55	0	0
T3	388006	66	0	0
T4	120268	1534	0	0
T7	20211	182	0	0
T8	380424	731	0	0
T9	4549	207	0	0
T10	38058	433	0	0
T11	68511	3830	0	0
T12	97475	6405	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	798541	0	0
T1	505796	58	0	0
T2	401678	55	0	0
T3	388006	66	0	0
T4	120268	1534	0	0
T7	20211	182	0	0
T8	380424	731	0	0
T9	4549	207	0	0
T10	38058	433	0	0
T11	68511	3830	0	0
T12	97475	6405	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	798541	0	0
T1	505796	58	0	0
T2	401678	55	0	0
T3	388006	66	0	0
T4	120268	1534	0	0
T7	20211	182	0	0
T8	380424	731	0	0
T9	4549	207	0	0
T10	38058	433	0	0
T11	68511	3830	0	0
T12	97475	6405	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	10812375	0	0
T1	505796	21326	0	0
T2	401678	14262	0	0
T3	388006	287	0	0
T4	120268	7228	0	0
T7	20211	1265	0	0
T8	380424	241172	0	0
T9	4549	160	0	0
T10	38058	2915	0	0
T11	68511	2926	0	0
T12	97475	3593	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	798541	0	0
T1	505796	58	0	0
T2	401678	55	0	0
T3	388006	66	0	0
T4	120268	1534	0	0
T7	20211	182	0	0
T8	380424	731	0	0
T9	4549	207	0	0
T10	38058	433	0	0
T11	68511	3830	0	0
T12	97475	6405	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	798541	0	0
T1	505796	58	0	0
T2	401678	55	0	0
T3	388006	66	0	0
T4	120268	1534	0	0
T7	20211	182	0	0
T8	380424	731	0	0
T9	4549	207	0	0
T10	38058	433	0	0
T11	68511	3830	0	0
T12	97475	6405	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2261648	0	0
T1	505796	1016	0	0
T2	401678	1634	0	0
T3	388006	103	0	0
T4	120268	8259	0	0
T7	20211	302	0	0
T8	380424	20378	0	0
T9	4549	255	0	0
T10	38058	618	0	0
T11	68511	4738	0	0
T12	97475	9223	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	798541	0	0
T1	505796	58	0	0
T2	401678	55	0	0
T3	388006	66	0	0
T4	120268	1534	0	0
T7	20211	182	0	0
T8	380424	731	0	0
T9	4549	207	0	0
T10	38058	433	0	0
T11	68511	3830	0	0
T12	97475	6405	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	784357	0	0
GntImpliesValid_A	411143232	784357	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	784357	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	10569682	0	0
ReadyAndValidImplyGrant_A	411143232	784357	0	0
ReqAndReadyImplyGrant_A	411143232	784357	0	0
ReqImpliesValid_A	411143232	2190424	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	784357	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	784357	0	0
T1	505796	48	0	0
T2	401678	58	0	0
T3	388006	55	0	0
T4	120268	827	0	0
T7	20211	182	0	0
T8	380424	776	0	0
T9	4549	203	0	0
T10	38058	505	0	0
T11	68511	3790	0	0
T12	97475	4190	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	784357	0	0
T1	505796	48	0	0
T2	401678	58	0	0
T3	388006	55	0	0
T4	120268	827	0	0
T7	20211	182	0	0
T8	380424	776	0	0
T9	4549	203	0	0
T10	38058	505	0	0
T11	68511	3790	0	0
T12	97475	4190	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	784357	0	0
T1	505796	48	0	0
T2	401678	58	0	0
T3	388006	55	0	0
T4	120268	827	0	0
T7	20211	182	0	0
T8	380424	776	0	0
T9	4549	203	0	0
T10	38058	505	0	0
T11	68511	3790	0	0
T12	97475	4190	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	10569682	0	0
T1	505796	18833	0	0
T2	401678	20456	0	0
T3	388006	207	0	0
T4	120268	5956	0	0
T7	20211	1249	0	0
T8	380424	255226	0	0
T9	4549	165	0	0
T10	38058	3584	0	0
T11	68511	2914	0	0
T12	97475	3375	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	784357	0	0
T1	505796	48	0	0
T2	401678	58	0	0
T3	388006	55	0	0
T4	120268	827	0	0
T7	20211	182	0	0
T8	380424	776	0	0
T9	4549	203	0	0
T10	38058	505	0	0
T11	68511	3790	0	0
T12	97475	4190	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	784357	0	0
T1	505796	48	0	0
T2	401678	58	0	0
T3	388006	55	0	0
T4	120268	827	0	0
T7	20211	182	0	0
T8	380424	776	0	0
T9	4549	203	0	0
T10	38058	505	0	0
T11	68511	3790	0	0
T12	97475	4190	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2190424	0	0
T1	505796	184	0	0
T2	401678	1922	0	0
T3	388006	74	0	0
T4	120268	1341	0	0
T7	20211	257	0	0
T8	380424	25847	0	0
T9	4549	242	0	0
T10	38058	865	0	0
T11	68511	4670	0	0
T12	97475	5011	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	784357	0	0
T1	505796	48	0	0
T2	401678	58	0	0
T3	388006	55	0	0
T4	120268	827	0	0
T7	20211	182	0	0
T8	380424	776	0	0
T9	4549	203	0	0
T10	38058	505	0	0
T11	68511	3790	0	0
T12	97475	4190	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	205178	0	0
GntImpliesValid_A	411143232	205178	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	205178	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2745414	0	0
ReadyAndValidImplyGrant_A	411143232	205178	0	0
ReqAndReadyImplyGrant_A	411143232	205178	0	0
ReqImpliesValid_A	411143232	557677	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	205178	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	205178	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	1034	0	0
T7	20211	49	0	0
T8	380424	185	0	0
T9	4549	38	0	0
T10	38058	79	0	0
T11	68511	1011	0	0
T12	97475	1274	0	0
T13	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	205178	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	1034	0	0
T7	20211	49	0	0
T8	380424	185	0	0
T9	4549	38	0	0
T10	38058	79	0	0
T11	68511	1011	0	0
T12	97475	1274	0	0
T13	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	205178	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	1034	0	0
T7	20211	49	0	0
T8	380424	185	0	0
T9	4549	38	0	0
T10	38058	79	0	0
T11	68511	1011	0	0
T12	97475	1274	0	0
T13	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2745414	0	0
T1	505796	5831	0	0
T2	401678	3549	0	0
T3	388006	1	0	0
T4	120268	2656	0	0
T7	20211	343	0	0
T8	380424	66441	0	0
T9	4549	34	0	0
T10	38058	643	0	0
T11	68511	594	0	0
T12	97475	1200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	205178	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	1034	0	0
T7	20211	49	0	0
T8	380424	185	0	0
T9	4549	38	0	0
T10	38058	79	0	0
T11	68511	1011	0	0
T12	97475	1274	0	0
T13	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	205178	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	1034	0	0
T7	20211	49	0	0
T8	380424	185	0	0
T9	4549	38	0	0
T10	38058	79	0	0
T11	68511	1011	0	0
T12	97475	1274	0	0
T13	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	557677	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	9067	0	0
T7	20211	54	0	0
T8	380424	2800	0	0
T9	4549	43	0	0
T10	38058	79	0	0
T11	68511	1432	0	0
T12	97475	1354	0	0
T13	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	205178	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	1034	0	0
T7	20211	49	0	0
T8	380424	185	0	0
T9	4549	38	0	0
T10	38058	79	0	0
T11	68511	1011	0	0
T12	97475	1274	0	0
T13	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	196230	0	0
GntImpliesValid_A	411143232	196230	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	196230	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2745518	0	0
ReadyAndValidImplyGrant_A	411143232	196230	0	0
ReqAndReadyImplyGrant_A	411143232	196230	0	0
ReqImpliesValid_A	411143232	497532	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	196230	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196230	0	0
T1	505796	20	0	0
T2	401678	13	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	42	0	0
T8	380424	184	0	0
T9	4549	61	0	0
T10	38058	67	0	0
T11	68511	1737	0	0
T12	97475	816	0	0
T13	0	12	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196230	0	0
T1	505796	20	0	0
T2	401678	13	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	42	0	0
T8	380424	184	0	0
T9	4549	61	0	0
T10	38058	67	0	0
T11	68511	1737	0	0
T12	97475	816	0	0
T13	0	12	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196230	0	0
T1	505796	20	0	0
T2	401678	13	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	42	0	0
T8	380424	184	0	0
T9	4549	61	0	0
T10	38058	67	0	0
T11	68511	1737	0	0
T12	97475	816	0	0
T13	0	12	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2745518	0	0
T1	505796	6253	0	0
T2	401678	3904	0	0
T3	388006	1	0	0
T4	120268	1	0	0
T7	20211	313	0	0
T8	380424	61532	0	0
T9	4549	56	0	0
T10	38058	465	0	0
T11	68511	1543	0	0
T12	97475	803	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196230	0	0
T1	505796	20	0	0
T2	401678	13	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	42	0	0
T8	380424	184	0	0
T9	4549	61	0	0
T10	38058	67	0	0
T11	68511	1737	0	0
T12	97475	816	0	0
T13	0	12	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196230	0	0
T1	505796	20	0	0
T2	401678	13	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	42	0	0
T8	380424	184	0	0
T9	4549	61	0	0
T10	38058	67	0	0
T11	68511	1737	0	0
T12	97475	816	0	0
T13	0	12	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	497532	0	0
T1	505796	20	0	0
T2	401678	75	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	52	0	0
T8	380424	3668	0	0
T9	4549	67	0	0
T10	38058	67	0	0
T11	68511	1935	0	0
T12	97475	835	0	0
T13	0	13	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196230	0	0
T1	505796	20	0	0
T2	401678	13	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	42	0	0
T8	380424	184	0	0
T9	4549	61	0	0
T10	38058	67	0	0
T11	68511	1737	0	0
T12	97475	816	0	0
T13	0	12	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	189051	0	0
GntImpliesValid_A	411143232	189051	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	189051	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	5640070	0	0
ReadyAndValidImplyGrant_A	411143232	189051	0	0
ReqAndReadyImplyGrant_A	411143232	189051	0	0
ReqImpliesValid_A	411143232	1085516	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	189051	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	189051	0	0
T1	505796	12	0	0
T2	401678	16	0	0
T3	388006	0	0	0
T4	120268	484	0	0
T7	20211	52	0	0
T8	380424	214	0	0
T9	4549	41	0	0
T10	38058	70	0	0
T11	68511	945	0	0
T12	97475	1198	0	0
T13	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	189051	0	0
T1	505796	12	0	0
T2	401678	16	0	0
T3	388006	0	0	0
T4	120268	484	0	0
T7	20211	52	0	0
T8	380424	214	0	0
T9	4549	41	0	0
T10	38058	70	0	0
T11	68511	945	0	0
T12	97475	1198	0	0
T13	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	189051	0	0
T1	505796	12	0	0
T2	401678	16	0	0
T3	388006	0	0	0
T4	120268	484	0	0
T7	20211	52	0	0
T8	380424	214	0	0
T9	4549	41	0	0
T10	38058	70	0	0
T11	68511	945	0	0
T12	97475	1198	0	0
T13	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	5640070	0	0
T1	505796	921	0	0
T2	401678	3568	0	0
T3	388006	0	0	0
T4	120268	2123	0	0
T7	20211	402	0	0
T8	380424	82249	0	0
T9	4549	476	0	0
T10	38058	309	0	0
T11	68511	4317	0	0
T12	97475	9304	0	0
T13	0	39	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	189051	0	0
T1	505796	12	0	0
T2	401678	16	0	0
T3	388006	0	0	0
T4	120268	484	0	0
T7	20211	52	0	0
T8	380424	214	0	0
T9	4549	41	0	0
T10	38058	70	0	0
T11	68511	945	0	0
T12	97475	1198	0	0
T13	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	189051	0	0
T1	505796	12	0	0
T2	401678	16	0	0
T3	388006	0	0	0
T4	120268	484	0	0
T7	20211	52	0	0
T8	380424	214	0	0
T9	4549	41	0	0
T10	38058	70	0	0
T11	68511	945	0	0
T12	97475	1198	0	0
T13	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	1085516	0	0
T1	505796	134	0	0
T2	401678	306	0	0
T3	388006	0	0	0
T4	120268	8522	0	0
T7	20211	56	0	0
T8	380424	4212	0	0
T9	4549	65	0	0
T10	38058	70	0	0
T11	68511	3913	0	0
T12	97475	7611	0	0
T13	0	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	189051	0	0
T1	505796	12	0	0
T2	401678	16	0	0
T3	388006	0	0	0
T4	120268	484	0	0
T7	20211	52	0	0
T8	380424	214	0	0
T9	4549	41	0	0
T10	38058	70	0	0
T11	68511	945	0	0
T12	97475	1198	0	0
T13	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	194772	0	0
GntImpliesValid_A	411143232	194772	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	194772	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	4659976	0	0
ReadyAndValidImplyGrant_A	411143232	194772	0	0
ReqAndReadyImplyGrant_A	411143232	194772	0	0
ReqImpliesValid_A	411143232	984324	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	194772	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	194772	0	0
T1	505796	15	0	0
T2	401678	12	0	0
T3	388006	500	0	0
T4	120268	984	0	0
T7	20211	46	0	0
T8	380424	194	0	0
T9	4549	54	0	0
T10	38058	582	0	0
T11	68511	583	0	0
T12	97475	1244	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	194772	0	0
T1	505796	15	0	0
T2	401678	12	0	0
T3	388006	500	0	0
T4	120268	984	0	0
T7	20211	46	0	0
T8	380424	194	0	0
T9	4549	54	0	0
T10	38058	582	0	0
T11	68511	583	0	0
T12	97475	1244	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	194772	0	0
T1	505796	15	0	0
T2	401678	12	0	0
T3	388006	500	0	0
T4	120268	984	0	0
T7	20211	46	0	0
T8	380424	194	0	0
T9	4549	54	0	0
T10	38058	582	0	0
T11	68511	583	0	0
T12	97475	1244	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	4659976	0	0
T1	505796	1344	0	0
T2	401678	2737	0	0
T3	388006	4341	0	0
T4	120268	2489	0	0
T7	20211	375	0	0
T8	380424	92936	0	0
T9	4549	270	0	0
T10	38058	2083	0	0
T11	68511	2334	0	0
T12	97475	5705	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	194772	0	0
T1	505796	15	0	0
T2	401678	12	0	0
T3	388006	500	0	0
T4	120268	984	0	0
T7	20211	46	0	0
T8	380424	194	0	0
T9	4549	54	0	0
T10	38058	582	0	0
T11	68511	583	0	0
T12	97475	1244	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	194772	0	0
T1	505796	15	0	0
T2	401678	12	0	0
T3	388006	500	0	0
T4	120268	984	0	0
T7	20211	46	0	0
T8	380424	194	0	0
T9	4549	54	0	0
T10	38058	582	0	0
T11	68511	583	0	0
T12	97475	1244	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	984324	0	0
T1	505796	15	0	0
T2	401678	12	0	0
T3	388006	2489	0	0
T4	120268	10577	0	0
T7	20211	54	0	0
T8	380424	4370	0	0
T9	4549	87	0	0
T10	38058	951	0	0
T11	68511	787	0	0
T12	97475	4048	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	194772	0	0
T1	505796	15	0	0
T2	401678	12	0	0
T3	388006	500	0	0
T4	120268	984	0	0
T7	20211	46	0	0
T8	380424	194	0	0
T9	4549	54	0	0
T10	38058	582	0	0
T11	68511	583	0	0
T12	97475	1244	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	190607	0	0
GntImpliesValid_A	411143232	190607	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	190607	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	4535999	0	0
ReadyAndValidImplyGrant_A	411143232	190607	0	0
ReqAndReadyImplyGrant_A	411143232	190607	0	0
ReqImpliesValid_A	411143232	900876	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	190607	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	190607	0	0
T1	505796	12	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	459	0	0
T7	20211	55	0	0
T8	380424	197	0	0
T9	4549	48	0	0
T10	38058	67	0	0
T11	68511	1676	0	0
T12	97475	1289	0	0
T13	0	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	190607	0	0
T1	505796	12	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	459	0	0
T7	20211	55	0	0
T8	380424	197	0	0
T9	4549	48	0	0
T10	38058	67	0	0
T11	68511	1676	0	0
T12	97475	1289	0	0
T13	0	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	190607	0	0
T1	505796	12	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	459	0	0
T7	20211	55	0	0
T8	380424	197	0	0
T9	4549	48	0	0
T10	38058	67	0	0
T11	68511	1676	0	0
T12	97475	1289	0	0
T13	0	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	4535999	0	0
T1	505796	886	0	0
T2	401678	4694	0	0
T3	388006	0	0	0
T4	120268	1396	0	0
T7	20211	476	0	0
T8	380424	403948	0	0
T9	4549	858	0	0
T10	38058	343	0	0
T11	68511	4712	0	0
T12	97475	4214	0	0
T13	0	60	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	190607	0	0
T1	505796	12	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	459	0	0
T7	20211	55	0	0
T8	380424	197	0	0
T9	4549	48	0	0
T10	38058	67	0	0
T11	68511	1676	0	0
T12	97475	1289	0	0
T13	0	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	190607	0	0
T1	505796	12	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	459	0	0
T7	20211	55	0	0
T8	380424	197	0	0
T9	4549	48	0	0
T10	38058	67	0	0
T11	68511	1676	0	0
T12	97475	1289	0	0
T13	0	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	900876	0	0
T1	505796	12	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	6149	0	0
T7	20211	74	0	0
T8	380424	59715	0	0
T9	4549	189	0	0
T10	38058	70	0	0
T11	68511	5227	0	0
T12	97475	4880	0	0
T13	0	37	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	190607	0	0
T1	505796	12	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	459	0	0
T7	20211	55	0	0
T8	380424	197	0	0
T9	4549	48	0	0
T10	38058	67	0	0
T11	68511	1676	0	0
T12	97475	1289	0	0
T13	0	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	192730	0	0
GntImpliesValid_A	411143232	192730	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	192730	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	5881133	0	0
ReadyAndValidImplyGrant_A	411143232	192730	0	0
ReqAndReadyImplyGrant_A	411143232	192730	0	0
ReqImpliesValid_A	411143232	1212337	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	192730	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192730	0	0
T1	505796	12	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	518	0	0
T7	20211	42	0	0
T8	380424	189	0	0
T9	4549	45	0	0
T10	38058	67	0	0
T11	68511	578	0	0
T12	97475	2270	0	0
T13	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192730	0	0
T1	505796	12	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	518	0	0
T7	20211	42	0	0
T8	380424	189	0	0
T9	4549	45	0	0
T10	38058	67	0	0
T11	68511	578	0	0
T12	97475	2270	0	0
T13	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192730	0	0
T1	505796	12	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	518	0	0
T7	20211	42	0	0
T8	380424	189	0	0
T9	4549	45	0	0
T10	38058	67	0	0
T11	68511	578	0	0
T12	97475	2270	0	0
T13	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	5881133	0	0
T1	505796	671	0	0
T2	401678	4608	0	0
T3	388006	0	0	0
T4	120268	1801	0	0
T7	20211	327	0	0
T8	380424	395127	0	0
T9	4549	567	0	0
T10	38058	926	0	0
T11	68511	3139	0	0
T12	97475	6130	0	0
T13	0	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192730	0	0
T1	505796	12	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	518	0	0
T7	20211	42	0	0
T8	380424	189	0	0
T9	4549	45	0	0
T10	38058	67	0	0
T11	68511	578	0	0
T12	97475	2270	0	0
T13	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192730	0	0
T1	505796	12	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	518	0	0
T7	20211	42	0	0
T8	380424	189	0	0
T9	4549	45	0	0
T10	38058	67	0	0
T11	68511	578	0	0
T12	97475	2270	0	0
T13	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	1212337	0	0
T1	505796	114	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	9070	0	0
T7	20211	51	0	0
T8	380424	79154	0	0
T9	4549	81	0	0
T10	38058	74	0	0
T11	68511	849	0	0
T12	97475	8415	0	0
T13	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192730	0	0
T1	505796	12	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	518	0	0
T7	20211	42	0	0
T8	380424	189	0	0
T9	4549	45	0	0
T10	38058	67	0	0
T11	68511	578	0	0
T12	97475	2270	0	0
T13	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	191569	0	0
GntImpliesValid_A	411143232	191569	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	191569	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2699111	0	0
ReadyAndValidImplyGrant_A	411143232	191569	0	0
ReqAndReadyImplyGrant_A	411143232	191569	0	0
ReqImpliesValid_A	411143232	479369	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	191569	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191569	0	0
T1	505796	13	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	446	0	0
T7	20211	49	0	0
T8	380424	183	0	0
T9	4549	50	0	0
T10	38058	61	0	0
T11	68511	617	0	0
T12	97475	796	0	0
T13	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191569	0	0
T1	505796	13	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	446	0	0
T7	20211	49	0	0
T8	380424	183	0	0
T9	4549	50	0	0
T10	38058	61	0	0
T11	68511	617	0	0
T12	97475	796	0	0
T13	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191569	0	0
T1	505796	13	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	446	0	0
T7	20211	49	0	0
T8	380424	183	0	0
T9	4549	50	0	0
T10	38058	61	0	0
T11	68511	617	0	0
T12	97475	796	0	0
T13	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2699111	0	0
T1	505796	3701	0	0
T2	401678	3574	0	0
T3	388006	1	0	0
T4	120268	712	0	0
T7	20211	416	0	0
T8	380424	55368	0	0
T9	4549	48	0	0
T10	38058	523	0	0
T11	68511	600	0	0
T12	97475	776	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191569	0	0
T1	505796	13	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	446	0	0
T7	20211	49	0	0
T8	380424	183	0	0
T9	4549	50	0	0
T10	38058	61	0	0
T11	68511	617	0	0
T12	97475	796	0	0
T13	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191569	0	0
T1	505796	13	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	446	0	0
T7	20211	49	0	0
T8	380424	183	0	0
T9	4549	50	0	0
T10	38058	61	0	0
T11	68511	617	0	0
T12	97475	796	0	0
T13	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	479369	0	0
T1	505796	13	0	0
T2	401678	211	0	0
T3	388006	0	0	0
T4	120268	4421	0	0
T7	20211	67	0	0
T8	380424	2481	0	0
T9	4549	53	0	0
T10	38058	64	0	0
T11	68511	638	0	0
T12	97475	822	0	0
T13	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191569	0	0
T1	505796	13	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	446	0	0
T7	20211	49	0	0
T8	380424	183	0	0
T9	4549	50	0	0
T10	38058	61	0	0
T11	68511	617	0	0
T12	97475	796	0	0
T13	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	188159	0	0
GntImpliesValid_A	411143232	188159	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	188159	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2674658	0	0
ReadyAndValidImplyGrant_A	411143232	188159	0	0
ReqAndReadyImplyGrant_A	411143232	188159	0	0
ReqImpliesValid_A	411143232	498115	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	188159	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188159	0	0
T1	505796	20	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	481	0	0
T7	20211	42	0	0
T8	380424	204	0	0
T9	4549	53	0	0
T10	38058	120	0	0
T11	68511	584	0	0
T12	97475	1812	0	0
T13	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188159	0	0
T1	505796	20	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	481	0	0
T7	20211	42	0	0
T8	380424	204	0	0
T9	4549	53	0	0
T10	38058	120	0	0
T11	68511	584	0	0
T12	97475	1812	0	0
T13	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188159	0	0
T1	505796	20	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	481	0	0
T7	20211	42	0	0
T8	380424	204	0	0
T9	4549	53	0	0
T10	38058	120	0	0
T11	68511	584	0	0
T12	97475	1812	0	0
T13	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2674658	0	0
T1	505796	5922	0	0
T2	401678	4327	0	0
T3	388006	1	0	0
T4	120268	1189	0	0
T7	20211	320	0	0
T8	380424	67996	0	0
T9	4549	48	0	0
T10	38058	762	0	0
T11	68511	568	0	0
T12	97475	1199	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188159	0	0
T1	505796	20	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	481	0	0
T7	20211	42	0	0
T8	380424	204	0	0
T9	4549	53	0	0
T10	38058	120	0	0
T11	68511	584	0	0
T12	97475	1812	0	0
T13	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188159	0	0
T1	505796	20	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	481	0	0
T7	20211	42	0	0
T8	380424	204	0	0
T9	4549	53	0	0
T10	38058	120	0	0
T11	68511	584	0	0
T12	97475	1812	0	0
T13	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	498115	0	0
T1	505796	55	0	0
T2	401678	511	0	0
T3	388006	0	0	0
T4	120268	4151	0	0
T7	20211	45	0	0
T8	380424	4978	0	0
T9	4549	59	0	0
T10	38058	318	0	0
T11	68511	604	0	0
T12	97475	2431	0	0
T13	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188159	0	0
T1	505796	20	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	481	0	0
T7	20211	42	0	0
T8	380424	204	0	0
T9	4549	53	0	0
T10	38058	120	0	0
T11	68511	584	0	0
T12	97475	1812	0	0
T13	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	192336	0	0
GntImpliesValid_A	411143232	192336	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	192336	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2802109	0	0
ReadyAndValidImplyGrant_A	411143232	192336	0	0
ReqAndReadyImplyGrant_A	411143232	192336	0	0
ReqImpliesValid_A	411143232	478233	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	192336	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192336	0	0
T1	505796	17	0	0
T2	401678	17	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	190	0	0
T9	4549	48	0	0
T10	38058	373	0	0
T11	68511	1100	0	0
T12	97475	1326	0	0
T13	0	10	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192336	0	0
T1	505796	17	0	0
T2	401678	17	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	190	0	0
T9	4549	48	0	0
T10	38058	373	0	0
T11	68511	1100	0	0
T12	97475	1326	0	0
T13	0	10	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192336	0	0
T1	505796	17	0	0
T2	401678	17	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	190	0	0
T9	4549	48	0	0
T10	38058	373	0	0
T11	68511	1100	0	0
T12	97475	1326	0	0
T13	0	10	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2802109	0	0
T1	505796	5926	0	0
T2	401678	5244	0	0
T3	388006	1	0	0
T4	120268	1	0	0
T7	20211	272	0	0
T8	380424	63471	0	0
T9	4549	48	0	0
T10	38058	2302	0	0
T11	68511	602	0	0
T12	97475	827	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192336	0	0
T1	505796	17	0	0
T2	401678	17	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	190	0	0
T9	4549	48	0	0
T10	38058	373	0	0
T11	68511	1100	0	0
T12	97475	1326	0	0
T13	0	10	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192336	0	0
T1	505796	17	0	0
T2	401678	17	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	190	0	0
T9	4549	48	0	0
T10	38058	373	0	0
T11	68511	1100	0	0
T12	97475	1326	0	0
T13	0	10	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	478233	0	0
T1	505796	798	0	0
T2	401678	1585	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	6261	0	0
T9	4549	49	0	0
T10	38058	1362	0	0
T11	68511	1602	0	0
T12	97475	1831	0	0
T13	0	11	0	0
T14	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	192336	0	0
T1	505796	17	0	0
T2	401678	17	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	190	0	0
T9	4549	48	0	0
T10	38058	373	0	0
T11	68511	1100	0	0
T12	97475	1326	0	0
T13	0	10	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	197072	0	0
GntImpliesValid_A	411143232	197072	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	197072	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2742319	0	0
ReadyAndValidImplyGrant_A	411143232	197072	0	0
ReqAndReadyImplyGrant_A	411143232	197072	0	0
ReqImpliesValid_A	411143232	498868	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	197072	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197072	0	0
T1	505796	11	0	0
T2	401678	6	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	52	0	0
T8	380424	185	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	1138	0	0
T12	97475	835	0	0
T13	0	17	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197072	0	0
T1	505796	11	0	0
T2	401678	6	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	52	0	0
T8	380424	185	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	1138	0	0
T12	97475	835	0	0
T13	0	17	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197072	0	0
T1	505796	11	0	0
T2	401678	6	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	52	0	0
T8	380424	185	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	1138	0	0
T12	97475	835	0	0
T13	0	17	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2742319	0	0
T1	505796	3708	0	0
T2	401678	1203	0	0
T3	388006	1	0	0
T4	120268	1	0	0
T7	20211	358	0	0
T8	380424	69132	0	0
T9	4549	48	0	0
T10	38058	468	0	0
T11	68511	711	0	0
T12	97475	815	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197072	0	0
T1	505796	11	0	0
T2	401678	6	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	52	0	0
T8	380424	185	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	1138	0	0
T12	97475	835	0	0
T13	0	17	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197072	0	0
T1	505796	11	0	0
T2	401678	6	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	52	0	0
T8	380424	185	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	1138	0	0
T12	97475	835	0	0
T13	0	17	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	498868	0	0
T1	505796	278	0	0
T2	401678	6	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	52	0	0
T8	380424	2405	0	0
T9	4549	49	0	0
T10	38058	61	0	0
T11	68511	1569	0	0
T12	97475	861	0	0
T13	0	17	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197072	0	0
T1	505796	11	0	0
T2	401678	6	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	52	0	0
T8	380424	185	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	1138	0	0
T12	97475	835	0	0
T13	0	17	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	201299	0	0
GntImpliesValid_A	411143232	201299	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	201299	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2786269	0	0
ReadyAndValidImplyGrant_A	411143232	201299	0	0
ReqAndReadyImplyGrant_A	411143232	201299	0	0
ReqImpliesValid_A	411143232	514396	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	201299	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201299	0	0
T1	505796	16	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	510	0	0
T7	20211	35	0	0
T8	380424	201	0	0
T9	4549	43	0	0
T10	38058	60	0	0
T11	68511	1571	0	0
T12	97475	753	0	0
T13	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201299	0	0
T1	505796	16	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	510	0	0
T7	20211	35	0	0
T8	380424	201	0	0
T9	4549	43	0	0
T10	38058	60	0	0
T11	68511	1571	0	0
T12	97475	753	0	0
T13	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201299	0	0
T1	505796	16	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	510	0	0
T7	20211	35	0	0
T8	380424	201	0	0
T9	4549	43	0	0
T10	38058	60	0	0
T11	68511	1571	0	0
T12	97475	753	0	0
T13	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2786269	0	0
T1	505796	6458	0	0
T2	401678	3717	0	0
T3	388006	1	0	0
T4	120268	1121	0	0
T7	20211	285	0	0
T8	380424	69937	0	0
T9	4549	41	0	0
T10	38058	422	0	0
T11	68511	673	0	0
T12	97475	735	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201299	0	0
T1	505796	16	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	510	0	0
T7	20211	35	0	0
T8	380424	201	0	0
T9	4549	43	0	0
T10	38058	60	0	0
T11	68511	1571	0	0
T12	97475	753	0	0
T13	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201299	0	0
T1	505796	16	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	510	0	0
T7	20211	35	0	0
T8	380424	201	0	0
T9	4549	43	0	0
T10	38058	60	0	0
T11	68511	1571	0	0
T12	97475	753	0	0
T13	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	514396	0	0
T1	505796	16	0	0
T2	401678	474	0	0
T3	388006	0	0	0
T4	120268	2095	0	0
T7	20211	40	0	0
T8	380424	3600	0	0
T9	4549	46	0	0
T10	38058	60	0	0
T11	68511	2473	0	0
T12	97475	777	0	0
T13	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201299	0	0
T1	505796	16	0	0
T2	401678	12	0	0
T3	388006	0	0	0
T4	120268	510	0	0
T7	20211	35	0	0
T8	380424	201	0	0
T9	4549	43	0	0
T10	38058	60	0	0
T11	68511	1571	0	0
T12	97475	753	0	0
T13	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	201058	0	0
GntImpliesValid_A	411143232	201058	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	201058	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2637314	0	0
ReadyAndValidImplyGrant_A	411143232	201058	0	0
ReqAndReadyImplyGrant_A	411143232	201058	0	0
ReqImpliesValid_A	411143232	526189	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	201058	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201058	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	176	0	0
T9	4549	55	0	0
T10	38058	65	0	0
T11	68511	657	0	0
T12	97475	808	0	0
T13	0	10	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201058	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	176	0	0
T9	4549	55	0	0
T10	38058	65	0	0
T11	68511	657	0	0
T12	97475	808	0	0
T13	0	10	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201058	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	176	0	0
T9	4549	55	0	0
T10	38058	65	0	0
T11	68511	657	0	0
T12	97475	808	0	0
T13	0	10	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2637314	0	0
T1	505796	4103	0	0
T2	401678	5472	0	0
T3	388006	1	0	0
T4	120268	1	0	0
T7	20211	301	0	0
T8	380424	54497	0	0
T9	4549	56	0	0
T10	38058	518	0	0
T11	68511	631	0	0
T12	97475	796	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201058	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	176	0	0
T9	4549	55	0	0
T10	38058	65	0	0
T11	68511	657	0	0
T12	97475	808	0	0
T13	0	10	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201058	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	176	0	0
T9	4549	55	0	0
T10	38058	65	0	0
T11	68511	657	0	0
T12	97475	808	0	0
T13	0	10	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	526189	0	0
T1	505796	258	0	0
T2	401678	1771	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	52	0	0
T8	380424	3631	0	0
T9	4549	55	0	0
T10	38058	73	0	0
T11	68511	687	0	0
T12	97475	826	0	0
T13	0	10	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	201058	0	0
T1	505796	15	0	0
T2	401678	14	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	176	0	0
T9	4549	55	0	0
T10	38058	65	0	0
T11	68511	657	0	0
T12	97475	808	0	0
T13	0	10	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	204666	0	0
GntImpliesValid_A	411143232	204666	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	204666	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2661051	0	0
ReadyAndValidImplyGrant_A	411143232	204666	0	0
ReqAndReadyImplyGrant_A	411143232	204666	0	0
ReqImpliesValid_A	411143232	516110	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	204666	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	204666	0	0
T1	505796	18	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	469	0	0
T7	20211	49	0	0
T8	380424	191	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	2623	0	0
T12	97475	1287	0	0
T13	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	204666	0	0
T1	505796	18	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	469	0	0
T7	20211	49	0	0
T8	380424	191	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	2623	0	0
T12	97475	1287	0	0
T13	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	204666	0	0
T1	505796	18	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	469	0	0
T7	20211	49	0	0
T8	380424	191	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	2623	0	0
T12	97475	1287	0	0
T13	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2661051	0	0
T1	505796	6324	0	0
T2	401678	3130	0	0
T3	388006	1	0	0
T4	120268	1164	0	0
T7	20211	389	0	0
T8	380424	66876	0	0
T9	4549	48	0	0
T10	38058	599	0	0
T11	68511	880	0	0
T12	97475	900	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	204666	0	0
T1	505796	18	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	469	0	0
T7	20211	49	0	0
T8	380424	191	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	2623	0	0
T12	97475	1287	0	0
T13	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	204666	0	0
T1	505796	18	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	469	0	0
T7	20211	49	0	0
T8	380424	191	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	2623	0	0
T12	97475	1287	0	0
T13	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	516110	0	0
T1	505796	358	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	3960	0	0
T7	20211	60	0	0
T8	380424	2383	0	0
T9	4549	49	0	0
T10	38058	61	0	0
T11	68511	4370	0	0
T12	97475	1680	0	0
T13	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	204666	0	0
T1	505796	18	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	469	0	0
T7	20211	49	0	0
T8	380424	191	0	0
T9	4549	48	0	0
T10	38058	61	0	0
T11	68511	2623	0	0
T12	97475	1287	0	0
T13	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	196926	0	0
GntImpliesValid_A	411143232	196926	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	196926	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2648599	0	0
ReadyAndValidImplyGrant_A	411143232	196926	0	0
ReqAndReadyImplyGrant_A	411143232	196926	0	0
ReqImpliesValid_A	411143232	507667	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	196926	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196926	0	0
T1	505796	11	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	32	0	0
T8	380424	180	0	0
T9	4549	63	0	0
T10	38058	64	0	0
T11	68511	1640	0	0
T12	97475	1807	0	0
T13	0	14	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196926	0	0
T1	505796	11	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	32	0	0
T8	380424	180	0	0
T9	4549	63	0	0
T10	38058	64	0	0
T11	68511	1640	0	0
T12	97475	1807	0	0
T13	0	14	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196926	0	0
T1	505796	11	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	32	0	0
T8	380424	180	0	0
T9	4549	63	0	0
T10	38058	64	0	0
T11	68511	1640	0	0
T12	97475	1807	0	0
T13	0	14	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2648599	0	0
T1	505796	4482	0	0
T2	401678	3064	0	0
T3	388006	1	0	0
T4	120268	1	0	0
T7	20211	251	0	0
T8	380424	56032	0	0
T9	4549	60	0	0
T10	38058	493	0	0
T11	68511	1449	0	0
T12	97475	1180	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196926	0	0
T1	505796	11	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	32	0	0
T8	380424	180	0	0
T9	4549	63	0	0
T10	38058	64	0	0
T11	68511	1640	0	0
T12	97475	1807	0	0
T13	0	14	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196926	0	0
T1	505796	11	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	32	0	0
T8	380424	180	0	0
T9	4549	63	0	0
T10	38058	64	0	0
T11	68511	1640	0	0
T12	97475	1807	0	0
T13	0	14	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	507667	0	0
T1	505796	11	0	0
T2	401678	564	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	36	0	0
T8	380424	3130	0	0
T9	4549	67	0	0
T10	38058	76	0	0
T11	68511	1835	0	0
T12	97475	2440	0	0
T13	0	15	0	0
T14	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	196926	0	0
T1	505796	11	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	32	0	0
T8	380424	180	0	0
T9	4549	63	0	0
T10	38058	64	0	0
T11	68511	1640	0	0
T12	97475	1807	0	0
T13	0	14	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	218770	0	0
GntImpliesValid_A	411143232	218770	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	218770	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2834809	0	0
ReadyAndValidImplyGrant_A	411143232	218770	0	0
ReqAndReadyImplyGrant_A	411143232	218770	0	0
ReqImpliesValid_A	411143232	566773	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	218770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	218770	0	0
T1	505796	18	0	0
T2	401678	15	0	0
T3	388006	0	0	0
T4	120268	476	0	0
T7	20211	63	0	0
T8	380424	209	0	0
T9	4549	55	0	0
T10	38058	69	0	0
T11	68511	1259	0	0
T12	97475	852	0	0
T13	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	218770	0	0
T1	505796	18	0	0
T2	401678	15	0	0
T3	388006	0	0	0
T4	120268	476	0	0
T7	20211	63	0	0
T8	380424	209	0	0
T9	4549	55	0	0
T10	38058	69	0	0
T11	68511	1259	0	0
T12	97475	852	0	0
T13	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	218770	0	0
T1	505796	18	0	0
T2	401678	15	0	0
T3	388006	0	0	0
T4	120268	476	0	0
T7	20211	63	0	0
T8	380424	209	0	0
T9	4549	55	0	0
T10	38058	69	0	0
T11	68511	1259	0	0
T12	97475	852	0	0
T13	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2834809	0	0
T1	505796	6271	0	0
T2	401678	3987	0	0
T3	388006	1	0	0
T4	120268	1085	0	0
T7	20211	563	0	0
T8	380424	67159	0	0
T9	4549	54	0	0
T10	38058	496	0	0
T11	68511	715	0	0
T12	97475	829	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	218770	0	0
T1	505796	18	0	0
T2	401678	15	0	0
T3	388006	0	0	0
T4	120268	476	0	0
T7	20211	63	0	0
T8	380424	209	0	0
T9	4549	55	0	0
T10	38058	69	0	0
T11	68511	1259	0	0
T12	97475	852	0	0
T13	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	218770	0	0
T1	505796	18	0	0
T2	401678	15	0	0
T3	388006	0	0	0
T4	120268	476	0	0
T7	20211	63	0	0
T8	380424	209	0	0
T9	4549	55	0	0
T10	38058	69	0	0
T11	68511	1259	0	0
T12	97475	852	0	0
T13	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	566773	0	0
T1	505796	235	0	0
T2	401678	316	0	0
T3	388006	0	0	0
T4	120268	4108	0	0
T7	20211	88	0	0
T8	380424	5183	0	0
T9	4549	57	0	0
T10	38058	74	0	0
T11	68511	1807	0	0
T12	97475	881	0	0
T13	0	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	218770	0	0
T1	505796	18	0	0
T2	401678	15	0	0
T3	388006	0	0	0
T4	120268	476	0	0
T7	20211	63	0	0
T8	380424	209	0	0
T9	4549	55	0	0
T10	38058	69	0	0
T11	68511	1259	0	0
T12	97475	852	0	0
T13	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	186150	0	0
GntImpliesValid_A	411143232	186150	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	186150	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2703784	0	0
ReadyAndValidImplyGrant_A	411143232	186150	0	0
ReqAndReadyImplyGrant_A	411143232	186150	0	0
ReqImpliesValid_A	411143232	453718	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	186150	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	186150	0	0
T1	505796	10	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	429	0	0
T7	20211	39	0	0
T8	380424	208	0	0
T9	4549	48	0	0
T10	38058	521	0	0
T11	68511	1578	0	0
T12	97475	1353	0	0
T13	0	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	186150	0	0
T1	505796	10	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	429	0	0
T7	20211	39	0	0
T8	380424	208	0	0
T9	4549	48	0	0
T10	38058	521	0	0
T11	68511	1578	0	0
T12	97475	1353	0	0
T13	0	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	186150	0	0
T1	505796	10	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	429	0	0
T7	20211	39	0	0
T8	380424	208	0	0
T9	4549	48	0	0
T10	38058	521	0	0
T11	68511	1578	0	0
T12	97475	1353	0	0
T13	0	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2703784	0	0
T1	505796	3138	0	0
T2	401678	3368	0	0
T3	388006	1	0	0
T4	120268	771	0	0
T7	20211	247	0	0
T8	380424	72082	0	0
T9	4549	46	0	0
T10	38058	2618	0	0
T11	68511	840	0	0
T12	97475	1133	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	186150	0	0
T1	505796	10	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	429	0	0
T7	20211	39	0	0
T8	380424	208	0	0
T9	4549	48	0	0
T10	38058	521	0	0
T11	68511	1578	0	0
T12	97475	1353	0	0
T13	0	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	186150	0	0
T1	505796	10	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	429	0	0
T7	20211	39	0	0
T8	380424	208	0	0
T9	4549	48	0	0
T10	38058	521	0	0
T11	68511	1578	0	0
T12	97475	1353	0	0
T13	0	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	453718	0	0
T1	505796	647	0	0
T2	401678	360	0	0
T3	388006	0	0	0
T4	120268	4015	0	0
T7	20211	60	0	0
T8	380424	4027	0	0
T9	4549	51	0	0
T10	38058	2927	0	0
T11	68511	2320	0	0
T12	97475	1579	0	0
T13	0	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	186150	0	0
T1	505796	10	0	0
T2	401678	8	0	0
T3	388006	0	0	0
T4	120268	429	0	0
T7	20211	39	0	0
T8	380424	208	0	0
T9	4549	48	0	0
T10	38058	521	0	0
T11	68511	1578	0	0
T12	97475	1353	0	0
T13	0	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	191273	0	0
GntImpliesValid_A	411143232	191273	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	191273	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2724888	0	0
ReadyAndValidImplyGrant_A	411143232	191273	0	0
ReqAndReadyImplyGrant_A	411143232	191273	0	0
ReqImpliesValid_A	411143232	514503	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	191273	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191273	0	0
T1	505796	8	0	0
T2	401678	9	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	192	0	0
T9	4549	48	0	0
T10	38058	112	0	0
T11	68511	640	0	0
T12	97475	844	0	0
T13	0	16	0	0
T14	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191273	0	0
T1	505796	8	0	0
T2	401678	9	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	192	0	0
T9	4549	48	0	0
T10	38058	112	0	0
T11	68511	640	0	0
T12	97475	844	0	0
T13	0	16	0	0
T14	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191273	0	0
T1	505796	8	0	0
T2	401678	9	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	192	0	0
T9	4549	48	0	0
T10	38058	112	0	0
T11	68511	640	0	0
T12	97475	844	0	0
T13	0	16	0	0
T14	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2724888	0	0
T1	505796	3282	0	0
T2	401678	2440	0	0
T3	388006	1	0	0
T4	120268	1	0	0
T7	20211	345	0	0
T8	380424	62517	0	0
T9	4549	48	0	0
T10	38058	855	0	0
T11	68511	627	0	0
T12	97475	828	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191273	0	0
T1	505796	8	0	0
T2	401678	9	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	192	0	0
T9	4549	48	0	0
T10	38058	112	0	0
T11	68511	640	0	0
T12	97475	844	0	0
T13	0	16	0	0
T14	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191273	0	0
T1	505796	8	0	0
T2	401678	9	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	192	0	0
T9	4549	48	0	0
T10	38058	112	0	0
T11	68511	640	0	0
T12	97475	844	0	0
T13	0	16	0	0
T14	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	514503	0	0
T1	505796	8	0	0
T2	401678	9	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	51	0	0
T8	380424	2926	0	0
T9	4549	49	0	0
T10	38058	228	0	0
T11	68511	657	0	0
T12	97475	866	0	0
T13	0	17	0	0
T14	0	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	191273	0	0
T1	505796	8	0	0
T2	401678	9	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	44	0	0
T8	380424	192	0	0
T9	4549	48	0	0
T10	38058	112	0	0
T11	68511	640	0	0
T12	97475	844	0	0
T13	0	16	0	0
T14	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	197827	0	0
GntImpliesValid_A	411143232	197827	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	197827	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2704950	0	0
ReadyAndValidImplyGrant_A	411143232	197827	0	0
ReqAndReadyImplyGrant_A	411143232	197827	0	0
ReqImpliesValid_A	411143232	521094	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	197827	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197827	0	0
T1	505796	14	0	0
T2	401678	11	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	35	0	0
T8	380424	166	0	0
T9	4549	49	0	0
T10	38058	66	0	0
T11	68511	1612	0	0
T12	97475	1339	0	0
T13	0	14	0	0
T14	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197827	0	0
T1	505796	14	0	0
T2	401678	11	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	35	0	0
T8	380424	166	0	0
T9	4549	49	0	0
T10	38058	66	0	0
T11	68511	1612	0	0
T12	97475	1339	0	0
T13	0	14	0	0
T14	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197827	0	0
T1	505796	14	0	0
T2	401678	11	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	35	0	0
T8	380424	166	0	0
T9	4549	49	0	0
T10	38058	66	0	0
T11	68511	1612	0	0
T12	97475	1339	0	0
T13	0	14	0	0
T14	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2704950	0	0
T1	505796	4313	0	0
T2	401678	4313	0	0
T3	388006	1	0	0
T4	120268	1	0	0
T7	20211	286	0	0
T8	380424	49221	0	0
T9	4549	48	0	0
T10	38058	482	0	0
T11	68511	639	0	0
T12	97475	1191	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197827	0	0
T1	505796	14	0	0
T2	401678	11	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	35	0	0
T8	380424	166	0	0
T9	4549	49	0	0
T10	38058	66	0	0
T11	68511	1612	0	0
T12	97475	1339	0	0
T13	0	14	0	0
T14	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197827	0	0
T1	505796	14	0	0
T2	401678	11	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	35	0	0
T8	380424	166	0	0
T9	4549	49	0	0
T10	38058	66	0	0
T11	68511	1612	0	0
T12	97475	1339	0	0
T13	0	14	0	0
T14	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	521094	0	0
T1	505796	14	0	0
T2	401678	347	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	54	0	0
T8	380424	4582	0	0
T9	4549	51	0	0
T10	38058	89	0	0
T11	68511	2589	0	0
T12	97475	1493	0	0
T13	0	15	0	0
T14	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	197827	0	0
T1	505796	14	0	0
T2	401678	11	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	35	0	0
T8	380424	166	0	0
T9	4549	49	0	0
T10	38058	66	0	0
T11	68511	1612	0	0
T12	97475	1339	0	0
T13	0	14	0	0
T14	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	188234	0	0
GntImpliesValid_A	411143232	188234	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	188234	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2769966	0	0
ReadyAndValidImplyGrant_A	411143232	188234	0	0
ReqAndReadyImplyGrant_A	411143232	188234	0	0
ReqImpliesValid_A	411143232	491224	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	188234	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188234	0	0
T1	505796	12	0	0
T2	401678	7	0	0
T3	388006	0	0	0
T4	120268	405	0	0
T7	20211	40	0	0
T8	380424	203	0	0
T9	4549	41	0	0
T10	38058	58	0	0
T11	68511	607	0	0
T12	97475	821	0	0
T13	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188234	0	0
T1	505796	12	0	0
T2	401678	7	0	0
T3	388006	0	0	0
T4	120268	405	0	0
T7	20211	40	0	0
T8	380424	203	0	0
T9	4549	41	0	0
T10	38058	58	0	0
T11	68511	607	0	0
T12	97475	821	0	0
T13	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188234	0	0
T1	505796	12	0	0
T2	401678	7	0	0
T3	388006	0	0	0
T4	120268	405	0	0
T7	20211	40	0	0
T8	380424	203	0	0
T9	4549	41	0	0
T10	38058	58	0	0
T11	68511	607	0	0
T12	97475	821	0	0
T13	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2769966	0	0
T1	505796	5817	0	0
T2	401678	1650	0	0
T3	388006	1	0	0
T4	120268	864	0	0
T7	20211	360	0	0
T8	380424	65717	0	0
T9	4549	42	0	0
T10	38058	456	0	0
T11	68511	587	0	0
T12	97475	803	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188234	0	0
T1	505796	12	0	0
T2	401678	7	0	0
T3	388006	0	0	0
T4	120268	405	0	0
T7	20211	40	0	0
T8	380424	203	0	0
T9	4549	41	0	0
T10	38058	58	0	0
T11	68511	607	0	0
T12	97475	821	0	0
T13	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188234	0	0
T1	505796	12	0	0
T2	401678	7	0	0
T3	388006	0	0	0
T4	120268	405	0	0
T7	20211	40	0	0
T8	380424	203	0	0
T9	4549	41	0	0
T10	38058	58	0	0
T11	68511	607	0	0
T12	97475	821	0	0
T13	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	491224	0	0
T1	505796	82	0	0
T2	401678	446	0	0
T3	388006	0	0	0
T4	120268	3592	0	0
T7	20211	47	0	0
T8	380424	4278	0	0
T9	4549	41	0	0
T10	38058	67	0	0
T11	68511	631	0	0
T12	97475	845	0	0
T13	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	188234	0	0
T1	505796	12	0	0
T2	401678	7	0	0
T3	388006	0	0	0
T4	120268	405	0	0
T7	20211	40	0	0
T8	380424	203	0	0
T9	4549	41	0	0
T10	38058	58	0	0
T11	68511	607	0	0
T12	97475	821	0	0
T13	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	195870	0	0
GntImpliesValid_A	411143232	195870	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	195870	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	2700468	0	0
ReadyAndValidImplyGrant_A	411143232	195870	0	0
ReqAndReadyImplyGrant_A	411143232	195870	0	0
ReqImpliesValid_A	411143232	539234	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	0	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	195870	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	195870	0	0
T1	505796	21	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	38	0	0
T8	380424	169	0	0
T9	4549	48	0	0
T10	38058	53	0	0
T11	68511	589	0	0
T12	97475	1243	0	0
T13	0	13	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	195870	0	0
T1	505796	21	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	38	0	0
T8	380424	169	0	0
T9	4549	48	0	0
T10	38058	53	0	0
T11	68511	589	0	0
T12	97475	1243	0	0
T13	0	13	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	195870	0	0
T1	505796	21	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	38	0	0
T8	380424	169	0	0
T9	4549	48	0	0
T10	38058	53	0	0
T11	68511	589	0	0
T12	97475	1243	0	0
T13	0	13	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2700468	0	0
T1	505796	5119	0	0
T2	401678	3662	0	0
T3	388006	1	0	0
T4	120268	1	0	0
T7	20211	243	0	0
T8	380424	60487	0	0
T9	4549	48	0	0
T10	38058	399	0	0
T11	68511	580	0	0
T12	97475	1110	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	195870	0	0
T1	505796	21	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	38	0	0
T8	380424	169	0	0
T9	4549	48	0	0
T10	38058	53	0	0
T11	68511	589	0	0
T12	97475	1243	0	0
T13	0	13	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	195870	0	0
T1	505796	21	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	38	0	0
T8	380424	169	0	0
T9	4549	48	0	0
T10	38058	53	0	0
T11	68511	589	0	0
T12	97475	1243	0	0
T13	0	13	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	539234	0	0
T1	505796	425	0	0
T2	401678	377	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	39	0	0
T8	380424	2869	0	0
T9	4549	49	0	0
T10	38058	59	0	0
T11	68511	602	0	0
T12	97475	1382	0	0
T13	0	13	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	195870	0	0
T1	505796	21	0	0
T2	401678	10	0	0
T3	388006	0	0	0
T4	120268	0	0	0
T7	20211	38	0	0
T8	380424	169	0	0
T9	4549	48	0	0
T10	38058	53	0	0
T11	68511	589	0	0
T12	97475	1243	0	0
T13	0	13	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	790983	0	0
GntImpliesValid_A	411143232	790983	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	790983	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	10134623	0	0
ReadyAndValidImplyGrant_A	411143232	790983	0	0
ReqAndReadyImplyGrant_A	411143232	790983	0	0
ReqImpliesValid_A	411143232	2073319	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	16355	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	790983	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	790983	0	0
T1	505796	55	0	0
T2	401678	56	0	0
T3	388006	63	0	0
T4	120268	852	0	0
T7	20211	175	0	0
T8	380424	745	0	0
T9	4549	219	0	0
T10	38058	534	0	0
T11	68511	4566	0	0
T12	97475	4939	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	790983	0	0
T1	505796	55	0	0
T2	401678	56	0	0
T3	388006	63	0	0
T4	120268	852	0	0
T7	20211	175	0	0
T8	380424	745	0	0
T9	4549	219	0	0
T10	38058	534	0	0
T11	68511	4566	0	0
T12	97475	4939	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	790983	0	0
T1	505796	55	0	0
T2	401678	56	0	0
T3	388006	63	0	0
T4	120268	852	0	0
T7	20211	175	0	0
T8	380424	745	0	0
T9	4549	219	0	0
T10	38058	534	0	0
T11	68511	4566	0	0
T12	97475	4939	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	10134623	0	0
T1	505796	18587	0	0
T2	401678	19769	0	0
T3	388006	212	0	0
T4	120268	5446	0	0
T7	20211	1209	0	0
T8	380424	237648	0	0
T9	4549	1	0	0
T10	38058	3282	0	0
T11	68511	4	0	0
T12	97475	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	790983	0	0
T1	505796	55	0	0
T2	401678	56	0	0
T3	388006	63	0	0
T4	120268	852	0	0
T7	20211	175	0	0
T8	380424	745	0	0
T9	4549	219	0	0
T10	38058	534	0	0
T11	68511	4566	0	0
T12	97475	4939	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	790983	0	0
T1	505796	55	0	0
T2	401678	56	0	0
T3	388006	63	0	0
T4	120268	852	0	0
T7	20211	175	0	0
T8	380424	745	0	0
T9	4549	219	0	0
T10	38058	534	0	0
T11	68511	4566	0	0
T12	97475	4939	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	2073319	0	0
T1	505796	569	0	0
T2	401678	283	0	0
T3	388006	88	0	0
T4	120268	1369	0	0
T7	20211	245	0	0
T8	380424	29142	0	0
T9	4549	219	0	0
T10	38058	909	0	0
T11	68511	4566	0	0
T12	97475	4939	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	16355	0	900
T4	120268	0	0	1
T9	4549	3	0	1
T10	38058	0	0	1
T11	68511	327	0	1
T12	97475	113	0	1
T13	1845	0	0	1
T14	275511	0	0	1
T15	17424	17	0	1
T16	0	1	0	0
T17	0	31	0	0
T19	0	1	0	0
T20	0	11	0	0
T21	0	7	0	0
T22	0	4	0	0
T23	9103	0	0	1
T24	2812	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	790983	0	0
T1	505796	55	0	0
T2	401678	56	0	0
T3	388006	63	0	0
T4	120268	852	0	0
T7	20211	175	0	0
T8	380424	745	0	0
T9	4549	219	0	0
T10	38058	534	0	0
T11	68511	4566	0	0
T12	97475	4939	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411143232	411026140	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	411143232	771585	0	0
GntImpliesValid_A	411143232	771585	0	0
GrantKnown_A	411143232	411026140	0	0
IdxKnown_A	411143232	411026140	0	0
IndexIsCorrect_A	411143232	771585	0	0
LockArbDecision_A	411143232	0	0	0
NoReadyValidNoGrant_A	411143232	346099000	0	0
ReadyAndValidImplyGrant_A	411143232	771585	0	0
ReqAndReadyImplyGrant_A	411143232	771585	0	0
ReqImpliesValid_A	411143232	11830766	0	0
ReqStaysHighUntilGranted0_M	411143232	0	0	0
RoundRobin_A	411143232	19814	0	900
ValidKnown_A	411143232	411026140	0	0
gen_data_port_assertion.DataFlow_A	411143232	771585	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	771585	0	0
T1	505796	31	0	0
T2	401678	54	0	0
T3	388006	63	0	0
T4	120268	1538	0	0
T7	20211	152	0	0
T8	380424	728	0	0
T9	4549	230	0	0
T10	38058	462	0	0
T11	68511	4410	0	0
T12	97475	5651	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	771585	0	0
T1	505796	31	0	0
T2	401678	54	0	0
T3	388006	63	0	0
T4	120268	1538	0	0
T7	20211	152	0	0
T8	380424	728	0	0
T9	4549	230	0	0
T10	38058	462	0	0
T11	68511	4410	0	0
T12	97475	5651	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	771585	0	0
T1	505796	31	0	0
T2	401678	54	0	0
T3	388006	63	0	0
T4	120268	1538	0	0
T7	20211	152	0	0
T8	380424	728	0	0
T9	4549	230	0	0
T10	38058	462	0	0
T11	68511	4410	0	0
T12	97475	5651	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	346099000	0	0
T1	505796	491888	0	0
T2	401678	383022	0	0
T3	388006	323249	0	0
T4	120268	96174	0	0
T7	20211	17167	0	0
T8	380424	354580	0	0
T9	4549	1	0	0
T10	38058	29997	0	0
T11	68511	1	0	0
T12	97475	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	771585	0	0
T1	505796	31	0	0
T2	401678	54	0	0
T3	388006	63	0	0
T4	120268	1538	0	0
T7	20211	152	0	0
T8	380424	728	0	0
T9	4549	230	0	0
T10	38058	462	0	0
T11	68511	4410	0	0
T12	97475	5651	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	771585	0	0
T1	505796	31	0	0
T2	401678	54	0	0
T3	388006	63	0	0
T4	120268	1538	0	0
T7	20211	152	0	0
T8	380424	728	0	0
T9	4549	230	0	0
T10	38058	462	0	0
T11	68511	4410	0	0
T12	97475	5651	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	11830766	0	0
T1	505796	9951	0	0
T2	401678	17874	0	0
T3	388006	308	0	0
T4	120268	14595	0	0
T7	20211	1377	0	0
T8	380424	251479	0	0
T9	4549	230	0	0
T10	38058	3391	0	0
T11	68511	4410	0	0
T12	97475	5651	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	19814	0	900
T4	120268	15	0	1
T9	4549	3	0	1
T10	38058	0	0	1
T11	68511	466	0	1
T12	97475	989	0	1
T13	1845	0	0	1
T14	275511	0	0	1
T15	17424	19	0	1
T16	0	1	0	0
T17	0	142	0	0
T18	0	2	0	0
T21	0	8	0	0
T22	0	5	0	0
T23	9103	0	0	1
T24	2812	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	411026140	0	0
T1	505796	505786	0	0
T2	401678	401627	0	0
T3	388006	387969	0	0
T4	120268	120199	0	0
T7	20211	20186	0	0
T8	380424	380417	0	0
T9	4549	4486	0	0
T10	38058	37745	0	0
T11	68511	68439	0	0
T12	97475	97088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411143232	771585	0	0
T1	505796	31	0	0
T2	401678	54	0	0
T3	388006	63	0	0
T4	120268	1538	0	0
T7	20211	152	0	0
T8	380424	728	0	0
T9	4549	230	0	0
T10	38058	462	0	0
T11	68511	4410	0	0
T12	97475	5651	0	0