Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1558928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248021

1

T1

6

T2

5

T3

416

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	612291	1			T1	43		T2	33		T3	945
values[0x0]	581447	1			T1	4		T2	8		T3	975
values[0x1]	613211	1			T1	45		T2	34		T3	1009

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205257	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

601692

1

T1

35

T2

27

T3

1000

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28770	1			T1	3		T2	1		T3	40
valid_sources[0x01]	28936	1			T1	2		T3	52		T7	24
valid_sources[0x02]	29176	1			T1	1		T2	1		T3	44
valid_sources[0x03]	28181	1			T2	3		T3	52		T7	34
valid_sources[0x04]	27889	1			T2	2		T3	42		T7	20
valid_sources[0x05]	27627	1			T1	2		T2	1		T3	47
valid_sources[0x06]	28415	1			T1	3		T2	1		T3	38
valid_sources[0x07]	28169	1			T1	4		T2	2		T3	55
valid_sources[0x08]	28081	1			T1	2		T3	34		T7	36
valid_sources[0x09]	27994	1			T3	41		T7	29		T8	59
valid_sources[0x0a]	27113	1			T2	1		T3	50		T7	28
valid_sources[0x0b]	29315	1			T1	3		T2	2		T3	49
valid_sources[0x0c]	28837	1			T1	1		T2	1		T3	38
valid_sources[0x0d]	28668	1			T1	3		T2	4		T3	42
valid_sources[0x0e]	27431	1			T1	2		T2	3		T3	55
valid_sources[0x0f]	27495	1			T2	1		T3	43		T7	26
valid_sources[0x10]	28248	1			T3	48		T7	27		T8	66
valid_sources[0x11]	27751	1			T3	28		T7	18		T8	32
valid_sources[0x12]	28802	1			T1	1		T2	2		T3	36
valid_sources[0x13]	27792	1			T3	45		T7	29		T8	17
valid_sources[0x14]	27848	1			T1	3		T2	1		T3	44
valid_sources[0x15]	27366	1			T1	1		T3	38		T7	21
valid_sources[0x16]	28735	1			T1	1		T3	36		T7	17
valid_sources[0x17]	27349	1			T1	1		T2	1		T3	46
valid_sources[0x18]	27936	1			T1	2		T2	2		T3	48
valid_sources[0x19]	27281	1			T1	1		T3	52		T7	29
valid_sources[0x1a]	28163	1			T1	2		T2	1		T3	38
valid_sources[0x1b]	28666	1			T1	1		T2	1		T3	46
valid_sources[0x1c]	29123	1			T1	1		T2	1		T3	58
valid_sources[0x1d]	27689	1			T1	2		T2	3		T3	43
valid_sources[0x1e]	28711	1			T1	2		T3	44		T7	21
valid_sources[0x1f]	28575	1			T1	1		T2	2		T3	50
valid_sources[0x20]	27667	1			T1	2		T3	49		T7	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26096

1

T1

1

T3

39

T7

26

values[0x0]

all_enables

biggest_size

195993

1

T1

1

T2

3

T3

330

values[0x1]

all_enables

biggest_size

25932

1

T1

4

T2

2

T3

47

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1570909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

257526

1

T1

8

T2

9

T3

417

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	625331	1			T1	31		T2	35		T3	984
values[0x0]	577485	1			T1	9		T2	5		T3	955
values[0x1]	625619	1			T1	35		T2	37		T3	964

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

622694

1

T1

26

T2

31

T3

1010

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28682	1			T1	1		T2	1		T3	37
valid_sources[0x01]	28568	1			T1	2		T3	47		T7	25
valid_sources[0x02]	28677	1			T1	2		T3	30		T7	6
valid_sources[0x03]	29200	1			T2	1		T3	75		T7	21
valid_sources[0x04]	28748	1			T1	3		T3	48		T7	25
valid_sources[0x05]	29200	1			T1	3		T2	2		T3	61
valid_sources[0x06]	28329	1			T2	4		T3	48		T7	51
valid_sources[0x07]	27648	1			T2	4		T3	49		T7	66
valid_sources[0x08]	28665	1			T1	1		T2	1		T3	54
valid_sources[0x09]	28701	1			T1	1		T3	45		T7	9
valid_sources[0x0a]	28536	1			T1	2		T2	1		T3	43
valid_sources[0x0b]	28348	1			T1	1		T3	38		T7	32
valid_sources[0x0c]	28417	1			T1	1		T3	44		T7	48
valid_sources[0x0d]	28459	1			T2	1		T3	49		T7	57
valid_sources[0x0e]	27831	1			T2	4		T3	43		T7	36
valid_sources[0x0f]	28195	1			T1	3		T3	42		T7	50
valid_sources[0x10]	28600	1			T1	4		T2	1		T3	51
valid_sources[0x11]	28119	1			T2	4		T3	33		T7	13
valid_sources[0x12]	27614	1			T1	3		T2	2		T3	56
valid_sources[0x13]	28414	1			T1	3		T3	38		T7	13
valid_sources[0x14]	29397	1			T1	1		T2	1		T3	51
valid_sources[0x15]	28662	1			T1	1		T3	32		T7	63
valid_sources[0x16]	28136	1			T1	1		T2	1		T3	61
valid_sources[0x17]	27562	1			T3	58		T7	35		T8	33
valid_sources[0x18]	29071	1			T3	53		T7	19		T8	19
valid_sources[0x19]	28328	1			T2	3		T3	46		T7	17
valid_sources[0x1a]	29021	1			T1	1		T2	1		T3	40
valid_sources[0x1b]	28285	1			T1	1		T3	35		T7	8
valid_sources[0x1c]	28540	1			T1	2		T2	2		T3	47
valid_sources[0x1d]	28003	1			T1	2		T2	1		T3	38
valid_sources[0x1e]	29284	1			T1	2		T2	4		T3	35
valid_sources[0x1f]	29103	1			T1	2		T3	39		T7	17
valid_sources[0x20]	28379	1			T2	3		T3	58		T7	62

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26928

1

T1

1

T2

5

T3

41

values[0x0]

all_enables

biggest_size

203524

1

T1

6

T2

2

T3

339

values[0x1]

all_enables

biggest_size

27074

1

T1

1

T2

2

T3

37

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1571015	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249604

1

T1

8

T2

10

T3

417

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	617276	1			T1	41		T2	34		T3	1042
values[0x0]	585519	1			T1	6		T2	7		T3	965
values[0x1]	617824	1			T1	36		T2	36		T3	994

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1214503	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

606116

1

T1

30

T2

28

T3

990

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28256	1			T1	4		T2	2		T3	32
valid_sources[0x01]	28125	1			T1	1		T3	37		T7	31
valid_sources[0x02]	27873	1			T3	35		T7	24		T8	40
valid_sources[0x03]	28647	1			T1	3		T2	1		T3	54
valid_sources[0x04]	29128	1			T1	3		T2	1		T3	48
valid_sources[0x05]	28755	1			T1	1		T2	2		T3	49
valid_sources[0x06]	27732	1			T2	3		T3	59		T7	35
valid_sources[0x07]	28419	1			T1	4		T3	45		T7	26
valid_sources[0x08]	28292	1			T1	1		T3	44		T7	30
valid_sources[0x09]	28783	1			T2	2		T3	38		T7	29
valid_sources[0x0a]	28461	1			T1	2		T2	2		T3	43
valid_sources[0x0b]	27940	1			T1	1		T2	1		T3	61
valid_sources[0x0c]	28228	1			T2	2		T3	43		T7	19
valid_sources[0x0d]	27989	1			T1	1		T2	2		T3	41
valid_sources[0x0e]	27687	1			T2	2		T3	39		T7	35
valid_sources[0x0f]	28492	1			T1	1		T3	38		T7	27
valid_sources[0x10]	28162	1			T1	1		T3	42		T7	34
valid_sources[0x11]	28483	1			T1	3		T2	7		T3	52
valid_sources[0x12]	28238	1			T1	4		T2	3		T3	60
valid_sources[0x13]	28285	1			T1	1		T3	43		T7	34
valid_sources[0x14]	29017	1			T3	53		T7	24		T8	30
valid_sources[0x15]	27789	1			T1	2		T3	45		T7	29
valid_sources[0x16]	28413	1			T1	1		T3	51		T7	22
valid_sources[0x17]	29354	1			T1	1		T2	5		T3	43
valid_sources[0x18]	28433	1			T3	64		T7	18		T8	28
valid_sources[0x19]	28096	1			T1	3		T2	2		T3	37
valid_sources[0x1a]	28345	1			T1	1		T2	1		T3	47
valid_sources[0x1b]	28405	1			T2	1		T3	49		T7	16
valid_sources[0x1c]	29005	1			T2	1		T3	45		T7	29
valid_sources[0x1d]	29286	1			T1	1		T3	58		T7	25
valid_sources[0x1e]	28608	1			T3	49		T7	36		T8	30
valid_sources[0x1f]	28110	1			T1	2		T3	52		T7	25
valid_sources[0x20]	28499	1			T1	1		T3	33		T7	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26066

1

T1

2

T2

4

T3

43

values[0x0]

all_enables

biggest_size

197356

1

T1

3

T2

3

T3

325

values[0x1]

all_enables

biggest_size

26182

1

T1

3

T2

3

T3

49