Line Coverage for Module :
prim_fifo_async
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_async ( parameter Width=107,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_async ( parameter Width=64,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_async
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_async
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
348320 |
347913 |
0 |
0 |
T2 |
97632 |
93867 |
0 |
0 |
T3 |
516076 |
515542 |
0 |
0 |
T7 |
2276616 |
2276543 |
0 |
0 |
T8 |
1909556 |
1909508 |
0 |
0 |
T9 |
269660 |
268768 |
0 |
0 |
T10 |
42579 |
42343 |
0 |
0 |
T11 |
50765 |
50249 |
0 |
0 |
T12 |
1355082 |
1349398 |
0 |
0 |
T13 |
2028366 |
2026245 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
348320 |
347913 |
0 |
0 |
T2 |
97632 |
93867 |
0 |
0 |
T3 |
516076 |
515542 |
0 |
0 |
T7 |
2276616 |
2276543 |
0 |
0 |
T8 |
1909556 |
1909508 |
0 |
0 |
T9 |
269660 |
268768 |
0 |
0 |
T10 |
42579 |
42343 |
0 |
0 |
T11 |
50765 |
50249 |
0 |
0 |
T12 |
1355082 |
1349398 |
0 |
0 |
T13 |
2028366 |
2026245 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7200 |
7200 |
0 |
0 |
T1 |
8 |
8 |
0 |
0 |
T2 |
8 |
8 |
0 |
0 |
T3 |
8 |
8 |
0 |
0 |
T7 |
8 |
8 |
0 |
0 |
T8 |
8 |
8 |
0 |
0 |
T9 |
8 |
8 |
0 |
0 |
T10 |
8 |
8 |
0 |
0 |
T11 |
8 |
8 |
0 |
0 |
T12 |
8 |
8 |
0 |
0 |
T13 |
8 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_35.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_35.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_35.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_35.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
410263252 |
410139181 |
0 |
0 |
T1 |
52447 |
52386 |
0 |
0 |
T2 |
11716 |
11263 |
0 |
0 |
T3 |
69678 |
69606 |
0 |
0 |
T7 |
218452 |
218445 |
0 |
0 |
T8 |
215657 |
215651 |
0 |
0 |
T9 |
43690 |
43546 |
0 |
0 |
T10 |
2250 |
2237 |
0 |
0 |
T11 |
5764 |
5705 |
0 |
0 |
T12 |
148339 |
147715 |
0 |
0 |
T13 |
194459 |
194251 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
551551974 |
551420129 |
0 |
0 |
T1 |
17103 |
17083 |
0 |
0 |
T2 |
7810 |
7507 |
0 |
0 |
T3 |
58958 |
58897 |
0 |
0 |
T7 |
223707 |
223700 |
0 |
0 |
T8 |
239192 |
239186 |
0 |
0 |
T9 |
31478 |
31373 |
0 |
0 |
T10 |
9693 |
9640 |
0 |
0 |
T11 |
4348 |
4304 |
0 |
0 |
T12 |
256585 |
255514 |
0 |
0 |
T13 |
103211 |
103106 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_37.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_37.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_37.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_37.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
410263252 |
410139181 |
0 |
0 |
T1 |
52447 |
52386 |
0 |
0 |
T2 |
11716 |
11263 |
0 |
0 |
T3 |
69678 |
69606 |
0 |
0 |
T7 |
218452 |
218445 |
0 |
0 |
T8 |
215657 |
215651 |
0 |
0 |
T9 |
43690 |
43546 |
0 |
0 |
T10 |
2250 |
2237 |
0 |
0 |
T11 |
5764 |
5705 |
0 |
0 |
T12 |
148339 |
147715 |
0 |
0 |
T13 |
194459 |
194251 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
574601197 |
574482686 |
0 |
0 |
T1 |
39336 |
39290 |
0 |
0 |
T2 |
19068 |
18337 |
0 |
0 |
T3 |
66616 |
66547 |
0 |
0 |
T7 |
218452 |
218445 |
0 |
0 |
T8 |
278386 |
278380 |
0 |
0 |
T9 |
7046 |
7022 |
0 |
0 |
T10 |
8654 |
8607 |
0 |
0 |
T11 |
7686 |
7608 |
0 |
0 |
T12 |
352795 |
351329 |
0 |
0 |
T13 |
688093 |
687386 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_39.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_39.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_39.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_39.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
410263252 |
410139181 |
0 |
0 |
T1 |
52447 |
52386 |
0 |
0 |
T2 |
11716 |
11263 |
0 |
0 |
T3 |
69678 |
69606 |
0 |
0 |
T7 |
218452 |
218445 |
0 |
0 |
T8 |
215657 |
215651 |
0 |
0 |
T9 |
43690 |
43546 |
0 |
0 |
T10 |
2250 |
2237 |
0 |
0 |
T11 |
5764 |
5705 |
0 |
0 |
T12 |
148339 |
147715 |
0 |
0 |
T13 |
194459 |
194251 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
554480188 |
554365343 |
0 |
0 |
T1 |
37626 |
37581 |
0 |
0 |
T2 |
21364 |
20545 |
0 |
0 |
T3 |
58958 |
58897 |
0 |
0 |
T7 |
815895 |
815869 |
0 |
0 |
T8 |
176450 |
176446 |
0 |
0 |
T9 |
14564 |
14515 |
0 |
0 |
T10 |
5539 |
5508 |
0 |
0 |
T11 |
9203 |
9110 |
0 |
0 |
T12 |
72163 |
71855 |
0 |
0 |
T13 |
115180 |
115062 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_41.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_41.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_41.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_41.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
410263252 |
410139181 |
0 |
0 |
T1 |
52447 |
52386 |
0 |
0 |
T2 |
11716 |
11263 |
0 |
0 |
T3 |
69678 |
69606 |
0 |
0 |
T7 |
218452 |
218445 |
0 |
0 |
T8 |
215657 |
215651 |
0 |
0 |
T9 |
43690 |
43546 |
0 |
0 |
T10 |
2250 |
2237 |
0 |
0 |
T11 |
5764 |
5705 |
0 |
0 |
T12 |
148339 |
147715 |
0 |
0 |
T13 |
194459 |
194251 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
510173921 |
510047561 |
0 |
0 |
T1 |
44467 |
44415 |
0 |
0 |
T2 |
2526 |
2426 |
0 |
0 |
T3 |
52832 |
52777 |
0 |
0 |
T7 |
144754 |
144749 |
0 |
0 |
T8 |
352900 |
352892 |
0 |
0 |
T9 |
41812 |
41674 |
0 |
0 |
T10 |
9693 |
9640 |
0 |
0 |
T11 |
6472 |
6407 |
0 |
0 |
T12 |
80183 |
79840 |
0 |
0 |
T13 |
344046 |
343687 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_35.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_35.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_35.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_35.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
551551974 |
551420129 |
0 |
0 |
T1 |
17103 |
17083 |
0 |
0 |
T2 |
7810 |
7507 |
0 |
0 |
T3 |
58958 |
58897 |
0 |
0 |
T7 |
223707 |
223700 |
0 |
0 |
T8 |
239192 |
239186 |
0 |
0 |
T9 |
31478 |
31373 |
0 |
0 |
T10 |
9693 |
9640 |
0 |
0 |
T11 |
4348 |
4304 |
0 |
0 |
T12 |
256585 |
255514 |
0 |
0 |
T13 |
103211 |
103106 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
410263252 |
410139181 |
0 |
0 |
T1 |
52447 |
52386 |
0 |
0 |
T2 |
11716 |
11263 |
0 |
0 |
T3 |
69678 |
69606 |
0 |
0 |
T7 |
218452 |
218445 |
0 |
0 |
T8 |
215657 |
215651 |
0 |
0 |
T9 |
43690 |
43546 |
0 |
0 |
T10 |
2250 |
2237 |
0 |
0 |
T11 |
5764 |
5705 |
0 |
0 |
T12 |
148339 |
147715 |
0 |
0 |
T13 |
194459 |
194251 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_37.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_37.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_37.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_37.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
574601197 |
574482686 |
0 |
0 |
T1 |
39336 |
39290 |
0 |
0 |
T2 |
19068 |
18337 |
0 |
0 |
T3 |
66616 |
66547 |
0 |
0 |
T7 |
218452 |
218445 |
0 |
0 |
T8 |
278386 |
278380 |
0 |
0 |
T9 |
7046 |
7022 |
0 |
0 |
T10 |
8654 |
8607 |
0 |
0 |
T11 |
7686 |
7608 |
0 |
0 |
T12 |
352795 |
351329 |
0 |
0 |
T13 |
688093 |
687386 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
410263252 |
410139181 |
0 |
0 |
T1 |
52447 |
52386 |
0 |
0 |
T2 |
11716 |
11263 |
0 |
0 |
T3 |
69678 |
69606 |
0 |
0 |
T7 |
218452 |
218445 |
0 |
0 |
T8 |
215657 |
215651 |
0 |
0 |
T9 |
43690 |
43546 |
0 |
0 |
T10 |
2250 |
2237 |
0 |
0 |
T11 |
5764 |
5705 |
0 |
0 |
T12 |
148339 |
147715 |
0 |
0 |
T13 |
194459 |
194251 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_39.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_39.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_39.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_39.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
554480188 |
554365343 |
0 |
0 |
T1 |
37626 |
37581 |
0 |
0 |
T2 |
21364 |
20545 |
0 |
0 |
T3 |
58958 |
58897 |
0 |
0 |
T7 |
815895 |
815869 |
0 |
0 |
T8 |
176450 |
176446 |
0 |
0 |
T9 |
14564 |
14515 |
0 |
0 |
T10 |
5539 |
5508 |
0 |
0 |
T11 |
9203 |
9110 |
0 |
0 |
T12 |
72163 |
71855 |
0 |
0 |
T13 |
115180 |
115062 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
410263252 |
410139181 |
0 |
0 |
T1 |
52447 |
52386 |
0 |
0 |
T2 |
11716 |
11263 |
0 |
0 |
T3 |
69678 |
69606 |
0 |
0 |
T7 |
218452 |
218445 |
0 |
0 |
T8 |
215657 |
215651 |
0 |
0 |
T9 |
43690 |
43546 |
0 |
0 |
T10 |
2250 |
2237 |
0 |
0 |
T11 |
5764 |
5705 |
0 |
0 |
T12 |
148339 |
147715 |
0 |
0 |
T13 |
194459 |
194251 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_41.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_41.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_41.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_41.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
510173921 |
510047561 |
0 |
0 |
T1 |
44467 |
44415 |
0 |
0 |
T2 |
2526 |
2426 |
0 |
0 |
T3 |
52832 |
52777 |
0 |
0 |
T7 |
144754 |
144749 |
0 |
0 |
T8 |
352900 |
352892 |
0 |
0 |
T9 |
41812 |
41674 |
0 |
0 |
T10 |
9693 |
9640 |
0 |
0 |
T11 |
6472 |
6407 |
0 |
0 |
T12 |
80183 |
79840 |
0 |
0 |
T13 |
344046 |
343687 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
410263252 |
410139181 |
0 |
0 |
T1 |
52447 |
52386 |
0 |
0 |
T2 |
11716 |
11263 |
0 |
0 |
T3 |
69678 |
69606 |
0 |
0 |
T7 |
218452 |
218445 |
0 |
0 |
T8 |
215657 |
215651 |
0 |
0 |
T9 |
43690 |
43546 |
0 |
0 |
T10 |
2250 |
2237 |
0 |
0 |
T11 |
5764 |
5705 |
0 |
0 |
T12 |
148339 |
147715 |
0 |
0 |
T13 |
194459 |
194251 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |