Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7894332	0	0
GntImpliesValid_A	2147483647	7894332	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7894332	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	445799015	0	0
ReadyAndValidImplyGrant_A	2147483647	7894332	0	0
ReqAndReadyImplyGrant_A	2147483647	7894332	0	0
ReqImpliesValid_A	2147483647	33979908	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50329	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7894332	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1258728	1257288	0	0
T2	281184	270456	0	0
T3	1672272	1670568	0	0
T7	5242848	5242680	0	0
T8	5175768	5175648	0	0
T9	1048560	1045152	0	0
T10	54000	53712	0	0
T11	138336	136944	0	0
T12	3560136	3545448	0	0
T13	4667016	4662264	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7894332	0	0
T1	1258728	5435	0	0
T2	281184	4889	0	0
T3	1672272	4549	0	0
T7	5242848	5281	0	0
T8	5175768	5539	0	0
T9	1048560	19942	0	0
T10	54000	856	0	0
T11	138336	445	0	0
T12	3560136	74683	0	0
T13	4667016	23405	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7894332	0	0
T1	1258728	5435	0	0
T2	281184	4889	0	0
T3	1672272	4549	0	0
T7	5242848	5281	0	0
T8	5175768	5539	0	0
T9	1048560	19942	0	0
T10	54000	856	0	0
T11	138336	445	0	0
T12	3560136	74683	0	0
T13	4667016	23405	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1258728	1257288	0	0
T2	281184	270456	0	0
T3	1672272	1670568	0	0
T7	5242848	5242680	0	0
T8	5175768	5175648	0	0
T9	1048560	1045152	0	0
T10	54000	53712	0	0
T11	138336	136944	0	0
T12	3560136	3545448	0	0
T13	4667016	4662264	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1258728	1257288	0	0
T2	281184	270456	0	0
T3	1672272	1670568	0	0
T7	5242848	5242680	0	0
T8	5175768	5175648	0	0
T9	1048560	1045152	0	0
T10	54000	53712	0	0
T11	138336	136944	0	0
T12	3560136	3545448	0	0
T13	4667016	4662264	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7894332	0	0
T1	1258728	5435	0	0
T2	281184	4889	0	0
T3	1672272	4549	0	0
T7	5242848	5281	0	0
T8	5175768	5539	0	0
T9	1048560	19942	0	0
T10	54000	856	0	0
T11	138336	445	0	0
T12	3560136	74683	0	0
T13	4667016	23405	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	445799015	0	0
T1	1258728	85391	0	0
T2	281184	7386	0	0
T3	1672272	90667	0	0
T7	5242848	1783139	0	0
T8	5175768	1737238	0	0
T9	1048560	30101	0	0
T10	54000	908	0	0
T11	138336	8056	0	0
T12	3560136	64050	0	0
T13	4667016	302427	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7894332	0	0
T1	1258728	5435	0	0
T2	281184	4889	0	0
T3	1672272	4549	0	0
T7	5242848	5281	0	0
T8	5175768	5539	0	0
T9	1048560	19942	0	0
T10	54000	856	0	0
T11	138336	445	0	0
T12	3560136	74683	0	0
T13	4667016	23405	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7894332	0	0
T1	1258728	5435	0	0
T2	281184	4889	0	0
T3	1672272	4549	0	0
T7	5242848	5281	0	0
T8	5175768	5539	0	0
T9	1048560	19942	0	0
T10	54000	856	0	0
T11	138336	445	0	0
T12	3560136	74683	0	0
T13	4667016	23405	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33979908	0	0
T1	1258728	13033	0	0
T2	281184	5643	0	0
T3	1672272	9631	0	0
T7	5242848	329120	0	0
T8	5175768	346951	0	0
T9	1048560	22403	0	0
T10	54000	867	0	0
T11	138336	1034	0	0
T12	3560136	121499	0	0
T13	4667016	51721	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50329	0	21600
T1	52447	1	0	1
T2	23432	10	0	2
T3	139356	0	0	2
T7	436904	1	0	2
T8	431314	0	0	2
T9	87380	624	0	2
T10	4500	1	0	2
T11	11528	0	0	2
T12	296678	1033	0	2
T13	388918	2	0	2
T14	0	8	0	0
T15	0	20	0	0
T16	0	330	0	0
T17	0	435	0	0
T18	0	6	0	0
T19	113466	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1258728	1257288	0	0
T2	281184	270456	0	0
T3	1672272	1670568	0	0
T7	5242848	5242680	0	0
T8	5175768	5175648	0	0
T9	1048560	1045152	0	0
T10	54000	53712	0	0
T11	138336	136944	0	0
T12	3560136	3545448	0	0
T13	4667016	4662264	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7894332	0	0
T1	1258728	5435	0	0
T2	281184	4889	0	0
T3	1672272	4549	0	0
T7	5242848	5281	0	0
T8	5175768	5539	0	0
T9	1048560	19942	0	0
T10	54000	856	0	0
T11	138336	445	0	0
T12	3560136	74683	0	0
T13	4667016	23405	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	874193	0	0
GntImpliesValid_A	410263252	874193	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	874193	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	11598996	0	0
ReadyAndValidImplyGrant_A	410263252	874193	0	0
ReqAndReadyImplyGrant_A	410263252	874193	0	0
ReqImpliesValid_A	410263252	2449347	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	874193	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	874193	0	0
T1	52447	576	0	0
T2	11716	568	0	0
T3	69678	465	0	0
T7	218452	629	0	0
T8	215657	598	0	0
T9	43690	2056	0	0
T10	2250	93	0	0
T11	5764	38	0	0
T12	148339	7376	0	0
T13	194459	2529	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	874193	0	0
T1	52447	576	0	0
T2	11716	568	0	0
T3	69678	465	0	0
T7	218452	629	0	0
T8	215657	598	0	0
T9	43690	2056	0	0
T10	2250	93	0	0
T11	5764	38	0	0
T12	148339	7376	0	0
T13	194459	2529	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	874193	0	0
T1	52447	576	0	0
T2	11716	568	0	0
T3	69678	465	0	0
T7	218452	629	0	0
T8	215657	598	0	0
T9	43690	2056	0	0
T10	2250	93	0	0
T11	5764	38	0	0
T12	148339	7376	0	0
T13	194459	2529	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	11598996	0	0
T1	52447	4378	0	0
T2	11716	478	0	0
T3	69678	3203	0	0
T7	218452	187139	0	0
T8	215657	188012	0	0
T9	43690	1786	0	0
T10	2250	91	0	0
T11	5764	288	0	0
T12	148339	5121	0	0
T13	194459	17026	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	874193	0	0
T1	52447	576	0	0
T2	11716	568	0	0
T3	69678	465	0	0
T7	218452	629	0	0
T8	215657	598	0	0
T9	43690	2056	0	0
T10	2250	93	0	0
T11	5764	38	0	0
T12	148339	7376	0	0
T13	194459	2529	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	874193	0	0
T1	52447	576	0	0
T2	11716	568	0	0
T3	69678	465	0	0
T7	218452	629	0	0
T8	215657	598	0	0
T9	43690	2056	0	0
T10	2250	93	0	0
T11	5764	38	0	0
T12	148339	7376	0	0
T13	194459	2529	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2449347	0	0
T1	52447	1000	0	0
T2	11716	664	0	0
T3	69678	723	0	0
T7	218452	20900	0	0
T8	215657	13050	0	0
T9	43690	2328	0	0
T10	2250	96	0	0
T11	5764	38	0	0
T12	148339	9643	0	0
T13	194459	4418	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	874193	0	0
T1	52447	576	0	0
T2	11716	568	0	0
T3	69678	465	0	0
T7	218452	629	0	0
T8	215657	598	0	0
T9	43690	2056	0	0
T10	2250	93	0	0
T11	5764	38	0	0
T12	148339	7376	0	0
T13	194459	2529	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	868509	0	0
GntImpliesValid_A	410263252	868509	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	868509	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	11434026	0	0
ReadyAndValidImplyGrant_A	410263252	868509	0	0
ReqAndReadyImplyGrant_A	410263252	868509	0	0
ReqImpliesValid_A	410263252	2366087	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	868509	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	868509	0	0
T1	52447	621	0	0
T2	11716	532	0	0
T3	69678	552	0	0
T7	218452	605	0	0
T8	215657	606	0	0
T9	43690	2026	0	0
T10	2250	80	0	0
T11	5764	60	0	0
T12	148339	9622	0	0
T13	194459	3367	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	868509	0	0
T1	52447	621	0	0
T2	11716	532	0	0
T3	69678	552	0	0
T7	218452	605	0	0
T8	215657	606	0	0
T9	43690	2026	0	0
T10	2250	80	0	0
T11	5764	60	0	0
T12	148339	9622	0	0
T13	194459	3367	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	868509	0	0
T1	52447	621	0	0
T2	11716	532	0	0
T3	69678	552	0	0
T7	218452	605	0	0
T8	215657	606	0	0
T9	43690	2026	0	0
T10	2250	80	0	0
T11	5764	60	0	0
T12	148339	9622	0	0
T13	194459	3367	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	11434026	0	0
T1	52447	4556	0	0
T2	11716	448	0	0
T3	69678	4168	0	0
T7	218452	199813	0	0
T8	215657	191297	0	0
T9	43690	1768	0	0
T10	2250	81	0	0
T11	5764	445	0	0
T12	148339	5368	0	0
T13	194459	20208	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	868509	0	0
T1	52447	621	0	0
T2	11716	532	0	0
T3	69678	552	0	0
T7	218452	605	0	0
T8	215657	606	0	0
T9	43690	2026	0	0
T10	2250	80	0	0
T11	5764	60	0	0
T12	148339	9622	0	0
T13	194459	3367	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	868509	0	0
T1	52447	621	0	0
T2	11716	532	0	0
T3	69678	552	0	0
T7	218452	605	0	0
T8	215657	606	0	0
T9	43690	2026	0	0
T10	2250	80	0	0
T11	5764	60	0	0
T12	148339	9622	0	0
T13	194459	3367	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2366087	0	0
T1	52447	1260	0	0
T2	11716	622	0	0
T3	69678	883	0	0
T7	218452	22756	0	0
T8	215657	22250	0	0
T9	43690	2286	0	0
T10	2250	80	0	0
T11	5764	102	0	0
T12	148339	13887	0	0
T13	194459	7325	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	868509	0	0
T1	52447	621	0	0
T2	11716	532	0	0
T3	69678	552	0	0
T7	218452	605	0	0
T8	215657	606	0	0
T9	43690	2026	0	0
T10	2250	80	0	0
T11	5764	60	0	0
T12	148339	9622	0	0
T13	194459	3367	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	217426	0	0
GntImpliesValid_A	410263252	217426	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	217426	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2817029	0	0
ReadyAndValidImplyGrant_A	410263252	217426	0	0
ReqAndReadyImplyGrant_A	410263252	217426	0	0
ReqImpliesValid_A	410263252	565209	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	217426	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217426	0	0
T1	52447	148	0	0
T2	11716	143	0	0
T3	69678	136	0	0
T7	218452	140	0	0
T8	215657	150	0	0
T9	43690	437	0	0
T10	2250	22	0	0
T11	5764	9	0	0
T12	148339	1714	0	0
T13	194459	609	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217426	0	0
T1	52447	148	0	0
T2	11716	143	0	0
T3	69678	136	0	0
T7	218452	140	0	0
T8	215657	150	0	0
T9	43690	437	0	0
T10	2250	22	0	0
T11	5764	9	0	0
T12	148339	1714	0	0
T13	194459	609	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217426	0	0
T1	52447	148	0	0
T2	11716	143	0	0
T3	69678	136	0	0
T7	218452	140	0	0
T8	215657	150	0	0
T9	43690	437	0	0
T10	2250	22	0	0
T11	5764	9	0	0
T12	148339	1714	0	0
T13	194459	609	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2817029	0	0
T1	52447	1095	0	0
T2	11716	140	0	0
T3	69678	1010	0	0
T7	218452	50486	0	0
T8	215657	48024	0	0
T9	43690	430	0	0
T10	2250	23	0	0
T11	5764	39	0	0
T12	148339	1231	0	0
T13	194459	4635	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217426	0	0
T1	52447	148	0	0
T2	11716	143	0	0
T3	69678	136	0	0
T7	218452	140	0	0
T8	215657	150	0	0
T9	43690	437	0	0
T10	2250	22	0	0
T11	5764	9	0	0
T12	148339	1714	0	0
T13	194459	609	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217426	0	0
T1	52447	148	0	0
T2	11716	143	0	0
T3	69678	136	0	0
T7	218452	140	0	0
T8	215657	150	0	0
T9	43690	437	0	0
T10	2250	22	0	0
T11	5764	9	0	0
T12	148339	1714	0	0
T13	194459	609	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	565209	0	0
T1	52447	190	0	0
T2	11716	152	0	0
T3	69678	192	0	0
T7	218452	2783	0	0
T8	215657	5496	0	0
T9	43690	446	0	0
T10	2250	22	0	0
T11	5764	9	0	0
T12	148339	2209	0	0
T13	194459	764	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217426	0	0
T1	52447	148	0	0
T2	11716	143	0	0
T3	69678	136	0	0
T7	218452	140	0	0
T8	215657	150	0	0
T9	43690	437	0	0
T10	2250	22	0	0
T11	5764	9	0	0
T12	148339	1714	0	0
T13	194459	609	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	222077	0	0
GntImpliesValid_A	410263252	222077	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	222077	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2855962	0	0
ReadyAndValidImplyGrant_A	410263252	222077	0	0
ReqAndReadyImplyGrant_A	410263252	222077	0	0
ReqImpliesValid_A	410263252	627593	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	222077	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222077	0	0
T1	52447	159	0	0
T2	11716	143	0	0
T3	69678	120	0	0
T7	218452	152	0	0
T8	215657	137	0	0
T9	43690	434	0	0
T10	2250	25	0	0
T11	5764	6	0	0
T12	148339	2749	0	0
T13	194459	582	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222077	0	0
T1	52447	159	0	0
T2	11716	143	0	0
T3	69678	120	0	0
T7	218452	152	0	0
T8	215657	137	0	0
T9	43690	434	0	0
T10	2250	25	0	0
T11	5764	6	0	0
T12	148339	2749	0	0
T13	194459	582	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222077	0	0
T1	52447	159	0	0
T2	11716	143	0	0
T3	69678	120	0	0
T7	218452	152	0	0
T8	215657	137	0	0
T9	43690	434	0	0
T10	2250	25	0	0
T11	5764	6	0	0
T12	148339	2749	0	0
T13	194459	582	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2855962	0	0
T1	52447	1087	0	0
T2	11716	141	0	0
T3	69678	851	0	0
T7	218452	47520	0	0
T8	215657	42976	0	0
T9	43690	426	0	0
T10	2250	26	0	0
T11	5764	59	0	0
T12	148339	1198	0	0
T13	194459	4383	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222077	0	0
T1	52447	159	0	0
T2	11716	143	0	0
T3	69678	120	0	0
T7	218452	152	0	0
T8	215657	137	0	0
T9	43690	434	0	0
T10	2250	25	0	0
T11	5764	6	0	0
T12	148339	2749	0	0
T13	194459	582	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222077	0	0
T1	52447	159	0	0
T2	11716	143	0	0
T3	69678	120	0	0
T7	218452	152	0	0
T8	215657	137	0	0
T9	43690	434	0	0
T10	2250	25	0	0
T11	5764	6	0	0
T12	148339	2749	0	0
T13	194459	582	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	627593	0	0
T1	52447	210	0	0
T2	11716	150	0	0
T3	69678	166	0	0
T7	218452	2229	0	0
T8	215657	4215	0	0
T9	43690	444	0	0
T10	2250	25	0	0
T11	5764	6	0	0
T12	148339	4312	0	0
T13	194459	804	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222077	0	0
T1	52447	159	0	0
T2	11716	143	0	0
T3	69678	120	0	0
T7	218452	152	0	0
T8	215657	137	0	0
T9	43690	434	0	0
T10	2250	25	0	0
T11	5764	6	0	0
T12	148339	2749	0	0
T13	194459	582	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	208781	0	0
GntImpliesValid_A	410263252	208781	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	208781	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	5619808	0	0
ReadyAndValidImplyGrant_A	410263252	208781	0	0
ReqAndReadyImplyGrant_A	410263252	208781	0	0
ReqImpliesValid_A	410263252	1288398	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	208781	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	208781	0	0
T1	52447	155	0	0
T2	11716	136	0	0
T3	69678	139	0	0
T7	218452	149	0	0
T8	215657	173	0	0
T9	43690	396	0	0
T10	2250	34	0	0
T11	5764	16	0	0
T12	148339	2143	0	0
T13	194459	617	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	208781	0	0
T1	52447	155	0	0
T2	11716	136	0	0
T3	69678	139	0	0
T7	218452	149	0	0
T8	215657	173	0	0
T9	43690	396	0	0
T10	2250	34	0	0
T11	5764	16	0	0
T12	148339	2143	0	0
T13	194459	617	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	208781	0	0
T1	52447	155	0	0
T2	11716	136	0	0
T3	69678	139	0	0
T7	218452	149	0	0
T8	215657	173	0	0
T9	43690	396	0	0
T10	2250	34	0	0
T11	5764	16	0	0
T12	148339	2143	0	0
T13	194459	617	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	5619808	0	0
T1	52447	4746	0	0
T2	11716	932	0	0
T3	69678	1971	0	0
T7	218452	45303	0	0
T8	215657	49883	0	0
T9	43690	2727	0	0
T10	2250	113	0	0
T11	5764	283	0	0
T12	148339	4608	0	0
T13	194459	2887	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	208781	0	0
T1	52447	155	0	0
T2	11716	136	0	0
T3	69678	139	0	0
T7	218452	149	0	0
T8	215657	173	0	0
T9	43690	396	0	0
T10	2250	34	0	0
T11	5764	16	0	0
T12	148339	2143	0	0
T13	194459	617	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	208781	0	0
T1	52447	155	0	0
T2	11716	136	0	0
T3	69678	139	0	0
T7	218452	149	0	0
T8	215657	173	0	0
T9	43690	396	0	0
T10	2250	34	0	0
T11	5764	16	0	0
T12	148339	2143	0	0
T13	194459	617	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	1288398	0	0
T1	52447	471	0	0
T2	11716	206	0	0
T3	69678	214	0	0
T7	218452	1789	0	0
T8	215657	4015	0	0
T9	43690	537	0	0
T10	2250	38	0	0
T11	5764	27	0	0
T12	148339	7803	0	0
T13	194459	681	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	208781	0	0
T1	52447	155	0	0
T2	11716	136	0	0
T3	69678	139	0	0
T7	218452	149	0	0
T8	215657	173	0	0
T9	43690	396	0	0
T10	2250	34	0	0
T11	5764	16	0	0
T12	148339	2143	0	0
T13	194459	617	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	203613	0	0
GntImpliesValid_A	410263252	203613	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	203613	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	5502216	0	0
ReadyAndValidImplyGrant_A	410263252	203613	0	0
ReqAndReadyImplyGrant_A	410263252	203613	0	0
ReqImpliesValid_A	410263252	1233963	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	203613	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	203613	0	0
T1	52447	161	0	0
T2	11716	121	0	0
T3	69678	119	0	0
T7	218452	131	0	0
T8	215657	151	0	0
T9	43690	437	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	3409	0	0
T13	194459	664	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	203613	0	0
T1	52447	161	0	0
T2	11716	121	0	0
T3	69678	119	0	0
T7	218452	131	0	0
T8	215657	151	0	0
T9	43690	437	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	3409	0	0
T13	194459	664	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	203613	0	0
T1	52447	161	0	0
T2	11716	121	0	0
T3	69678	119	0	0
T7	218452	131	0	0
T8	215657	151	0	0
T9	43690	437	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	3409	0	0
T13	194459	664	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	5502216	0	0
T1	52447	2414	0	0
T2	11716	558	0	0
T3	69678	1548	0	0
T7	218452	38098	0	0
T8	215657	38103	0	0
T9	43690	8614	0	0
T10	2250	76	0	0
T11	5764	131	0	0
T12	148339	7441	0	0
T13	194459	3758	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	203613	0	0
T1	52447	161	0	0
T2	11716	121	0	0
T3	69678	119	0	0
T7	218452	131	0	0
T8	215657	151	0	0
T9	43690	437	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	3409	0	0
T13	194459	664	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	203613	0	0
T1	52447	161	0	0
T2	11716	121	0	0
T3	69678	119	0	0
T7	218452	131	0	0
T8	215657	151	0	0
T9	43690	437	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	3409	0	0
T13	194459	664	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	1233963	0	0
T1	52447	297	0	0
T2	11716	152	0	0
T3	69678	226	0	0
T7	218452	1610	0	0
T8	215657	2771	0	0
T9	43690	1302	0	0
T10	2250	25	0	0
T11	5764	21	0	0
T12	148339	10765	0	0
T13	194459	759	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	203613	0	0
T1	52447	161	0	0
T2	11716	121	0	0
T3	69678	119	0	0
T7	218452	131	0	0
T8	215657	151	0	0
T9	43690	437	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	3409	0	0
T13	194459	664	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	222656	0	0
GntImpliesValid_A	410263252	222656	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	222656	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	4794022	0	0
ReadyAndValidImplyGrant_A	410263252	222656	0	0
ReqAndReadyImplyGrant_A	410263252	222656	0	0
ReqImpliesValid_A	410263252	1162472	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	222656	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222656	0	0
T1	52447	152	0	0
T2	11716	125	0	0
T3	69678	115	0	0
T7	218452	152	0	0
T8	215657	151	0	0
T9	43690	421	0	0
T10	2250	25	0	0
T11	5764	11	0	0
T12	148339	1746	0	0
T13	194459	620	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222656	0	0
T1	52447	152	0	0
T2	11716	125	0	0
T3	69678	115	0	0
T7	218452	152	0	0
T8	215657	151	0	0
T9	43690	421	0	0
T10	2250	25	0	0
T11	5764	11	0	0
T12	148339	1746	0	0
T13	194459	620	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222656	0	0
T1	52447	152	0	0
T2	11716	125	0	0
T3	69678	115	0	0
T7	218452	152	0	0
T8	215657	151	0	0
T9	43690	421	0	0
T10	2250	25	0	0
T11	5764	11	0	0
T12	148339	1746	0	0
T13	194459	620	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	4794022	0	0
T1	52447	2335	0	0
T2	11716	559	0	0
T3	69678	1482	0	0
T7	218452	129565	0	0
T8	215657	56765	0	0
T9	43690	4813	0	0
T10	2250	100	0	0
T11	5764	100	0	0
T12	148339	9626	0	0
T13	194459	2761	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222656	0	0
T1	52447	152	0	0
T2	11716	125	0	0
T3	69678	115	0	0
T7	218452	152	0	0
T8	215657	151	0	0
T9	43690	421	0	0
T10	2250	25	0	0
T11	5764	11	0	0
T12	148339	1746	0	0
T13	194459	620	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222656	0	0
T1	52447	152	0	0
T2	11716	125	0	0
T3	69678	115	0	0
T7	218452	152	0	0
T8	215657	151	0	0
T9	43690	421	0	0
T10	2250	25	0	0
T11	5764	11	0	0
T12	148339	1746	0	0
T13	194459	620	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	1162472	0	0
T1	52447	308	0	0
T2	11716	145	0	0
T3	69678	208	0	0
T7	218452	23825	0	0
T8	215657	3586	0	0
T9	43690	706	0	0
T10	2250	26	0	0
T11	5764	11	0	0
T12	148339	8159	0	0
T13	194459	671	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222656	0	0
T1	52447	152	0	0
T2	11716	125	0	0
T3	69678	115	0	0
T7	218452	152	0	0
T8	215657	151	0	0
T9	43690	421	0	0
T10	2250	25	0	0
T11	5764	11	0	0
T12	148339	1746	0	0
T13	194459	620	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	218474	0	0
GntImpliesValid_A	410263252	218474	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	218474	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	5537496	0	0
ReadyAndValidImplyGrant_A	410263252	218474	0	0
ReqAndReadyImplyGrant_A	410263252	218474	0	0
ReqImpliesValid_A	410263252	1244736	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	218474	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	218474	0	0
T1	52447	147	0	0
T2	11716	156	0	0
T3	69678	119	0	0
T7	218452	168	0	0
T8	215657	163	0	0
T9	43690	412	0	0
T10	2250	19	0	0
T11	5764	13	0	0
T12	148339	2415	0	0
T13	194459	661	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	218474	0	0
T1	52447	147	0	0
T2	11716	156	0	0
T3	69678	119	0	0
T7	218452	168	0	0
T8	215657	163	0	0
T9	43690	412	0	0
T10	2250	19	0	0
T11	5764	13	0	0
T12	148339	2415	0	0
T13	194459	661	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	218474	0	0
T1	52447	147	0	0
T2	11716	156	0	0
T3	69678	119	0	0
T7	218452	168	0	0
T8	215657	163	0	0
T9	43690	412	0	0
T10	2250	19	0	0
T11	5764	13	0	0
T12	148339	2415	0	0
T13	194459	661	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	5537496	0	0
T1	52447	2054	0	0
T2	11716	2227	0	0
T3	69678	1796	0	0
T7	218452	77042	0	0
T8	215657	33163	0	0
T9	43690	2449	0	0
T10	2250	63	0	0
T11	5764	147	0	0
T12	148339	11371	0	0
T13	194459	5223	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	218474	0	0
T1	52447	147	0	0
T2	11716	156	0	0
T3	69678	119	0	0
T7	218452	168	0	0
T8	215657	163	0	0
T9	43690	412	0	0
T10	2250	19	0	0
T11	5764	13	0	0
T12	148339	2415	0	0
T13	194459	661	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	218474	0	0
T1	52447	147	0	0
T2	11716	156	0	0
T3	69678	119	0	0
T7	218452	168	0	0
T8	215657	163	0	0
T9	43690	412	0	0
T10	2250	19	0	0
T11	5764	13	0	0
T12	148339	2415	0	0
T13	194459	661	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	1244736	0	0
T1	52447	228	0	0
T2	11716	521	0	0
T3	69678	159	0	0
T7	218452	4742	0	0
T8	215657	758	0	0
T9	43690	513	0	0
T10	2250	19	0	0
T11	5764	13	0	0
T12	148339	11657	0	0
T13	194459	953	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	218474	0	0
T1	52447	147	0	0
T2	11716	156	0	0
T3	69678	119	0	0
T7	218452	168	0	0
T8	215657	163	0	0
T9	43690	412	0	0
T10	2250	19	0	0
T11	5764	13	0	0
T12	148339	2415	0	0
T13	194459	661	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	220516	0	0
GntImpliesValid_A	410263252	220516	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	220516	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2854130	0	0
ReadyAndValidImplyGrant_A	410263252	220516	0	0
ReqAndReadyImplyGrant_A	410263252	220516	0	0
ReqImpliesValid_A	410263252	598628	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	220516	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220516	0	0
T1	52447	123	0	0
T2	11716	132	0	0
T3	69678	130	0	0
T7	218452	142	0	0
T8	215657	138	0	0
T9	43690	463	0	0
T10	2250	24	0	0
T11	5764	13	0	0
T12	148339	2790	0	0
T13	194459	663	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220516	0	0
T1	52447	123	0	0
T2	11716	132	0	0
T3	69678	130	0	0
T7	218452	142	0	0
T8	215657	138	0	0
T9	43690	463	0	0
T10	2250	24	0	0
T11	5764	13	0	0
T12	148339	2790	0	0
T13	194459	663	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220516	0	0
T1	52447	123	0	0
T2	11716	132	0	0
T3	69678	130	0	0
T7	218452	142	0	0
T8	215657	138	0	0
T9	43690	463	0	0
T10	2250	24	0	0
T11	5764	13	0	0
T12	148339	2790	0	0
T13	194459	663	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2854130	0	0
T1	52447	930	0	0
T2	11716	137	0	0
T3	69678	913	0	0
T7	218452	43268	0	0
T8	215657	42709	0	0
T9	43690	456	0	0
T10	2250	25	0	0
T11	5764	105	0	0
T12	148339	1820	0	0
T13	194459	5013	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220516	0	0
T1	52447	123	0	0
T2	11716	132	0	0
T3	69678	130	0	0
T7	218452	142	0	0
T8	215657	138	0	0
T9	43690	463	0	0
T10	2250	24	0	0
T11	5764	13	0	0
T12	148339	2790	0	0
T13	194459	663	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220516	0	0
T1	52447	123	0	0
T2	11716	132	0	0
T3	69678	130	0	0
T7	218452	142	0	0
T8	215657	138	0	0
T9	43690	463	0	0
T10	2250	24	0	0
T11	5764	13	0	0
T12	148339	2790	0	0
T13	194459	663	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	598628	0	0
T1	52447	151	0	0
T2	11716	133	0	0
T3	69678	160	0	0
T7	218452	1465	0	0
T8	215657	4926	0	0
T9	43690	472	0	0
T10	2250	24	0	0
T11	5764	13	0	0
T12	148339	3772	0	0
T13	194459	848	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220516	0	0
T1	52447	123	0	0
T2	11716	132	0	0
T3	69678	130	0	0
T7	218452	142	0	0
T8	215657	138	0	0
T9	43690	463	0	0
T10	2250	24	0	0
T11	5764	13	0	0
T12	148339	2790	0	0
T13	194459	663	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	216679	0	0
GntImpliesValid_A	410263252	216679	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	216679	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2851457	0	0
ReadyAndValidImplyGrant_A	410263252	216679	0	0
ReqAndReadyImplyGrant_A	410263252	216679	0	0
ReqImpliesValid_A	410263252	562896	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	216679	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	216679	0	0
T1	52447	159	0	0
T2	11716	151	0	0
T3	69678	114	0	0
T7	218452	158	0	0
T8	215657	146	0	0
T9	43690	1423	0	0
T10	2250	21	0	0
T11	5764	13	0	0
T12	148339	1687	0	0
T13	194459	638	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	216679	0	0
T1	52447	159	0	0
T2	11716	151	0	0
T3	69678	114	0	0
T7	218452	158	0	0
T8	215657	146	0	0
T9	43690	1423	0	0
T10	2250	21	0	0
T11	5764	13	0	0
T12	148339	1687	0	0
T13	194459	638	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	216679	0	0
T1	52447	159	0	0
T2	11716	151	0	0
T3	69678	114	0	0
T7	218452	158	0	0
T8	215657	146	0	0
T9	43690	1423	0	0
T10	2250	21	0	0
T11	5764	13	0	0
T12	148339	1687	0	0
T13	194459	638	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2851457	0	0
T1	52447	1171	0	0
T2	11716	155	0	0
T3	69678	804	0	0
T7	218452	48810	0	0
T8	215657	42849	0	0
T9	43690	1093	0	0
T10	2250	22	0	0
T11	5764	105	0	0
T12	148339	1510	0	0
T13	194459	4651	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	216679	0	0
T1	52447	159	0	0
T2	11716	151	0	0
T3	69678	114	0	0
T7	218452	158	0	0
T8	215657	146	0	0
T9	43690	1423	0	0
T10	2250	21	0	0
T11	5764	13	0	0
T12	148339	1687	0	0
T13	194459	638	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	216679	0	0
T1	52447	159	0	0
T2	11716	151	0	0
T3	69678	114	0	0
T7	218452	158	0	0
T8	215657	146	0	0
T9	43690	1423	0	0
T10	2250	21	0	0
T11	5764	13	0	0
T12	148339	1687	0	0
T13	194459	638	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	562896	0	0
T1	52447	243	0	0
T2	11716	153	0	0
T3	69678	153	0	0
T7	218452	2110	0	0
T8	215657	3368	0	0
T9	43690	1755	0	0
T10	2250	21	0	0
T11	5764	44	0	0
T12	148339	1876	0	0
T13	194459	920	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	216679	0	0
T1	52447	159	0	0
T2	11716	151	0	0
T3	69678	114	0	0
T7	218452	158	0	0
T8	215657	146	0	0
T9	43690	1423	0	0
T10	2250	21	0	0
T11	5764	13	0	0
T12	148339	1687	0	0
T13	194459	638	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	221378	0	0
GntImpliesValid_A	410263252	221378	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	221378	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2887443	0	0
ReadyAndValidImplyGrant_A	410263252	221378	0	0
ReqAndReadyImplyGrant_A	410263252	221378	0	0
ReqImpliesValid_A	410263252	586946	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	221378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	221378	0	0
T1	52447	140	0	0
T2	11716	149	0	0
T3	69678	106	0	0
T7	218452	117	0	0
T8	215657	131	0	0
T9	43690	420	0	0
T10	2250	19	0	0
T11	5764	14	0	0
T12	148339	1849	0	0
T13	194459	594	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	221378	0	0
T1	52447	140	0	0
T2	11716	149	0	0
T3	69678	106	0	0
T7	218452	117	0	0
T8	215657	131	0	0
T9	43690	420	0	0
T10	2250	19	0	0
T11	5764	14	0	0
T12	148339	1849	0	0
T13	194459	594	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	221378	0	0
T1	52447	140	0	0
T2	11716	149	0	0
T3	69678	106	0	0
T7	218452	117	0	0
T8	215657	131	0	0
T9	43690	420	0	0
T10	2250	19	0	0
T11	5764	14	0	0
T12	148339	1849	0	0
T13	194459	594	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2887443	0	0
T1	52447	1096	0	0
T2	11716	145	0	0
T3	69678	776	0	0
T7	218452	40045	0	0
T8	215657	44909	0	0
T9	43690	408	0	0
T10	2250	20	0	0
T11	5764	110	0	0
T12	148339	1092	0	0
T13	194459	4398	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	221378	0	0
T1	52447	140	0	0
T2	11716	149	0	0
T3	69678	106	0	0
T7	218452	117	0	0
T8	215657	131	0	0
T9	43690	420	0	0
T10	2250	19	0	0
T11	5764	14	0	0
T12	148339	1849	0	0
T13	194459	594	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	221378	0	0
T1	52447	140	0	0
T2	11716	149	0	0
T3	69678	106	0	0
T7	218452	117	0	0
T8	215657	131	0	0
T9	43690	420	0	0
T10	2250	19	0	0
T11	5764	14	0	0
T12	148339	1849	0	0
T13	194459	594	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	586946	0	0
T1	52447	241	0	0
T2	11716	158	0	0
T3	69678	121	0	0
T7	218452	3437	0	0
T8	215657	3009	0	0
T9	43690	434	0	0
T10	2250	19	0	0
T11	5764	14	0	0
T12	148339	2618	0	0
T13	194459	802	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	221378	0	0
T1	52447	140	0	0
T2	11716	149	0	0
T3	69678	106	0	0
T7	218452	117	0	0
T8	215657	131	0	0
T9	43690	420	0	0
T10	2250	19	0	0
T11	5764	14	0	0
T12	148339	1849	0	0
T13	194459	594	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	225652	0	0
GntImpliesValid_A	410263252	225652	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	225652	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2925172	0	0
ReadyAndValidImplyGrant_A	410263252	225652	0	0
ReqAndReadyImplyGrant_A	410263252	225652	0	0
ReqImpliesValid_A	410263252	589836	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	225652	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	225652	0	0
T1	52447	154	0	0
T2	11716	133	0	0
T3	69678	126	0	0
T7	218452	150	0	0
T8	215657	178	0	0
T9	43690	407	0	0
T10	2250	20	0	0
T11	5764	14	0	0
T12	148339	1722	0	0
T13	194459	633	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	225652	0	0
T1	52447	154	0	0
T2	11716	133	0	0
T3	69678	126	0	0
T7	218452	150	0	0
T8	215657	178	0	0
T9	43690	407	0	0
T10	2250	20	0	0
T11	5764	14	0	0
T12	148339	1722	0	0
T13	194459	633	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	225652	0	0
T1	52447	154	0	0
T2	11716	133	0	0
T3	69678	126	0	0
T7	218452	150	0	0
T8	215657	178	0	0
T9	43690	407	0	0
T10	2250	20	0	0
T11	5764	14	0	0
T12	148339	1722	0	0
T13	194459	633	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2925172	0	0
T1	52447	1111	0	0
T2	11716	135	0	0
T3	69678	942	0	0
T7	218452	49042	0	0
T8	215657	57908	0	0
T9	43690	400	0	0
T10	2250	21	0	0
T11	5764	100	0	0
T12	148339	1099	0	0
T13	194459	4806	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	225652	0	0
T1	52447	154	0	0
T2	11716	133	0	0
T3	69678	126	0	0
T7	218452	150	0	0
T8	215657	178	0	0
T9	43690	407	0	0
T10	2250	20	0	0
T11	5764	14	0	0
T12	148339	1722	0	0
T13	194459	633	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	225652	0	0
T1	52447	154	0	0
T2	11716	133	0	0
T3	69678	126	0	0
T7	218452	150	0	0
T8	215657	178	0	0
T9	43690	407	0	0
T10	2250	20	0	0
T11	5764	14	0	0
T12	148339	1722	0	0
T13	194459	633	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	589836	0	0
T1	52447	215	0	0
T2	11716	137	0	0
T3	69678	213	0	0
T7	218452	986	0	0
T8	215657	3298	0	0
T9	43690	416	0	0
T10	2250	20	0	0
T11	5764	22	0	0
T12	148339	2357	0	0
T13	194459	813	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	225652	0	0
T1	52447	154	0	0
T2	11716	133	0	0
T3	69678	126	0	0
T7	218452	150	0	0
T8	215657	178	0	0
T9	43690	407	0	0
T10	2250	20	0	0
T11	5764	14	0	0
T12	148339	1722	0	0
T13	194459	633	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	220970	0	0
GntImpliesValid_A	410263252	220970	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	220970	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2914363	0	0
ReadyAndValidImplyGrant_A	410263252	220970	0	0
ReqAndReadyImplyGrant_A	410263252	220970	0	0
ReqImpliesValid_A	410263252	572574	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	220970	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220970	0	0
T1	52447	140	0	0
T2	11716	128	0	0
T3	69678	115	0	0
T7	218452	149	0	0
T8	215657	151	0	0
T9	43690	396	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	1731	0	0
T13	194459	638	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220970	0	0
T1	52447	140	0	0
T2	11716	128	0	0
T3	69678	115	0	0
T7	218452	149	0	0
T8	215657	151	0	0
T9	43690	396	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	1731	0	0
T13	194459	638	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220970	0	0
T1	52447	140	0	0
T2	11716	128	0	0
T3	69678	115	0	0
T7	218452	149	0	0
T8	215657	151	0	0
T9	43690	396	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	1731	0	0
T13	194459	638	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2914363	0	0
T1	52447	1071	0	0
T2	11716	128	0	0
T3	69678	824	0	0
T7	218452	47047	0	0
T8	215657	48258	0	0
T9	43690	387	0	0
T10	2250	24	0	0
T11	5764	93	0	0
T12	148339	1333	0	0
T13	194459	4948	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220970	0	0
T1	52447	140	0	0
T2	11716	128	0	0
T3	69678	115	0	0
T7	218452	149	0	0
T8	215657	151	0	0
T9	43690	396	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	1731	0	0
T13	194459	638	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220970	0	0
T1	52447	140	0	0
T2	11716	128	0	0
T3	69678	115	0	0
T7	218452	149	0	0
T8	215657	151	0	0
T9	43690	396	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	1731	0	0
T13	194459	638	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	572574	0	0
T1	52447	188	0	0
T2	11716	134	0	0
T3	69678	147	0	0
T7	218452	3387	0	0
T8	215657	6389	0	0
T9	43690	407	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	2141	0	0
T13	194459	805	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	220970	0	0
T1	52447	140	0	0
T2	11716	128	0	0
T3	69678	115	0	0
T7	218452	149	0	0
T8	215657	151	0	0
T9	43690	396	0	0
T10	2250	23	0	0
T11	5764	13	0	0
T12	148339	1731	0	0
T13	194459	638	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	219929	0	0
GntImpliesValid_A	410263252	219929	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	219929	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2939479	0	0
ReadyAndValidImplyGrant_A	410263252	219929	0	0
ReqAndReadyImplyGrant_A	410263252	219929	0	0
ReqImpliesValid_A	410263252	567287	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	219929	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	219929	0	0
T1	52447	129	0	0
T2	11716	140	0	0
T3	69678	137	0	0
T7	218452	144	0	0
T8	215657	163	0	0
T9	43690	467	0	0
T10	2250	31	0	0
T11	5764	12	0	0
T12	148339	1755	0	0
T13	194459	610	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	219929	0	0
T1	52447	129	0	0
T2	11716	140	0	0
T3	69678	137	0	0
T7	218452	144	0	0
T8	215657	163	0	0
T9	43690	467	0	0
T10	2250	31	0	0
T11	5764	12	0	0
T12	148339	1755	0	0
T13	194459	610	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	219929	0	0
T1	52447	129	0	0
T2	11716	140	0	0
T3	69678	137	0	0
T7	218452	144	0	0
T8	215657	163	0	0
T9	43690	467	0	0
T10	2250	31	0	0
T11	5764	12	0	0
T12	148339	1755	0	0
T13	194459	610	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2939479	0	0
T1	52447	989	0	0
T2	11716	139	0	0
T3	69678	1112	0	0
T7	218452	45000	0	0
T8	215657	52002	0	0
T9	43690	462	0	0
T10	2250	32	0	0
T11	5764	103	0	0
T12	148339	779	0	0
T13	194459	4528	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	219929	0	0
T1	52447	129	0	0
T2	11716	140	0	0
T3	69678	137	0	0
T7	218452	144	0	0
T8	215657	163	0	0
T9	43690	467	0	0
T10	2250	31	0	0
T11	5764	12	0	0
T12	148339	1755	0	0
T13	194459	610	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	219929	0	0
T1	52447	129	0	0
T2	11716	140	0	0
T3	69678	137	0	0
T7	218452	144	0	0
T8	215657	163	0	0
T9	43690	467	0	0
T10	2250	31	0	0
T11	5764	12	0	0
T12	148339	1755	0	0
T13	194459	610	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	567287	0	0
T1	52447	175	0	0
T2	11716	147	0	0
T3	69678	166	0	0
T7	218452	4276	0	0
T8	215657	3446	0	0
T9	43690	474	0	0
T10	2250	31	0	0
T11	5764	21	0	0
T12	148339	2743	0	0
T13	194459	834	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	219929	0	0
T1	52447	129	0	0
T2	11716	140	0	0
T3	69678	137	0	0
T7	218452	144	0	0
T8	215657	163	0	0
T9	43690	467	0	0
T10	2250	31	0	0
T11	5764	12	0	0
T12	148339	1755	0	0
T13	194459	610	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	230214	0	0
GntImpliesValid_A	410263252	230214	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	230214	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2890671	0	0
ReadyAndValidImplyGrant_A	410263252	230214	0	0
ReqAndReadyImplyGrant_A	410263252	230214	0	0
ReqImpliesValid_A	410263252	636833	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	230214	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	230214	0	0
T1	52447	139	0	0
T2	11716	124	0	0
T3	69678	99	0	0
T7	218452	149	0	0
T8	215657	165	0	0
T9	43690	443	0	0
T10	2250	26	0	0
T11	5764	10	0	0
T12	148339	1798	0	0
T13	194459	615	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	230214	0	0
T1	52447	139	0	0
T2	11716	124	0	0
T3	69678	99	0	0
T7	218452	149	0	0
T8	215657	165	0	0
T9	43690	443	0	0
T10	2250	26	0	0
T11	5764	10	0	0
T12	148339	1798	0	0
T13	194459	615	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	230214	0	0
T1	52447	139	0	0
T2	11716	124	0	0
T3	69678	99	0	0
T7	218452	149	0	0
T8	215657	165	0	0
T9	43690	443	0	0
T10	2250	26	0	0
T11	5764	10	0	0
T12	148339	1798	0	0
T13	194459	615	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2890671	0	0
T1	52447	981	0	0
T2	11716	124	0	0
T3	69678	731	0	0
T7	218452	50707	0	0
T8	215657	50057	0	0
T9	43690	439	0	0
T10	2250	27	0	0
T11	5764	95	0	0
T12	148339	1219	0	0
T13	194459	4707	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	230214	0	0
T1	52447	139	0	0
T2	11716	124	0	0
T3	69678	99	0	0
T7	218452	149	0	0
T8	215657	165	0	0
T9	43690	443	0	0
T10	2250	26	0	0
T11	5764	10	0	0
T12	148339	1798	0	0
T13	194459	615	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	230214	0	0
T1	52447	139	0	0
T2	11716	124	0	0
T3	69678	99	0	0
T7	218452	149	0	0
T8	215657	165	0	0
T9	43690	443	0	0
T10	2250	26	0	0
T11	5764	10	0	0
T12	148339	1798	0	0
T13	194459	615	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	636833	0	0
T1	52447	228	0	0
T2	11716	130	0	0
T3	69678	121	0	0
T7	218452	4037	0	0
T8	215657	4721	0	0
T9	43690	449	0	0
T10	2250	26	0	0
T11	5764	10	0	0
T12	148339	2389	0	0
T13	194459	777	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	230214	0	0
T1	52447	139	0	0
T2	11716	124	0	0
T3	69678	99	0	0
T7	218452	149	0	0
T8	215657	165	0	0
T9	43690	443	0	0
T10	2250	26	0	0
T11	5764	10	0	0
T12	148339	1798	0	0
T13	194459	615	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	217271	0	0
GntImpliesValid_A	410263252	217271	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	217271	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2908411	0	0
ReadyAndValidImplyGrant_A	410263252	217271	0	0
ReqAndReadyImplyGrant_A	410263252	217271	0	0
ReqImpliesValid_A	410263252	560760	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	217271	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217271	0	0
T1	52447	168	0	0
T2	11716	113	0	0
T3	69678	118	0	0
T7	218452	158	0	0
T8	215657	181	0	0
T9	43690	447	0	0
T10	2250	21	0	0
T11	5764	12	0	0
T12	148339	1734	0	0
T13	194459	575	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217271	0	0
T1	52447	168	0	0
T2	11716	113	0	0
T3	69678	118	0	0
T7	218452	158	0	0
T8	215657	181	0	0
T9	43690	447	0	0
T10	2250	21	0	0
T11	5764	12	0	0
T12	148339	1734	0	0
T13	194459	575	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217271	0	0
T1	52447	168	0	0
T2	11716	113	0	0
T3	69678	118	0	0
T7	218452	158	0	0
T8	215657	181	0	0
T9	43690	447	0	0
T10	2250	21	0	0
T11	5764	12	0	0
T12	148339	1734	0	0
T13	194459	575	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2908411	0	0
T1	52447	1160	0	0
T2	11716	118	0	0
T3	69678	858	0	0
T7	218452	47655	0	0
T8	215657	59994	0	0
T9	43690	444	0	0
T10	2250	22	0	0
T11	5764	112	0	0
T12	148339	867	0	0
T13	194459	4172	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217271	0	0
T1	52447	168	0	0
T2	11716	113	0	0
T3	69678	118	0	0
T7	218452	158	0	0
T8	215657	181	0	0
T9	43690	447	0	0
T10	2250	21	0	0
T11	5764	12	0	0
T12	148339	1734	0	0
T13	194459	575	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217271	0	0
T1	52447	168	0	0
T2	11716	113	0	0
T3	69678	118	0	0
T7	218452	158	0	0
T8	215657	181	0	0
T9	43690	447	0	0
T10	2250	21	0	0
T11	5764	12	0	0
T12	148339	1734	0	0
T13	194459	575	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	560760	0	0
T1	52447	260	0	0
T2	11716	114	0	0
T3	69678	174	0	0
T7	218452	2642	0	0
T8	215657	4505	0	0
T9	43690	452	0	0
T10	2250	21	0	0
T11	5764	34	0	0
T12	148339	2613	0	0
T13	194459	721	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	217271	0	0
T1	52447	168	0	0
T2	11716	113	0	0
T3	69678	118	0	0
T7	218452	158	0	0
T8	215657	181	0	0
T9	43690	447	0	0
T10	2250	21	0	0
T11	5764	12	0	0
T12	148339	1734	0	0
T13	194459	575	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	241795	0	0
GntImpliesValid_A	410263252	241795	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	241795	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	3006905	0	0
ReadyAndValidImplyGrant_A	410263252	241795	0	0
ReqAndReadyImplyGrant_A	410263252	241795	0	0
ReqImpliesValid_A	410263252	578474	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	241795	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	241795	0	0
T1	52447	196	0	0
T2	11716	146	0	0
T3	69678	226	0	0
T7	218452	167	0	0
T8	215657	157	0	0
T9	43690	471	0	0
T10	2250	17	0	0
T11	5764	16	0	0
T12	148339	2335	0	0
T13	194459	647	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	241795	0	0
T1	52447	196	0	0
T2	11716	146	0	0
T3	69678	226	0	0
T7	218452	167	0	0
T8	215657	157	0	0
T9	43690	471	0	0
T10	2250	17	0	0
T11	5764	16	0	0
T12	148339	2335	0	0
T13	194459	647	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	241795	0	0
T1	52447	196	0	0
T2	11716	146	0	0
T3	69678	226	0	0
T7	218452	167	0	0
T8	215657	157	0	0
T9	43690	471	0	0
T10	2250	17	0	0
T11	5764	16	0	0
T12	148339	2335	0	0
T13	194459	647	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	3006905	0	0
T1	52447	1386	0	0
T2	11716	146	0	0
T3	69678	1786	0	0
T7	218452	56135	0	0
T8	215657	46443	0	0
T9	43690	461	0	0
T10	2250	18	0	0
T11	5764	125	0	0
T12	148339	1696	0	0
T13	194459	4840	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	241795	0	0
T1	52447	196	0	0
T2	11716	146	0	0
T3	69678	226	0	0
T7	218452	167	0	0
T8	215657	157	0	0
T9	43690	471	0	0
T10	2250	17	0	0
T11	5764	16	0	0
T12	148339	2335	0	0
T13	194459	647	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	241795	0	0
T1	52447	196	0	0
T2	11716	146	0	0
T3	69678	226	0	0
T7	218452	167	0	0
T8	215657	157	0	0
T9	43690	471	0	0
T10	2250	17	0	0
T11	5764	16	0	0
T12	148339	2335	0	0
T13	194459	647	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	578474	0	0
T1	52447	260	0	0
T2	11716	152	0	0
T3	69678	289	0	0
T7	218452	4063	0	0
T8	215657	4566	0	0
T9	43690	483	0	0
T10	2250	17	0	0
T11	5764	16	0	0
T12	148339	2985	0	0
T13	194459	922	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	241795	0	0
T1	52447	196	0	0
T2	11716	146	0	0
T3	69678	226	0	0
T7	218452	167	0	0
T8	215657	157	0	0
T9	43690	471	0	0
T10	2250	17	0	0
T11	5764	16	0	0
T12	148339	2335	0	0
T13	194459	647	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	224689	0	0
GntImpliesValid_A	410263252	224689	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	224689	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2905960	0	0
ReadyAndValidImplyGrant_A	410263252	224689	0	0
ReqAndReadyImplyGrant_A	410263252	224689	0	0
ReqImpliesValid_A	410263252	561009	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	224689	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	224689	0	0
T1	52447	139	0	0
T2	11716	136	0	0
T3	69678	126	0	0
T7	218452	141	0	0
T8	215657	149	0	0
T9	43690	429	0	0
T10	2250	15	0	0
T11	5764	14	0	0
T12	148339	1977	0	0
T13	194459	694	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	224689	0	0
T1	52447	139	0	0
T2	11716	136	0	0
T3	69678	126	0	0
T7	218452	141	0	0
T8	215657	149	0	0
T9	43690	429	0	0
T10	2250	15	0	0
T11	5764	14	0	0
T12	148339	1977	0	0
T13	194459	694	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	224689	0	0
T1	52447	139	0	0
T2	11716	136	0	0
T3	69678	126	0	0
T7	218452	141	0	0
T8	215657	149	0	0
T9	43690	429	0	0
T10	2250	15	0	0
T11	5764	14	0	0
T12	148339	1977	0	0
T13	194459	694	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2905960	0	0
T1	52447	1027	0	0
T2	11716	137	0	0
T3	69678	903	0	0
T7	218452	42823	0	0
T8	215657	46878	0	0
T9	43690	423	0	0
T10	2250	16	0	0
T11	5764	93	0	0
T12	148339	1650	0	0
T13	194459	5024	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	224689	0	0
T1	52447	139	0	0
T2	11716	136	0	0
T3	69678	126	0	0
T7	218452	141	0	0
T8	215657	149	0	0
T9	43690	429	0	0
T10	2250	15	0	0
T11	5764	14	0	0
T12	148339	1977	0	0
T13	194459	694	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	224689	0	0
T1	52447	139	0	0
T2	11716	136	0	0
T3	69678	126	0	0
T7	218452	141	0	0
T8	215657	149	0	0
T9	43690	429	0	0
T10	2250	15	0	0
T11	5764	14	0	0
T12	148339	1977	0	0
T13	194459	694	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	561009	0	0
T1	52447	217	0	0
T2	11716	140	0	0
T3	69678	176	0	0
T7	218452	2203	0	0
T8	215657	5154	0	0
T9	43690	437	0	0
T10	2250	15	0	0
T11	5764	31	0	0
T12	148339	2315	0	0
T13	194459	967	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	224689	0	0
T1	52447	139	0	0
T2	11716	136	0	0
T3	69678	126	0	0
T7	218452	141	0	0
T8	215657	149	0	0
T9	43690	429	0	0
T10	2250	15	0	0
T11	5764	14	0	0
T12	148339	1977	0	0
T13	194459	694	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	206083	0	0
GntImpliesValid_A	410263252	206083	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	206083	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2790032	0	0
ReadyAndValidImplyGrant_A	410263252	206083	0	0
ReqAndReadyImplyGrant_A	410263252	206083	0	0
ReqImpliesValid_A	410263252	498817	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	206083	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	206083	0	0
T1	52447	160	0	0
T2	11716	141	0	0
T3	69678	117	0	0
T7	218452	145	0	0
T8	215657	155	0	0
T9	43690	457	0	0
T10	2250	28	0	0
T11	5764	14	0	0
T12	148339	2111	0	0
T13	194459	613	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	206083	0	0
T1	52447	160	0	0
T2	11716	141	0	0
T3	69678	117	0	0
T7	218452	145	0	0
T8	215657	155	0	0
T9	43690	457	0	0
T10	2250	28	0	0
T11	5764	14	0	0
T12	148339	2111	0	0
T13	194459	613	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	206083	0	0
T1	52447	160	0	0
T2	11716	141	0	0
T3	69678	117	0	0
T7	218452	145	0	0
T8	215657	155	0	0
T9	43690	457	0	0
T10	2250	28	0	0
T11	5764	14	0	0
T12	148339	2111	0	0
T13	194459	613	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2790032	0	0
T1	52447	1283	0	0
T2	11716	138	0	0
T3	69678	799	0	0
T7	218452	45296	0	0
T8	215657	45880	0	0
T9	43690	448	0	0
T10	2250	29	0	0
T11	5764	97	0	0
T12	148339	1756	0	0
T13	194459	4467	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	206083	0	0
T1	52447	160	0	0
T2	11716	141	0	0
T3	69678	117	0	0
T7	218452	145	0	0
T8	215657	155	0	0
T9	43690	457	0	0
T10	2250	28	0	0
T11	5764	14	0	0
T12	148339	2111	0	0
T13	194459	613	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	206083	0	0
T1	52447	160	0	0
T2	11716	141	0	0
T3	69678	117	0	0
T7	218452	145	0	0
T8	215657	155	0	0
T9	43690	457	0	0
T10	2250	28	0	0
T11	5764	14	0	0
T12	148339	2111	0	0
T13	194459	613	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	498817	0	0
T1	52447	200	0	0
T2	11716	150	0	0
T3	69678	132	0	0
T7	218452	1585	0	0
T8	215657	3581	0	0
T9	43690	468	0	0
T10	2250	28	0	0
T11	5764	18	0	0
T12	148339	2478	0	0
T13	194459	797	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	206083	0	0
T1	52447	160	0	0
T2	11716	141	0	0
T3	69678	117	0	0
T7	218452	145	0	0
T8	215657	155	0	0
T9	43690	457	0	0
T10	2250	28	0	0
T11	5764	14	0	0
T12	148339	2111	0	0
T13	194459	613	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	222176	0	0
GntImpliesValid_A	410263252	222176	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	222176	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2841317	0	0
ReadyAndValidImplyGrant_A	410263252	222176	0	0
ReqAndReadyImplyGrant_A	410263252	222176	0	0
ReqImpliesValid_A	410263252	550627	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	222176	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222176	0	0
T1	52447	150	0	0
T2	11716	131	0	0
T3	69678	114	0	0
T7	218452	141	0	0
T8	215657	176	0	0
T9	43690	466	0	0
T10	2250	24	0	0
T11	5764	11	0	0
T12	148339	2015	0	0
T13	194459	638	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222176	0	0
T1	52447	150	0	0
T2	11716	131	0	0
T3	69678	114	0	0
T7	218452	141	0	0
T8	215657	176	0	0
T9	43690	466	0	0
T10	2250	24	0	0
T11	5764	11	0	0
T12	148339	2015	0	0
T13	194459	638	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222176	0	0
T1	52447	150	0	0
T2	11716	131	0	0
T3	69678	114	0	0
T7	218452	141	0	0
T8	215657	176	0	0
T9	43690	466	0	0
T10	2250	24	0	0
T11	5764	11	0	0
T12	148339	2015	0	0
T13	194459	638	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2841317	0	0
T1	52447	1047	0	0
T2	11716	131	0	0
T3	69678	825	0	0
T7	218452	47546	0	0
T8	215657	53775	0	0
T9	43690	458	0	0
T10	2250	25	0	0
T11	5764	87	0	0
T12	148339	991	0	0
T13	194459	4853	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222176	0	0
T1	52447	150	0	0
T2	11716	131	0	0
T3	69678	114	0	0
T7	218452	141	0	0
T8	215657	176	0	0
T9	43690	466	0	0
T10	2250	24	0	0
T11	5764	11	0	0
T12	148339	2015	0	0
T13	194459	638	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222176	0	0
T1	52447	150	0	0
T2	11716	131	0	0
T3	69678	114	0	0
T7	218452	141	0	0
T8	215657	176	0	0
T9	43690	466	0	0
T10	2250	24	0	0
T11	5764	11	0	0
T12	148339	2015	0	0
T13	194459	638	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	550627	0	0
T1	52447	219	0	0
T2	11716	137	0	0
T3	69678	135	0	0
T7	218452	1738	0	0
T8	215657	2849	0	0
T9	43690	476	0	0
T10	2250	24	0	0
T11	5764	11	0	0
T12	148339	3050	0	0
T13	194459	881	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	222176	0	0
T1	52447	150	0	0
T2	11716	131	0	0
T3	69678	114	0	0
T7	218452	141	0	0
T8	215657	176	0	0
T9	43690	466	0	0
T10	2250	24	0	0
T11	5764	11	0	0
T12	148339	2015	0	0
T13	194459	638	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	227110	0	0
GntImpliesValid_A	410263252	227110	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	227110	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2872703	0	0
ReadyAndValidImplyGrant_A	410263252	227110	0	0
ReqAndReadyImplyGrant_A	410263252	227110	0	0
ReqImpliesValid_A	410263252	561347	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	227110	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	227110	0	0
T1	52447	156	0	0
T2	11716	127	0	0
T3	69678	138	0	0
T7	218452	134	0	0
T8	215657	154	0	0
T9	43690	887	0	0
T10	2250	21	0	0
T11	5764	18	0	0
T12	148339	1787	0	0
T13	194459	623	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	227110	0	0
T1	52447	156	0	0
T2	11716	127	0	0
T3	69678	138	0	0
T7	218452	134	0	0
T8	215657	154	0	0
T9	43690	887	0	0
T10	2250	21	0	0
T11	5764	18	0	0
T12	148339	1787	0	0
T13	194459	623	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	227110	0	0
T1	52447	156	0	0
T2	11716	127	0	0
T3	69678	138	0	0
T7	218452	134	0	0
T8	215657	154	0	0
T9	43690	887	0	0
T10	2250	21	0	0
T11	5764	18	0	0
T12	148339	1787	0	0
T13	194459	623	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2872703	0	0
T1	52447	1137	0	0
T2	11716	130	0	0
T3	69678	1024	0	0
T7	218452	39407	0	0
T8	215657	49630	0	0
T9	43690	818	0	0
T10	2250	22	0	0
T11	5764	131	0	0
T12	148339	1205	0	0
T13	194459	4590	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	227110	0	0
T1	52447	156	0	0
T2	11716	127	0	0
T3	69678	138	0	0
T7	218452	134	0	0
T8	215657	154	0	0
T9	43690	887	0	0
T10	2250	21	0	0
T11	5764	18	0	0
T12	148339	1787	0	0
T13	194459	623	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	227110	0	0
T1	52447	156	0	0
T2	11716	127	0	0
T3	69678	138	0	0
T7	218452	134	0	0
T8	215657	154	0	0
T9	43690	887	0	0
T10	2250	21	0	0
T11	5764	18	0	0
T12	148339	1787	0	0
T13	194459	623	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	561347	0	0
T1	52447	202	0	0
T2	11716	130	0	0
T3	69678	174	0	0
T7	218452	3557	0	0
T8	215657	1963	0	0
T9	43690	958	0	0
T10	2250	21	0	0
T11	5764	28	0	0
T12	148339	2381	0	0
T13	194459	829	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	227110	0	0
T1	52447	156	0	0
T2	11716	127	0	0
T3	69678	138	0	0
T7	218452	134	0	0
T8	215657	154	0	0
T9	43690	887	0	0
T10	2250	21	0	0
T11	5764	18	0	0
T12	148339	1787	0	0
T13	194459	623	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	214107	0	0
GntImpliesValid_A	410263252	214107	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	214107	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	2902589	0	0
ReadyAndValidImplyGrant_A	410263252	214107	0	0
ReqAndReadyImplyGrant_A	410263252	214107	0	0
ReqImpliesValid_A	410263252	555919	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	0	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	214107	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	214107	0	0
T1	52447	150	0	0
T2	11716	129	0	0
T3	69678	131	0	0
T7	218452	142	0	0
T8	215657	154	0	0
T9	43690	399	0	0
T10	2250	30	0	0
T11	5764	12	0	0
T12	148339	2172	0	0
T13	194459	640	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	214107	0	0
T1	52447	150	0	0
T2	11716	129	0	0
T3	69678	131	0	0
T7	218452	142	0	0
T8	215657	154	0	0
T9	43690	399	0	0
T10	2250	30	0	0
T11	5764	12	0	0
T12	148339	2172	0	0
T13	194459	640	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	214107	0	0
T1	52447	150	0	0
T2	11716	129	0	0
T3	69678	131	0	0
T7	218452	142	0	0
T8	215657	154	0	0
T9	43690	399	0	0
T10	2250	30	0	0
T11	5764	12	0	0
T12	148339	2172	0	0
T13	194459	640	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2902589	0	0
T1	52447	1000	0	0
T2	11716	133	0	0
T3	69678	954	0	0
T7	218452	44120	0	0
T8	215657	52136	0	0
T9	43690	388	0	0
T10	2250	30	0	0
T11	5764	96	0	0
T12	148339	1056	0	0
T13	194459	4758	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	214107	0	0
T1	52447	150	0	0
T2	11716	129	0	0
T3	69678	131	0	0
T7	218452	142	0	0
T8	215657	154	0	0
T9	43690	399	0	0
T10	2250	30	0	0
T11	5764	12	0	0
T12	148339	2172	0	0
T13	194459	640	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	214107	0	0
T1	52447	150	0	0
T2	11716	129	0	0
T3	69678	131	0	0
T7	218452	142	0	0
T8	215657	154	0	0
T9	43690	399	0	0
T10	2250	30	0	0
T11	5764	12	0	0
T12	148339	2172	0	0
T13	194459	640	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	555919	0	0
T1	52447	210	0	0
T2	11716	131	0	0
T3	69678	167	0	0
T7	218452	3627	0	0
T8	215657	2061	0	0
T9	43690	412	0	0
T10	2250	31	0	0
T11	5764	20	0	0
T12	148339	3300	0	0
T13	194459	859	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	214107	0	0
T1	52447	150	0	0
T2	11716	129	0	0
T3	69678	131	0	0
T7	218452	142	0	0
T8	215657	154	0	0
T9	43690	399	0	0
T10	2250	30	0	0
T11	5764	12	0	0
T12	148339	2172	0	0
T13	194459	640	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	876446	0	0
GntImpliesValid_A	410263252	876446	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	876446	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	10977641	0	0
ReadyAndValidImplyGrant_A	410263252	876446	0	0
ReqAndReadyImplyGrant_A	410263252	876446	0	0
ReqImpliesValid_A	410263252	2273927	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	17366	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	876446	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	876446	0	0
T1	52447	633	0	0
T2	11716	534	0	0
T3	69678	474	0	0
T7	218452	570	0	0
T8	215657	601	0	0
T9	43690	2088	0	0
T10	2250	118	0	0
T11	5764	43	0	0
T12	148339	8604	0	0
T13	194459	2506	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	876446	0	0
T1	52447	633	0	0
T2	11716	534	0	0
T3	69678	474	0	0
T7	218452	570	0	0
T8	215657	601	0	0
T9	43690	2088	0	0
T10	2250	118	0	0
T11	5764	43	0	0
T12	148339	8604	0	0
T13	194459	2506	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	876446	0	0
T1	52447	633	0	0
T2	11716	534	0	0
T3	69678	474	0	0
T7	218452	570	0	0
T8	215657	601	0	0
T9	43690	2088	0	0
T10	2250	118	0	0
T11	5764	43	0	0
T12	148339	8604	0	0
T13	194459	2506	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	10977641	0	0
T1	52447	4161	0	0
T2	11716	6	0	0
T3	69678	3040	0	0
T7	218452	171232	0	0
T8	215657	201984	0	0
T9	43690	2	0	0
T10	2250	1	0	0
T11	5764	316	0	0
T12	148339	12	0	0
T13	194459	16119	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	876446	0	0
T1	52447	633	0	0
T2	11716	534	0	0
T3	69678	474	0	0
T7	218452	570	0	0
T8	215657	601	0	0
T9	43690	2088	0	0
T10	2250	118	0	0
T11	5764	43	0	0
T12	148339	8604	0	0
T13	194459	2506	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	876446	0	0
T1	52447	633	0	0
T2	11716	534	0	0
T3	69678	474	0	0
T7	218452	570	0	0
T8	215657	601	0	0
T9	43690	2088	0	0
T10	2250	118	0	0
T11	5764	43	0	0
T12	148339	8604	0	0
T13	194459	2506	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	2273927	0	0
T1	52447	1045	0	0
T2	11716	534	0	0
T3	69678	643	0	0
T7	218452	20275	0	0
T8	215657	20215	0	0
T9	43690	2088	0	0
T10	2250	118	0	0
T11	5764	78	0	0
T12	148339	8604	0	0
T13	194459	4222	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	17366	0	900
T1	52447	1	0	1
T2	11716	6	0	1
T3	69678	0	0	1
T7	218452	1	0	1
T8	215657	0	0	1
T9	43690	33	0	1
T10	2250	0	0	1
T11	5764	0	0	1
T12	148339	685	0	1
T13	194459	0	0	1
T14	0	2	0	0
T15	0	12	0	0
T16	0	50	0	0
T17	0	6	0	0
T18	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	876446	0	0
T1	52447	633	0	0
T2	11716	534	0	0
T3	69678	474	0	0
T7	218452	570	0	0
T8	215657	601	0	0
T9	43690	2088	0	0
T10	2250	118	0	0
T11	5764	43	0	0
T12	148339	8604	0	0
T13	194459	2506	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410263252	410141146	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410263252	873588	0	0
GntImpliesValid_A	410263252	873588	0	0
GrantKnown_A	410263252	410141146	0	0
IdxKnown_A	410263252	410141146	0	0
IndexIsCorrect_A	410263252	873588	0	0
LockArbDecision_A	410263252	0	0	0
NoReadyValidNoGrant_A	410263252	344171187	0	0
ReadyAndValidImplyGrant_A	410263252	873588	0	0
ReqAndReadyImplyGrant_A	410263252	873588	0	0
ReqImpliesValid_A	410263252	12786223	0	0
ReqStaysHighUntilGranted0_M	410263252	0	0	0
RoundRobin_A	410263252	32963	0	900
ValidKnown_A	410263252	410141146	0	0
gen_data_port_assertion.DataFlow_A	410263252	873588	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	873588	0	0
T1	52447	580	0	0
T2	11716	551	0	0
T3	69678	513	0	0
T7	218452	548	0	0
T8	215657	611	0	0
T9	43690	3660	0	0
T10	2250	97	0	0
T11	5764	50	0	0
T12	148339	7442	0	0
T13	194459	2429	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	873588	0	0
T1	52447	580	0	0
T2	11716	551	0	0
T3	69678	513	0	0
T7	218452	548	0	0
T8	215657	611	0	0
T9	43690	3660	0	0
T10	2250	97	0	0
T11	5764	50	0	0
T12	148339	7442	0	0
T13	194459	2429	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	873588	0	0
T1	52447	580	0	0
T2	11716	551	0	0
T3	69678	513	0	0
T7	218452	548	0	0
T8	215657	611	0	0
T9	43690	3660	0	0
T10	2250	97	0	0
T11	5764	50	0	0
T12	148339	7442	0	0
T13	194459	2429	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	344171187	0	0
T1	52447	43176	0	0
T2	11716	1	0	0
T3	69678	58347	0	0
T7	218452	190040	0	0
T8	215657	193603	0	0
T9	43690	1	0	0
T10	2250	1	0	0
T11	5764	4796	0	0
T12	148339	1	0	0
T13	194459	159672	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	873588	0	0
T1	52447	580	0	0
T2	11716	551	0	0
T3	69678	513	0	0
T7	218452	548	0	0
T8	215657	611	0	0
T9	43690	3660	0	0
T10	2250	97	0	0
T11	5764	50	0	0
T12	148339	7442	0	0
T13	194459	2429	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	873588	0	0
T1	52447	580	0	0
T2	11716	551	0	0
T3	69678	513	0	0
T7	218452	548	0	0
T8	215657	611	0	0
T9	43690	3660	0	0
T10	2250	97	0	0
T11	5764	50	0	0
T12	148339	7442	0	0
T13	194459	2429	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	12786223	0	0
T1	52447	5015	0	0
T2	11716	551	0	0
T3	69678	3889	0	0
T7	218452	189098	0	0
T8	215657	216759	0	0
T9	43690	3660	0	0
T10	2250	97	0	0
T11	5764	434	0	0
T12	148339	7442	0	0
T13	194459	19349	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	32963	0	900
T2	11716	4	0	1
T3	69678	0	0	1
T7	218452	0	0	1
T8	215657	0	0	1
T9	43690	591	0	1
T10	2250	1	0	1
T11	5764	0	0	1
T12	148339	348	0	1
T13	194459	2	0	1
T14	0	6	0	0
T15	0	8	0	0
T16	0	280	0	0
T17	0	429	0	0
T18	0	3	0	0
T19	113466	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	410141146	0	0
T1	52447	52387	0	0
T2	11716	11269	0	0
T3	69678	69607	0	0
T7	218452	218445	0	0
T8	215657	215652	0	0
T9	43690	43548	0	0
T10	2250	2238	0	0
T11	5764	5706	0	0
T12	148339	147727	0	0
T13	194459	194261	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410263252	873588	0	0
T1	52447	580	0	0
T2	11716	551	0	0
T3	69678	513	0	0
T7	218452	548	0	0
T8	215657	611	0	0
T9	43690	3660	0	0
T10	2250	97	0	0
T11	5764	50	0	0
T12	148339	7442	0	0
T13	194459	2429	0	0