Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1461328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

231626

1

T1

13

T2

340

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	575402	1			T1	42		T2	775		T3	48
values[0x0]	543124	1			T1	36		T2	767		T3	3
values[0x1]	574428	1			T1	26		T2	767		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1129200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

563754

1

T1

29

T2

773

T3

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27052	1			T1	2		T2	8		T7	6
valid_sources[0x01]	25871	1			T2	45		T3	2		T7	4
valid_sources[0x02]	26811	1			T1	1		T2	53		T3	2
valid_sources[0x03]	26352	1			T1	6		T2	50		T3	2
valid_sources[0x04]	26470	1			T2	25		T3	2		T8	8
valid_sources[0x05]	26468	1			T2	85		T3	1		T8	5
valid_sources[0x06]	25763	1			T1	1		T2	34		T3	3
valid_sources[0x07]	26187	1			T2	25		T3	4		T7	4
valid_sources[0x08]	26860	1			T1	5		T2	18		T3	3
valid_sources[0x09]	25933	1			T1	1		T2	29		T3	1
valid_sources[0x0a]	27020	1			T2	56		T3	3		T8	5
valid_sources[0x0b]	26447	1			T2	48		T7	6		T8	1
valid_sources[0x0c]	26007	1			T2	73		T3	2		T7	2
valid_sources[0x0d]	27221	1			T2	44		T3	3		T8	4
valid_sources[0x0e]	26823	1			T1	1		T2	35		T8	2
valid_sources[0x0f]	25524	1			T1	2		T2	25		T3	1
valid_sources[0x10]	26100	1			T2	49		T8	8		T10	2
valid_sources[0x11]	26384	1			T2	8		T8	11		T10	4
valid_sources[0x12]	26393	1			T1	3		T2	63		T3	2
valid_sources[0x13]	25990	1			T1	4		T2	46		T3	5
valid_sources[0x14]	26307	1			T2	50		T8	11		T12	41
valid_sources[0x15]	25715	1			T1	3		T3	2		T8	2
valid_sources[0x16]	26066	1			T2	31		T3	1		T10	2
valid_sources[0x17]	27076	1			T2	37		T3	2		T7	1
valid_sources[0x18]	26798	1			T1	6		T2	25		T3	2
valid_sources[0x19]	26003	1			T1	2		T2	26		T8	2
valid_sources[0x1a]	27791	1			T2	37		T3	1		T8	7
valid_sources[0x1b]	26215	1			T3	1		T8	7		T10	3
valid_sources[0x1c]	25911	1			T1	8		T2	19		T3	3
valid_sources[0x1d]	25539	1			T2	10		T3	3		T8	18
valid_sources[0x1e]	26266	1			T1	1		T2	82		T7	31
valid_sources[0x1f]	26274	1			T1	2		T2	33		T8	4
valid_sources[0x20]	26455	1			T1	4		T2	37		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24285

1

T1

1

T2

25

T3

2

values[0x0]

all_enables

biggest_size

182805

1

T1

11

T2

282

T3

2

values[0x1]

all_enables

biggest_size

24536

1

T1

1

T2

33

T3

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1471064	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239571

1

T1

26

T2

301

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	585696	1			T1	59		T2	758		T3	40
values[0x0]	538361	1			T1	67		T2	702		T3	5
values[0x1]	586578	1			T1	59		T2	771		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1128721	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

581914

1

T1

59

T2

768

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27041	1			T1	5		T2	94		T3	3
valid_sources[0x01]	26212	1			T1	5		T2	18		T3	2
valid_sources[0x02]	27102	1			T1	3		T2	20		T7	2
valid_sources[0x03]	26540	1			T1	6		T2	25		T3	2
valid_sources[0x04]	26589	1			T1	1		T2	50		T7	1
valid_sources[0x05]	26308	1			T2	31		T3	2		T7	1
valid_sources[0x06]	27421	1			T1	4		T2	41		T7	1
valid_sources[0x07]	26789	1			T1	6		T2	8		T3	2
valid_sources[0x08]	27124	1			T1	8		T2	11		T3	2
valid_sources[0x09]	27923	1			T1	1		T2	24		T8	5
valid_sources[0x0a]	26185	1			T1	4		T2	64		T3	3
valid_sources[0x0b]	26866	1			T1	3		T2	42		T3	1
valid_sources[0x0c]	26349	1			T1	3		T2	33		T3	1
valid_sources[0x0d]	26324	1			T1	1		T2	13		T3	1
valid_sources[0x0e]	27063	1			T1	4		T2	27		T3	1
valid_sources[0x0f]	27227	1			T1	2		T2	51		T3	1
valid_sources[0x10]	26178	1			T1	6		T2	37		T7	1
valid_sources[0x11]	26586	1			T2	31		T8	4		T11	3
valid_sources[0x12]	26936	1			T2	88		T8	4		T12	36
valid_sources[0x13]	26494	1			T1	4		T2	38		T3	3
valid_sources[0x14]	26452	1			T1	1		T2	60		T3	2
valid_sources[0x15]	26283	1			T1	3		T2	36		T3	1
valid_sources[0x16]	27335	1			T1	2		T2	22		T3	3
valid_sources[0x17]	26916	1			T1	1		T2	41		T7	3
valid_sources[0x18]	26428	1			T1	5		T2	27		T8	4
valid_sources[0x19]	26853	1			T1	2		T2	15		T7	4
valid_sources[0x1a]	27126	1			T1	5		T2	28		T3	2
valid_sources[0x1b]	26589	1			T1	4		T2	42		T7	1
valid_sources[0x1c]	26329	1			T1	4		T2	37		T3	3
valid_sources[0x1d]	26278	1			T1	1		T2	23		T3	3
valid_sources[0x1e]	26488	1			T2	100		T3	1		T7	3
valid_sources[0x1f]	27193	1			T1	3		T2	28		T3	2
valid_sources[0x20]	27048	1			T1	1		T2	9		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25293

1

T1

4

T2

24

T3

6

values[0x0]

all_enables

biggest_size

188955

1

T1

20

T2

252

T3

1

values[0x1]

all_enables

biggest_size

25323

1

T1

2

T2

25

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1472221	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

234749

1

T1

25

T2

363

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	580283	1			T1	41		T2	905		T3	36
values[0x0]	547328	1			T1	45		T2	907		T3	10
values[0x1]	579359	1			T1	38		T2	886		T3	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1138403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

568567

1

T1

42

T2

907

T3

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26255	1			T1	1		T2	52		T3	1
valid_sources[0x01]	26713	1			T1	2		T2	64		T3	1
valid_sources[0x02]	26885	1			T1	1		T2	64		T3	3
valid_sources[0x03]	27083	1			T2	70		T3	3		T7	2
valid_sources[0x04]	26889	1			T1	5		T2	38		T3	2
valid_sources[0x05]	26635	1			T1	1		T2	29		T3	1
valid_sources[0x06]	26983	1			T1	1		T2	20		T8	8
valid_sources[0x07]	26602	1			T1	1		T2	56		T7	1
valid_sources[0x08]	26290	1			T1	4		T2	21		T7	6
valid_sources[0x09]	26248	1			T1	5		T2	5		T3	1
valid_sources[0x0a]	25840	1			T1	2		T2	18		T7	7
valid_sources[0x0b]	27178	1			T1	3		T2	68		T3	2
valid_sources[0x0c]	26748	1			T1	2		T2	54		T3	2
valid_sources[0x0d]	27205	1			T1	2		T2	24		T3	2
valid_sources[0x0e]	26364	1			T2	16		T7	1		T9	1
valid_sources[0x0f]	27716	1			T1	4		T2	56		T3	1
valid_sources[0x10]	27004	1			T1	2		T2	70		T3	3
valid_sources[0x11]	26104	1			T1	2		T2	18		T3	2
valid_sources[0x12]	26700	1			T1	2		T2	38		T3	1
valid_sources[0x13]	26673	1			T2	57		T3	1		T7	3
valid_sources[0x14]	26052	1			T1	4		T2	35		T3	2
valid_sources[0x15]	26342	1			T1	3		T2	25		T3	1
valid_sources[0x16]	26373	1			T1	1		T2	26		T7	3
valid_sources[0x17]	27320	1			T1	5		T2	83		T8	2
valid_sources[0x18]	26289	1			T2	26		T3	3		T7	1
valid_sources[0x19]	26036	1			T2	12		T3	1		T7	1
valid_sources[0x1a]	26369	1			T1	3		T2	36		T3	4
valid_sources[0x1b]	26132	1			T1	3		T2	46		T7	2
valid_sources[0x1c]	26687	1			T1	1		T2	88		T3	3
valid_sources[0x1d]	26636	1			T1	2		T2	21		T3	4
valid_sources[0x1e]	26894	1			T1	1		T2	37		T3	1
valid_sources[0x1f]	26121	1			T1	4		T2	53		T3	3
valid_sources[0x20]	26622	1			T1	3		T2	8		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24817

1

T1

3

T2

41

T7

2

values[0x0]

all_enables

biggest_size

185055

1

T1

20

T2

288

T3

3

values[0x1]

all_enables

biggest_size

24877

1

T1

2

T2

34

T3

2