Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1379329 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 218802 1 T1 1024 T2 1358 T3 26


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 543933 1 T1 2632 T2 3169 T3 56
values[0x0] 512237 1 T1 2560 T2 3135 T3 54
values[0x1] 541961 1 T1 2559 T2 3237 T3 68


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1066655 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 531476 1 T1 2514 T2 3152 T3 72


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25122 1 T1 100 T2 173 T3 1
valid_sources[0x01] 24701 1 T1 104 T2 182 T10 93
valid_sources[0x02] 25749 1 T1 155 T2 117 T3 9
valid_sources[0x03] 24816 1 T1 125 T2 129 T3 2
valid_sources[0x04] 24560 1 T1 109 T2 125 T3 2
valid_sources[0x05] 25250 1 T1 106 T2 158 T3 3
valid_sources[0x06] 25988 1 T1 116 T2 177 T10 123
valid_sources[0x07] 25175 1 T1 119 T2 160 T9 1
valid_sources[0x08] 24191 1 T1 119 T2 109 T3 2
valid_sources[0x09] 25374 1 T1 99 T2 127 T9 2
valid_sources[0x0a] 25447 1 T1 128 T2 116 T3 4
valid_sources[0x0b] 24203 1 T1 113 T2 141 T3 1
valid_sources[0x0c] 25002 1 T1 126 T2 159 T9 1
valid_sources[0x0d] 24329 1 T1 138 T2 130 T10 121
valid_sources[0x0e] 25744 1 T1 110 T2 164 T9 4
valid_sources[0x0f] 25598 1 T1 135 T2 150 T9 1
valid_sources[0x10] 24298 1 T1 146 T2 117 T3 2
valid_sources[0x11] 25083 1 T1 117 T2 121 T10 69
valid_sources[0x12] 24677 1 T1 94 T2 157 T3 2
valid_sources[0x13] 25356 1 T1 108 T2 174 T3 3
valid_sources[0x14] 24332 1 T1 119 T2 159 T9 8
valid_sources[0x15] 24481 1 T1 113 T2 207 T9 1
valid_sources[0x16] 24962 1 T1 129 T2 101 T3 9
valid_sources[0x17] 24959 1 T1 141 T2 139 T3 3
valid_sources[0x18] 24284 1 T1 135 T2 160 T9 13
valid_sources[0x19] 25585 1 T1 137 T2 178 T3 11
valid_sources[0x1a] 24287 1 T1 117 T2 129 T9 3
valid_sources[0x1b] 25312 1 T1 125 T2 136 T3 14
valid_sources[0x1c] 25643 1 T1 116 T2 173 T3 4
valid_sources[0x1d] 25359 1 T1 147 T2 133 T10 29
valid_sources[0x1e] 25730 1 T1 99 T2 185 T3 3
valid_sources[0x1f] 24710 1 T1 95 T2 151 T9 6
valid_sources[0x20] 25139 1 T1 151 T2 165 T3 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 23246 1 T1 99 T2 139 T3 2
values[0x0] all_enables biggest_size 172428 1 T1 838 T2 1073 T3 21
values[0x1] all_enables biggest_size 23128 1 T1 87 T2 146 T3 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1389348 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 226019 1 T1 1174 T2 1379 T3 19


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 552426 1 T1 2569 T2 3532 T3 56
values[0x0] 507452 1 T1 2635 T2 3309 T3 52
values[0x1] 555489 1 T1 2702 T2 3589 T3 47


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1066741 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 548626 1 T1 2736 T2 3484 T3 48


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25323 1 T1 99 T2 226 T3 1
valid_sources[0x01] 25354 1 T1 105 T2 124 T3 8
valid_sources[0x02] 25208 1 T1 184 T2 160 T3 2
valid_sources[0x03] 25420 1 T1 128 T2 222 T9 2
valid_sources[0x04] 25471 1 T1 102 T2 124 T9 4
valid_sources[0x05] 25278 1 T1 120 T2 136 T3 5
valid_sources[0x06] 25102 1 T1 83 T2 165 T9 1
valid_sources[0x07] 25007 1 T1 79 T2 173 T3 1
valid_sources[0x08] 24482 1 T1 107 T2 98 T9 2
valid_sources[0x09] 25946 1 T1 108 T2 191 T3 2
valid_sources[0x0a] 25795 1 T1 119 T2 145 T3 5
valid_sources[0x0b] 25151 1 T1 133 T2 119 T9 4
valid_sources[0x0c] 25333 1 T1 134 T2 157 T9 3
valid_sources[0x0d] 25324 1 T1 123 T2 127 T3 11
valid_sources[0x0e] 25832 1 T1 147 T2 146 T3 12
valid_sources[0x0f] 25739 1 T1 142 T2 240 T3 1
valid_sources[0x10] 25572 1 T1 131 T2 122 T3 3
valid_sources[0x11] 25449 1 T1 114 T2 131 T3 5
valid_sources[0x12] 24910 1 T1 108 T2 173 T9 2
valid_sources[0x13] 25231 1 T1 107 T2 157 T3 1
valid_sources[0x14] 25251 1 T1 116 T2 108 T9 4
valid_sources[0x15] 24831 1 T1 162 T2 284 T10 123
valid_sources[0x16] 25833 1 T1 127 T2 167 T3 3
valid_sources[0x17] 25426 1 T1 110 T2 135 T3 4
valid_sources[0x18] 25001 1 T1 161 T2 144 T3 4
valid_sources[0x19] 25623 1 T1 176 T2 128 T9 1
valid_sources[0x1a] 25281 1 T1 108 T2 84 T9 1
valid_sources[0x1b] 25105 1 T1 92 T2 165 T9 1
valid_sources[0x1c] 25225 1 T1 105 T2 211 T9 1
valid_sources[0x1d] 25326 1 T1 210 T2 123 T3 8
valid_sources[0x1e] 25404 1 T1 82 T2 178 T3 1
valid_sources[0x1f] 24631 1 T1 112 T2 177 T9 1
valid_sources[0x20] 25299 1 T1 142 T2 109 T9 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24017 1 T1 97 T2 134 T3 1
values[0x0] all_enables biggest_size 178194 1 T1 938 T2 1090 T3 18
values[0x1] all_enables biggest_size 23808 1 T1 139 T2 155 T9 4


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1387159 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 220062 1 T1 1070 T2 1352 T3 31


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 547179 1 T1 2659 T2 3241 T3 55
values[0x0] 514298 1 T1 2656 T2 3246 T3 69
values[0x1] 545744 1 T1 2719 T2 3279 T3 63


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1071182 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 536039 1 T1 2619 T2 3205 T3 58


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25271 1 T1 195 T2 204 T3 1
valid_sources[0x01] 24535 1 T1 31 T2 155 T10 17
valid_sources[0x02] 24901 1 T1 117 T2 129 T3 4
valid_sources[0x03] 25286 1 T1 82 T2 148 T3 6
valid_sources[0x04] 25425 1 T1 85 T2 139 T9 2
valid_sources[0x05] 25378 1 T1 94 T2 161 T3 2
valid_sources[0x06] 24374 1 T1 100 T2 163 T3 5
valid_sources[0x07] 24919 1 T1 60 T2 123 T9 4
valid_sources[0x08] 25161 1 T1 109 T2 138 T3 3
valid_sources[0x09] 25214 1 T1 156 T2 107 T9 2
valid_sources[0x0a] 25556 1 T1 176 T2 157 T3 3
valid_sources[0x0b] 24710 1 T1 94 T2 146 T3 4
valid_sources[0x0c] 25006 1 T1 168 T2 123 T3 4
valid_sources[0x0d] 25283 1 T1 130 T2 114 T3 3
valid_sources[0x0e] 25324 1 T1 192 T2 171 T3 3
valid_sources[0x0f] 25585 1 T1 108 T2 142 T3 2
valid_sources[0x10] 24455 1 T1 75 T2 136 T3 2
valid_sources[0x11] 24911 1 T1 105 T2 128 T3 3
valid_sources[0x12] 24606 1 T1 58 T2 148 T3 6
valid_sources[0x13] 25352 1 T1 150 T2 143 T3 3
valid_sources[0x14] 24286 1 T1 64 T2 140 T3 4
valid_sources[0x15] 25456 1 T1 169 T2 178 T3 2
valid_sources[0x16] 25678 1 T1 43 T2 123 T3 3
valid_sources[0x17] 25356 1 T1 156 T2 142 T3 2
valid_sources[0x18] 24792 1 T1 116 T2 172 T3 4
valid_sources[0x19] 24889 1 T1 140 T2 197 T3 3
valid_sources[0x1a] 25068 1 T1 78 T2 154 T3 3
valid_sources[0x1b] 25138 1 T1 125 T2 169 T3 7
valid_sources[0x1c] 24770 1 T1 38 T2 163 T3 5
valid_sources[0x1d] 25057 1 T1 81 T2 163 T9 6
valid_sources[0x1e] 25637 1 T1 105 T2 203 T3 3
valid_sources[0x1f] 25050 1 T1 89 T2 199 T3 2
valid_sources[0x20] 25211 1 T1 179 T2 131 T3 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 23575 1 T1 103 T2 123 T3 3
values[0x0] all_enables biggest_size 173242 1 T1 865 T2 1095 T3 25
values[0x1] all_enables biggest_size 23245 1 T1 102 T2 134 T3 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%