Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7387010	0	0
GntImpliesValid_A	2147483647	7387010	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7387010	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	399842646	0	0
ReadyAndValidImplyGrant_A	2147483647	7387010	0	0
ReqAndReadyImplyGrant_A	2147483647	7387010	0	0
ReqImpliesValid_A	2147483647	31490537	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	45663	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7387010	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	893352	890544	0	0
T2	1250952	1219728	0	0
T3	12588360	12587616	0	0
T4	3161880	3158328	0	0
T7	9056784	9056016	0	0
T8	345648	344856	0	0
T9	422712	398712	0	0
T10	2322528	2318256	0	0
T11	48744	48120	0	0
T12	585408	584928	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7387010	0	0
T1	893352	19868	0	0
T2	1250952	27476	0	0
T3	12588360	520	0	0
T4	3161880	11285	0	0
T7	9056784	397	0	0
T8	345648	1015	0	0
T9	422712	7381	0	0
T10	2322528	27221	0	0
T11	48744	429	0	0
T12	585408	11742	0	0
T13	0	1610	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7387010	0	0
T1	893352	19868	0	0
T2	1250952	27476	0	0
T3	12588360	520	0	0
T4	3161880	11285	0	0
T7	9056784	397	0	0
T8	345648	1015	0	0
T9	422712	7381	0	0
T10	2322528	27221	0	0
T11	48744	429	0	0
T12	585408	11742	0	0
T13	0	1610	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	893352	890544	0	0
T2	1250952	1219728	0	0
T3	12588360	12587616	0	0
T4	3161880	3158328	0	0
T7	9056784	9056016	0	0
T8	345648	344856	0	0
T9	422712	398712	0	0
T10	2322528	2318256	0	0
T11	48744	48120	0	0
T12	585408	584928	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	893352	890544	0	0
T2	1250952	1219728	0	0
T3	12588360	12587616	0	0
T4	3161880	3158328	0	0
T7	9056784	9056016	0	0
T8	345648	344856	0	0
T9	422712	398712	0	0
T10	2322528	2318256	0	0
T11	48744	48120	0	0
T12	585408	584928	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7387010	0	0
T1	893352	19868	0	0
T2	1250952	27476	0	0
T3	12588360	520	0	0
T4	3161880	11285	0	0
T7	9056784	397	0	0
T8	345648	1015	0	0
T9	422712	7381	0	0
T10	2322528	27221	0	0
T11	48744	429	0	0
T12	585408	11742	0	0
T13	0	1610	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	399842646	0	0
T1	893352	24593	0	0
T2	1250952	30225	0	0
T3	12588360	680126	0	0
T4	3161880	201370	0	0
T7	9056784	455356	0	0
T8	345648	18764	0	0
T9	422712	7149	0	0
T10	2322528	23111	0	0
T11	48744	617	0	0
T12	585408	1120	0	0
T13	0	10975	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7387010	0	0
T1	893352	19868	0	0
T2	1250952	27476	0	0
T3	12588360	520	0	0
T4	3161880	11285	0	0
T7	9056784	397	0	0
T8	345648	1015	0	0
T9	422712	7381	0	0
T10	2322528	27221	0	0
T11	48744	429	0	0
T12	585408	11742	0	0
T13	0	1610	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7387010	0	0
T1	893352	19868	0	0
T2	1250952	27476	0	0
T3	12588360	520	0	0
T4	3161880	11285	0	0
T7	9056784	397	0	0
T8	345648	1015	0	0
T9	422712	7381	0	0
T10	2322528	27221	0	0
T11	48744	429	0	0
T12	585408	11742	0	0
T13	0	1610	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31490537	0	0
T1	893352	22391	0	0
T2	1250952	33456	0	0
T3	12588360	31278	0	0
T4	3161880	23970	0	0
T7	9056784	24772	0	0
T8	345648	2021	0	0
T9	422712	11224	0	0
T10	2322528	74815	0	0
T11	48744	492	0	0
T12	585408	25651	0	0
T13	0	35013	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45663	0	21600
T1	74446	81	0	2
T2	104246	187	0	2
T3	1049030	0	0	2
T4	263490	2	0	2
T7	754732	0	0	2
T8	28804	0	0	2
T9	35226	20	0	2
T10	193544	375	0	2
T11	4062	0	0	2
T12	48784	585	0	2
T14	0	1	0	0
T15	0	13	0	0
T16	0	30	0	0
T17	0	1	0	0
T18	0	42	0	0
T19	0	402	0	0
T20	0	8	0	0
T21	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	893352	890544	0	0
T2	1250952	1219728	0	0
T3	12588360	12587616	0	0
T4	3161880	3158328	0	0
T7	9056784	9056016	0	0
T8	345648	344856	0	0
T9	422712	398712	0	0
T10	2322528	2318256	0	0
T11	48744	48120	0	0
T12	585408	584928	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7387010	0	0
T1	893352	19868	0	0
T2	1250952	27476	0	0
T3	12588360	520	0	0
T4	3161880	11285	0	0
T7	9056784	397	0	0
T8	345648	1015	0	0
T9	422712	7381	0	0
T10	2322528	27221	0	0
T11	48744	429	0	0
T12	585408	11742	0	0
T13	0	1610	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	826638	0	0
GntImpliesValid_A	362355569	826638	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	826638	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	11079627	0	0
ReadyAndValidImplyGrant_A	362355569	826638	0	0
ReqAndReadyImplyGrant_A	362355569	826638	0	0
ReqImpliesValid_A	362355569	2302962	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	826638	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826638	0	0
T1	37223	2203	0	0
T2	52123	3065	0	0
T3	524515	64	0	0
T4	131745	1244	0	0
T7	377366	47	0	0
T8	14402	124	0	0
T9	17613	1441	0	0
T10	96772	2921	0	0
T11	2031	45	0	0
T12	24392	2066	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826638	0	0
T1	37223	2203	0	0
T2	52123	3065	0	0
T3	524515	64	0	0
T4	131745	1244	0	0
T7	377366	47	0	0
T8	14402	124	0	0
T9	17613	1441	0	0
T10	96772	2921	0	0
T11	2031	45	0	0
T12	24392	2066	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826638	0	0
T1	37223	2203	0	0
T2	52123	3065	0	0
T3	524515	64	0	0
T4	131745	1244	0	0
T7	377366	47	0	0
T8	14402	124	0	0
T9	17613	1441	0	0
T10	96772	2921	0	0
T11	2031	45	0	0
T12	24392	2066	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	11079627	0	0
T1	37223	1742	0	0
T2	52123	2446	0	0
T3	524515	22594	0	0
T4	131745	8716	0	0
T7	377366	13192	0	0
T8	14402	905	0	0
T9	17613	589	0	0
T10	96772	1576	0	0
T11	2031	34	0	0
T12	24392	472	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826638	0	0
T1	37223	2203	0	0
T2	52123	3065	0	0
T3	524515	64	0	0
T4	131745	1244	0	0
T7	377366	47	0	0
T8	14402	124	0	0
T9	17613	1441	0	0
T10	96772	2921	0	0
T11	2031	45	0	0
T12	24392	2066	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826638	0	0
T1	37223	2203	0	0
T2	52123	3065	0	0
T3	524515	64	0	0
T4	131745	1244	0	0
T7	377366	47	0	0
T8	14402	124	0	0
T9	17613	1441	0	0
T10	96772	2921	0	0
T11	2031	45	0	0
T12	24392	2066	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2302962	0	0
T1	37223	2667	0	0
T2	52123	3700	0	0
T3	524515	2536	0	0
T4	131745	2018	0	0
T7	377366	1740	0	0
T8	14402	203	0	0
T9	17613	2300	0	0
T10	96772	4269	0	0
T11	2031	57	0	0
T12	24392	3661	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826638	0	0
T1	37223	2203	0	0
T2	52123	3065	0	0
T3	524515	64	0	0
T4	131745	1244	0	0
T7	377366	47	0	0
T8	14402	124	0	0
T9	17613	1441	0	0
T10	96772	2921	0	0
T11	2031	45	0	0
T12	24392	2066	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	826847	0	0
GntImpliesValid_A	362355569	826847	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	826847	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	11045210	0	0
ReadyAndValidImplyGrant_A	362355569	826847	0	0
ReqAndReadyImplyGrant_A	362355569	826847	0	0
ReqImpliesValid_A	362355569	2174691	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	826847	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826847	0	0
T1	37223	2198	0	0
T2	52123	2952	0	0
T3	524515	42	0	0
T4	131745	1277	0	0
T7	377366	56	0	0
T8	14402	109	0	0
T9	17613	751	0	0
T10	96772	2198	0	0
T11	2031	42	0	0
T12	24392	1999	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826847	0	0
T1	37223	2198	0	0
T2	52123	2952	0	0
T3	524515	42	0	0
T4	131745	1277	0	0
T7	377366	56	0	0
T8	14402	109	0	0
T9	17613	751	0	0
T10	96772	2198	0	0
T11	2031	42	0	0
T12	24392	1999	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826847	0	0
T1	37223	2198	0	0
T2	52123	2952	0	0
T3	524515	42	0	0
T4	131745	1277	0	0
T7	377366	56	0	0
T8	14402	109	0	0
T9	17613	751	0	0
T10	96772	2198	0	0
T11	2031	42	0	0
T12	24392	1999	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	11045210	0	0
T1	37223	1723	0	0
T2	52123	2361	0	0
T3	524515	10585	0	0
T4	131745	8605	0	0
T7	377366	17062	0	0
T8	14402	850	0	0
T9	17613	606	0	0
T10	96772	1615	0	0
T11	2031	36	0	0
T12	24392	475	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826847	0	0
T1	37223	2198	0	0
T2	52123	2952	0	0
T3	524515	42	0	0
T4	131745	1277	0	0
T7	377366	56	0	0
T8	14402	109	0	0
T9	17613	751	0	0
T10	96772	2198	0	0
T11	2031	42	0	0
T12	24392	1999	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826847	0	0
T1	37223	2198	0	0
T2	52123	2952	0	0
T3	524515	42	0	0
T4	131745	1277	0	0
T7	377366	56	0	0
T8	14402	109	0	0
T9	17613	751	0	0
T10	96772	2198	0	0
T11	2031	42	0	0
T12	24392	1999	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2174691	0	0
T1	37223	2676	0	0
T2	52123	3557	0	0
T3	524515	740	0	0
T4	131745	1910	0	0
T7	377366	1239	0	0
T8	14402	138	0	0
T9	17613	903	0	0
T10	96772	2784	0	0
T11	2031	49	0	0
T12	24392	3524	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	826847	0	0
T1	37223	2198	0	0
T2	52123	2952	0	0
T3	524515	42	0	0
T4	131745	1277	0	0
T7	377366	56	0	0
T8	14402	109	0	0
T9	17613	751	0	0
T10	96772	2198	0	0
T11	2031	42	0	0
T12	24392	1999	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	204443	0	0
GntImpliesValid_A	362355569	204443	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	204443	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2730803	0	0
ReadyAndValidImplyGrant_A	362355569	204443	0	0
ReqAndReadyImplyGrant_A	362355569	204443	0	0
ReqImpliesValid_A	362355569	535286	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	204443	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	204443	0	0
T1	37223	581	0	0
T2	52123	676	0	0
T3	524515	21	0	0
T4	131745	308	0	0
T7	377366	6	0	0
T8	14402	31	0	0
T9	17613	131	0	0
T10	96772	595	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	136	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	204443	0	0
T1	37223	581	0	0
T2	52123	676	0	0
T3	524515	21	0	0
T4	131745	308	0	0
T7	377366	6	0	0
T8	14402	31	0	0
T9	17613	131	0	0
T10	96772	595	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	136	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	204443	0	0
T1	37223	581	0	0
T2	52123	676	0	0
T3	524515	21	0	0
T4	131745	308	0	0
T7	377366	6	0	0
T8	14402	31	0	0
T9	17613	131	0	0
T10	96772	595	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	136	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2730803	0	0
T1	37223	557	0	0
T2	52123	662	0	0
T3	524515	6796	0	0
T4	131745	2278	0	0
T7	377366	1824	0	0
T8	14402	229	0	0
T9	17613	137	0	0
T10	96772	66	0	0
T11	2031	15	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	204443	0	0
T1	37223	581	0	0
T2	52123	676	0	0
T3	524515	21	0	0
T4	131745	308	0	0
T7	377366	6	0	0
T8	14402	31	0	0
T9	17613	131	0	0
T10	96772	595	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	136	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	204443	0	0
T1	37223	581	0	0
T2	52123	676	0	0
T3	524515	21	0	0
T4	131745	308	0	0
T7	377366	6	0	0
T8	14402	31	0	0
T9	17613	131	0	0
T10	96772	595	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	136	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	535286	0	0
T1	37223	608	0	0
T2	52123	706	0	0
T3	524515	659	0	0
T4	131745	428	0	0
T7	377366	6	0	0
T8	14402	43	0	0
T9	17613	132	0	0
T10	96772	1127	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	3587	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	204443	0	0
T1	37223	581	0	0
T2	52123	676	0	0
T3	524515	21	0	0
T4	131745	308	0	0
T7	377366	6	0	0
T8	14402	31	0	0
T9	17613	131	0	0
T10	96772	595	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	136	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	210910	0	0
GntImpliesValid_A	362355569	210910	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	210910	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2769319	0	0
ReadyAndValidImplyGrant_A	362355569	210910	0	0
ReqAndReadyImplyGrant_A	362355569	210910	0	0
ReqImpliesValid_A	362355569	568248	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	210910	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	210910	0	0
T1	37223	544	0	0
T2	52123	1075	0	0
T3	524515	11	0	0
T4	131745	318	0	0
T7	377366	7	0	0
T8	14402	31	0	0
T9	17613	134	0	0
T10	96772	2605	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	210910	0	0
T1	37223	544	0	0
T2	52123	1075	0	0
T3	524515	11	0	0
T4	131745	318	0	0
T7	377366	7	0	0
T8	14402	31	0	0
T9	17613	134	0	0
T10	96772	2605	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	210910	0	0
T1	37223	544	0	0
T2	52123	1075	0	0
T3	524515	11	0	0
T4	131745	318	0	0
T7	377366	7	0	0
T8	14402	31	0	0
T9	17613	134	0	0
T10	96772	2605	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2769319	0	0
T1	37223	523	0	0
T2	52123	677	0	0
T3	524515	3519	0	0
T4	131745	2222	0	0
T7	377366	2681	0	0
T8	14402	234	0	0
T9	17613	135	0	0
T10	96772	251	0	0
T11	2031	14	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	210910	0	0
T1	37223	544	0	0
T2	52123	1075	0	0
T3	524515	11	0	0
T4	131745	318	0	0
T7	377366	7	0	0
T8	14402	31	0	0
T9	17613	134	0	0
T10	96772	2605	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	210910	0	0
T1	37223	544	0	0
T2	52123	1075	0	0
T3	524515	11	0	0
T4	131745	318	0	0
T7	377366	7	0	0
T8	14402	31	0	0
T9	17613	134	0	0
T10	96772	2605	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	568248	0	0
T1	37223	568	0	0
T2	52123	1489	0	0
T3	524515	11	0	0
T4	131745	375	0	0
T7	377366	228	0	0
T8	14402	46	0	0
T9	17613	140	0	0
T10	96772	4962	0	0
T11	2031	15	0	0
T12	24392	0	0	0
T13	0	3539	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	210910	0	0
T1	37223	544	0	0
T2	52123	1075	0	0
T3	524515	11	0	0
T4	131745	318	0	0
T7	377366	7	0	0
T8	14402	31	0	0
T9	17613	134	0	0
T10	96772	2605	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	132	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	200923	0	0
GntImpliesValid_A	362355569	200923	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	200923	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	4677184	0	0
ReadyAndValidImplyGrant_A	362355569	200923	0	0
ReqAndReadyImplyGrant_A	362355569	200923	0	0
ReqImpliesValid_A	362355569	1003083	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	200923	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	200923	0	0
T1	37223	555	0	0
T2	52123	710	0	0
T3	524515	16	0	0
T4	131745	319	0	0
T7	377366	8	0	0
T8	14402	29	0	0
T9	17613	117	0	0
T10	96772	1101	0	0
T11	2031	10	0	0
T12	24392	428	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	200923	0	0
T1	37223	555	0	0
T2	52123	710	0	0
T3	524515	16	0	0
T4	131745	319	0	0
T7	377366	8	0	0
T8	14402	29	0	0
T9	17613	117	0	0
T10	96772	1101	0	0
T11	2031	10	0	0
T12	24392	428	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	200923	0	0
T1	37223	555	0	0
T2	52123	710	0	0
T3	524515	16	0	0
T4	131745	319	0	0
T7	377366	8	0	0
T8	14402	29	0	0
T9	17613	117	0	0
T10	96772	1101	0	0
T11	2031	10	0	0
T12	24392	428	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	4677184	0	0
T1	37223	2441	0	0
T2	52123	3499	0	0
T3	524515	14003	0	0
T4	131745	4848	0	0
T7	377366	1755	0	0
T8	14402	158	0	0
T9	17613	721	0	0
T10	96772	761	0	0
T11	2031	38	0	0
T12	24392	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	200923	0	0
T1	37223	555	0	0
T2	52123	710	0	0
T3	524515	16	0	0
T4	131745	319	0	0
T7	377366	8	0	0
T8	14402	29	0	0
T9	17613	117	0	0
T10	96772	1101	0	0
T11	2031	10	0	0
T12	24392	428	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	200923	0	0
T1	37223	555	0	0
T2	52123	710	0	0
T3	524515	16	0	0
T4	131745	319	0	0
T7	377366	8	0	0
T8	14402	29	0	0
T9	17613	117	0	0
T10	96772	1101	0	0
T11	2031	10	0	0
T12	24392	428	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	1003083	0	0
T1	37223	750	0	0
T2	52123	1017	0	0
T3	524515	252	0	0
T4	131745	525	0	0
T7	377366	8	0	0
T8	14402	29	0	0
T9	17613	151	0	0
T10	96772	7955	0	0
T11	2031	19	0	0
T12	24392	2270	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	200923	0	0
T1	37223	555	0	0
T2	52123	710	0	0
T3	524515	16	0	0
T4	131745	319	0	0
T7	377366	8	0	0
T8	14402	29	0	0
T9	17613	117	0	0
T10	96772	1101	0	0
T11	2031	10	0	0
T12	24392	428	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	206249	0	0
GntImpliesValid_A	362355569	206249	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	206249	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	4523280	0	0
ReadyAndValidImplyGrant_A	362355569	206249	0	0
ReqAndReadyImplyGrant_A	362355569	206249	0	0
ReqImpliesValid_A	362355569	1179431	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	206249	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206249	0	0
T1	37223	522	0	0
T2	52123	1141	0	0
T3	524515	18	0	0
T4	131745	329	0	0
T7	377366	9	0	0
T8	14402	25	0	0
T9	17613	122	0	0
T10	96772	1590	0	0
T11	2031	16	0	0
T12	24392	1077	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206249	0	0
T1	37223	522	0	0
T2	52123	1141	0	0
T3	524515	18	0	0
T4	131745	329	0	0
T7	377366	9	0	0
T8	14402	25	0	0
T9	17613	122	0	0
T10	96772	1590	0	0
T11	2031	16	0	0
T12	24392	1077	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206249	0	0
T1	37223	522	0	0
T2	52123	1141	0	0
T3	524515	18	0	0
T4	131745	329	0	0
T7	377366	9	0	0
T8	14402	25	0	0
T9	17613	122	0	0
T10	96772	1590	0	0
T11	2031	16	0	0
T12	24392	1077	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	4523280	0	0
T1	37223	2770	0	0
T2	52123	4016	0	0
T3	524515	9100	0	0
T4	131745	4011	0	0
T7	377366	4987	0	0
T8	14402	140	0	0
T9	17613	819	0	0
T10	96772	14228	0	0
T11	2031	116	0	0
T12	24392	65	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206249	0	0
T1	37223	522	0	0
T2	52123	1141	0	0
T3	524515	18	0	0
T4	131745	329	0	0
T7	377366	9	0	0
T8	14402	25	0	0
T9	17613	122	0	0
T10	96772	1590	0	0
T11	2031	16	0	0
T12	24392	1077	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206249	0	0
T1	37223	522	0	0
T2	52123	1141	0	0
T3	524515	18	0	0
T4	131745	329	0	0
T7	377366	9	0	0
T8	14402	25	0	0
T9	17613	122	0	0
T10	96772	1590	0	0
T11	2031	16	0	0
T12	24392	1077	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	1179431	0	0
T1	37223	829	0	0
T2	52123	4192	0	0
T3	524515	1766	0	0
T4	131745	457	0	0
T7	377366	9	0	0
T8	14402	27	0	0
T9	17613	169	0	0
T10	96772	22618	0	0
T11	2031	23	0	0
T12	24392	4787	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206249	0	0
T1	37223	522	0	0
T2	52123	1141	0	0
T3	524515	18	0	0
T4	131745	329	0	0
T7	377366	9	0	0
T8	14402	25	0	0
T9	17613	122	0	0
T10	96772	1590	0	0
T11	2031	16	0	0
T12	24392	1077	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	206927	0	0
GntImpliesValid_A	362355569	206927	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	206927	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	4469164	0	0
ReadyAndValidImplyGrant_A	362355569	206927	0	0
ReqAndReadyImplyGrant_A	362355569	206927	0	0
ReqImpliesValid_A	362355569	1029335	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	206927	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206927	0	0
T1	37223	518	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	299	0	0
T7	377366	6	0	0
T8	14402	29	0	0
T9	17613	141	0	0
T10	96772	1615	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	119	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206927	0	0
T1	37223	518	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	299	0	0
T7	377366	6	0	0
T8	14402	29	0	0
T9	17613	141	0	0
T10	96772	1615	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	119	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206927	0	0
T1	37223	518	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	299	0	0
T7	377366	6	0	0
T8	14402	29	0	0
T9	17613	141	0	0
T10	96772	1615	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	119	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	4469164	0	0
T1	37223	4022	0	0
T2	52123	3965	0	0
T3	524515	17463	0	0
T4	131745	12406	0	0
T7	377366	1102	0	0
T8	14402	141	0	0
T9	17613	938	0	0
T10	96772	1908	0	0
T11	2031	128	0	0
T12	24392	0	0	0
T13	0	10975	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206927	0	0
T1	37223	518	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	299	0	0
T7	377366	6	0	0
T8	14402	29	0	0
T9	17613	141	0	0
T10	96772	1615	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	119	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206927	0	0
T1	37223	518	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	299	0	0
T7	377366	6	0	0
T8	14402	29	0	0
T9	17613	141	0	0
T10	96772	1615	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	119	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	1029335	0	0
T1	37223	836	0	0
T2	52123	947	0	0
T3	524515	543	0	0
T4	131745	742	0	0
T7	377366	6	0	0
T8	14402	29	0	0
T9	17613	272	0	0
T10	96772	9251	0	0
T11	2031	26	0	0
T12	24392	0	0	0
T13	0	781	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	206927	0	0
T1	37223	518	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	299	0	0
T7	377366	6	0	0
T8	14402	29	0	0
T9	17613	141	0	0
T10	96772	1615	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	119	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	197609	0	0
GntImpliesValid_A	362355569	197609	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	197609	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	5122332	0	0
ReadyAndValidImplyGrant_A	362355569	197609	0	0
ReqAndReadyImplyGrant_A	362355569	197609	0	0
ReqImpliesValid_A	362355569	1095989	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	197609	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	197609	0	0
T1	37223	562	0	0
T2	52123	638	0	0
T3	524515	17	0	0
T4	131745	310	0	0
T7	377366	5	0	0
T8	14402	22	0	0
T9	17613	539	0	0
T10	96772	72	0	0
T11	2031	13	0	0
T12	24392	568	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	197609	0	0
T1	37223	562	0	0
T2	52123	638	0	0
T3	524515	17	0	0
T4	131745	310	0	0
T7	377366	5	0	0
T8	14402	22	0	0
T9	17613	539	0	0
T10	96772	72	0	0
T11	2031	13	0	0
T12	24392	568	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	197609	0	0
T1	37223	562	0	0
T2	52123	638	0	0
T3	524515	17	0	0
T4	131745	310	0	0
T7	377366	5	0	0
T8	14402	22	0	0
T9	17613	539	0	0
T10	96772	72	0	0
T11	2031	13	0	0
T12	24392	568	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	5122332	0	0
T1	37223	3304	0	0
T2	52123	2837	0	0
T3	524515	6031	0	0
T4	131745	4915	0	0
T7	377366	2488	0	0
T8	14402	105	0	0
T9	17613	763	0	0
T10	96772	713	0	0
T11	2031	50	0	0
T12	24392	29	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	197609	0	0
T1	37223	562	0	0
T2	52123	638	0	0
T3	524515	17	0	0
T4	131745	310	0	0
T7	377366	5	0	0
T8	14402	22	0	0
T9	17613	539	0	0
T10	96772	72	0	0
T11	2031	13	0	0
T12	24392	568	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	197609	0	0
T1	37223	562	0	0
T2	52123	638	0	0
T3	524515	17	0	0
T4	131745	310	0	0
T7	377366	5	0	0
T8	14402	22	0	0
T9	17613	539	0	0
T10	96772	72	0	0
T11	2031	13	0	0
T12	24392	568	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	1095989	0	0
T1	37223	934	0	0
T2	52123	847	0	0
T3	524515	17	0	0
T4	131745	555	0	0
T7	377366	5	0	0
T8	14402	25	0	0
T9	17613	2974	0	0
T10	96772	84	0	0
T11	2031	21	0	0
T12	24392	2900	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	197609	0	0
T1	37223	562	0	0
T2	52123	638	0	0
T3	524515	17	0	0
T4	131745	310	0	0
T7	377366	5	0	0
T8	14402	22	0	0
T9	17613	539	0	0
T10	96772	72	0	0
T11	2031	13	0	0
T12	24392	568	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	208074	0	0
GntImpliesValid_A	362355569	208074	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	208074	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2699326	0	0
ReadyAndValidImplyGrant_A	362355569	208074	0	0
ReqAndReadyImplyGrant_A	362355569	208074	0	0
ReqImpliesValid_A	362355569	520917	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	208074	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208074	0	0
T1	37223	523	0	0
T2	52123	1246	0	0
T3	524515	17	0	0
T4	131745	323	0	0
T7	377366	9	0	0
T8	14402	26	0	0
T9	17613	126	0	0
T10	96772	1505	0	0
T11	2031	20	0	0
T12	24392	473	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208074	0	0
T1	37223	523	0	0
T2	52123	1246	0	0
T3	524515	17	0	0
T4	131745	323	0	0
T7	377366	9	0	0
T8	14402	26	0	0
T9	17613	126	0	0
T10	96772	1505	0	0
T11	2031	20	0	0
T12	24392	473	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208074	0	0
T1	37223	523	0	0
T2	52123	1246	0	0
T3	524515	17	0	0
T4	131745	323	0	0
T7	377366	9	0	0
T8	14402	26	0	0
T9	17613	126	0	0
T10	96772	1505	0	0
T11	2031	20	0	0
T12	24392	473	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2699326	0	0
T1	37223	495	0	0
T2	52123	1157	0	0
T3	524515	5618	0	0
T4	131745	2427	0	0
T7	377366	4259	0	0
T8	14402	155	0	0
T9	17613	131	0	0
T10	96772	164	0	0
T11	2031	21	0	0
T12	24392	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208074	0	0
T1	37223	523	0	0
T2	52123	1246	0	0
T3	524515	17	0	0
T4	131745	323	0	0
T7	377366	9	0	0
T8	14402	26	0	0
T9	17613	126	0	0
T10	96772	1505	0	0
T11	2031	20	0	0
T12	24392	473	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208074	0	0
T1	37223	523	0	0
T2	52123	1246	0	0
T3	524515	17	0	0
T4	131745	323	0	0
T7	377366	9	0	0
T8	14402	26	0	0
T9	17613	126	0	0
T10	96772	1505	0	0
T11	2031	20	0	0
T12	24392	473	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	520917	0	0
T1	37223	554	0	0
T2	52123	1351	0	0
T3	524515	1011	0	0
T4	131745	411	0	0
T7	377366	9	0	0
T8	14402	36	0	0
T9	17613	128	0	0
T10	96772	2849	0	0
T11	2031	20	0	0
T12	24392	945	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208074	0	0
T1	37223	523	0	0
T2	52123	1246	0	0
T3	524515	17	0	0
T4	131745	323	0	0
T7	377366	9	0	0
T8	14402	26	0	0
T9	17613	126	0	0
T10	96772	1505	0	0
T11	2031	20	0	0
T12	24392	473	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	203075	0	0
GntImpliesValid_A	362355569	203075	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	203075	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2802828	0	0
ReadyAndValidImplyGrant_A	362355569	203075	0	0
ReqAndReadyImplyGrant_A	362355569	203075	0	0
ReqImpliesValid_A	362355569	530363	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	203075	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203075	0	0
T1	37223	506	0	0
T2	52123	666	0	0
T3	524515	10	0	0
T4	131745	296	0	0
T7	377366	14	0	0
T8	14402	24	0	0
T9	17613	141	0	0
T10	96772	78	0	0
T11	2031	9	0	0
T12	24392	0	0	0
T13	0	170	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203075	0	0
T1	37223	506	0	0
T2	52123	666	0	0
T3	524515	10	0	0
T4	131745	296	0	0
T7	377366	14	0	0
T8	14402	24	0	0
T9	17613	141	0	0
T10	96772	78	0	0
T11	2031	9	0	0
T12	24392	0	0	0
T13	0	170	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203075	0	0
T1	37223	506	0	0
T2	52123	666	0	0
T3	524515	10	0	0
T4	131745	296	0	0
T7	377366	14	0	0
T8	14402	24	0	0
T9	17613	141	0	0
T10	96772	78	0	0
T11	2031	9	0	0
T12	24392	0	0	0
T13	0	170	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2802828	0	0
T1	37223	491	0	0
T2	52123	659	0	0
T3	524515	5147	0	0
T4	131745	2093	0	0
T7	377366	4676	0	0
T8	14402	206	0	0
T9	17613	145	0	0
T10	96772	80	0	0
T11	2031	10	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203075	0	0
T1	37223	506	0	0
T2	52123	666	0	0
T3	524515	10	0	0
T4	131745	296	0	0
T7	377366	14	0	0
T8	14402	24	0	0
T9	17613	141	0	0
T10	96772	78	0	0
T11	2031	9	0	0
T12	24392	0	0	0
T13	0	170	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203075	0	0
T1	37223	506	0	0
T2	52123	666	0	0
T3	524515	10	0	0
T4	131745	296	0	0
T7	377366	14	0	0
T8	14402	24	0	0
T9	17613	141	0	0
T10	96772	78	0	0
T11	2031	9	0	0
T12	24392	0	0	0
T13	0	170	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	530363	0	0
T1	37223	524	0	0
T2	52123	689	0	0
T3	524515	10	0	0
T4	131745	356	0	0
T7	377366	591	0	0
T8	14402	24	0	0
T9	17613	144	0	0
T10	96772	79	0	0
T11	2031	9	0	0
T12	24392	0	0	0
T13	0	4377	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203075	0	0
T1	37223	506	0	0
T2	52123	666	0	0
T3	524515	10	0	0
T4	131745	296	0	0
T7	377366	14	0	0
T8	14402	24	0	0
T9	17613	141	0	0
T10	96772	78	0	0
T11	2031	9	0	0
T12	24392	0	0	0
T13	0	170	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	208739	0	0
GntImpliesValid_A	362355569	208739	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	208739	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2798107	0	0
ReadyAndValidImplyGrant_A	362355569	208739	0	0
ReqAndReadyImplyGrant_A	362355569	208739	0	0
ReqImpliesValid_A	362355569	546487	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	208739	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208739	0	0
T1	37223	543	0	0
T2	52123	621	0	0
T3	524515	11	0	0
T4	131745	316	0	0
T7	377366	7	0	0
T8	14402	25	0	0
T9	17613	646	0	0
T10	96772	497	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208739	0	0
T1	37223	543	0	0
T2	52123	621	0	0
T3	524515	11	0	0
T4	131745	316	0	0
T7	377366	7	0	0
T8	14402	25	0	0
T9	17613	646	0	0
T10	96772	497	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208739	0	0
T1	37223	543	0	0
T2	52123	621	0	0
T3	524515	11	0	0
T4	131745	316	0	0
T7	377366	7	0	0
T8	14402	25	0	0
T9	17613	646	0	0
T10	96772	497	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2798107	0	0
T1	37223	522	0	0
T2	52123	623	0	0
T3	524515	4124	0	0
T4	131745	2538	0	0
T7	377366	2704	0	0
T8	14402	200	0	0
T9	17613	571	0	0
T10	96772	352	0	0
T11	2031	13	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208739	0	0
T1	37223	543	0	0
T2	52123	621	0	0
T3	524515	11	0	0
T4	131745	316	0	0
T7	377366	7	0	0
T8	14402	25	0	0
T9	17613	646	0	0
T10	96772	497	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208739	0	0
T1	37223	543	0	0
T2	52123	621	0	0
T3	524515	11	0	0
T4	131745	316	0	0
T7	377366	7	0	0
T8	14402	25	0	0
T9	17613	646	0	0
T10	96772	497	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	546487	0	0
T1	37223	567	0	0
T2	52123	635	0	0
T3	524515	11	0	0
T4	131745	388	0	0
T7	377366	226	0	0
T8	14402	25	0	0
T9	17613	728	0	0
T10	96772	645	0	0
T11	2031	14	0	0
T12	24392	0	0	0
T13	0	4055	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	208739	0	0
T1	37223	543	0	0
T2	52123	621	0	0
T3	524515	11	0	0
T4	131745	316	0	0
T7	377366	7	0	0
T8	14402	25	0	0
T9	17613	646	0	0
T10	96772	497	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	132	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	203492	0	0
GntImpliesValid_A	362355569	203492	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	203492	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2766638	0	0
ReadyAndValidImplyGrant_A	362355569	203492	0	0
ReqAndReadyImplyGrant_A	362355569	203492	0	0
ReqImpliesValid_A	362355569	519228	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	203492	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203492	0	0
T1	37223	576	0	0
T2	52123	645	0	0
T3	524515	14	0	0
T4	131745	328	0	0
T7	377366	13	0	0
T8	14402	32	0	0
T9	17613	124	0	0
T10	96772	546	0	0
T11	2031	10	0	0
T12	24392	490	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203492	0	0
T1	37223	576	0	0
T2	52123	645	0	0
T3	524515	14	0	0
T4	131745	328	0	0
T7	377366	13	0	0
T8	14402	32	0	0
T9	17613	124	0	0
T10	96772	546	0	0
T11	2031	10	0	0
T12	24392	490	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203492	0	0
T1	37223	576	0	0
T2	52123	645	0	0
T3	524515	14	0	0
T4	131745	328	0	0
T7	377366	13	0	0
T8	14402	32	0	0
T9	17613	124	0	0
T10	96772	546	0	0
T11	2031	10	0	0
T12	24392	490	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2766638	0	0
T1	37223	558	0	0
T2	52123	635	0	0
T3	524515	4327	0	0
T4	131745	2382	0	0
T7	377366	4214	0	0
T8	14402	233	0	0
T9	17613	127	0	0
T10	96772	454	0	0
T11	2031	11	0	0
T12	24392	42	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203492	0	0
T1	37223	576	0	0
T2	52123	645	0	0
T3	524515	14	0	0
T4	131745	328	0	0
T7	377366	13	0	0
T8	14402	32	0	0
T9	17613	124	0	0
T10	96772	546	0	0
T11	2031	10	0	0
T12	24392	490	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203492	0	0
T1	37223	576	0	0
T2	52123	645	0	0
T3	524515	14	0	0
T4	131745	328	0	0
T7	377366	13	0	0
T8	14402	32	0	0
T9	17613	124	0	0
T10	96772	546	0	0
T11	2031	10	0	0
T12	24392	490	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	519228	0	0
T1	37223	597	0	0
T2	52123	671	0	0
T3	524515	322	0	0
T4	131745	395	0	0
T7	377366	224	0	0
T8	14402	43	0	0
T9	17613	128	0	0
T10	96772	641	0	0
T11	2031	10	0	0
T12	24392	939	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	203492	0	0
T1	37223	576	0	0
T2	52123	645	0	0
T3	524515	14	0	0
T4	131745	328	0	0
T7	377366	13	0	0
T8	14402	32	0	0
T9	17613	124	0	0
T10	96772	546	0	0
T11	2031	10	0	0
T12	24392	490	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	198481	0	0
GntImpliesValid_A	362355569	198481	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	198481	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2711515	0	0
ReadyAndValidImplyGrant_A	362355569	198481	0	0
ReqAndReadyImplyGrant_A	362355569	198481	0	0
ReqImpliesValid_A	362355569	473834	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	198481	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	198481	0	0
T1	37223	552	0	0
T2	52123	634	0	0
T3	524515	19	0	0
T4	131745	304	0	0
T7	377366	10	0	0
T8	14402	18	0	0
T9	17613	129	0	0
T10	96772	57	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	198481	0	0
T1	37223	552	0	0
T2	52123	634	0	0
T3	524515	19	0	0
T4	131745	304	0	0
T7	377366	10	0	0
T8	14402	18	0	0
T9	17613	129	0	0
T10	96772	57	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	198481	0	0
T1	37223	552	0	0
T2	52123	634	0	0
T3	524515	19	0	0
T4	131745	304	0	0
T7	377366	10	0	0
T8	14402	18	0	0
T9	17613	129	0	0
T10	96772	57	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2711515	0	0
T1	37223	536	0	0
T2	52123	627	0	0
T3	524515	5587	0	0
T4	131745	2276	0	0
T7	377366	2629	0	0
T8	14402	94	0	0
T9	17613	132	0	0
T10	96772	60	0	0
T11	2031	17	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	198481	0	0
T1	37223	552	0	0
T2	52123	634	0	0
T3	524515	19	0	0
T4	131745	304	0	0
T7	377366	10	0	0
T8	14402	18	0	0
T9	17613	129	0	0
T10	96772	57	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	198481	0	0
T1	37223	552	0	0
T2	52123	634	0	0
T3	524515	19	0	0
T4	131745	304	0	0
T7	377366	10	0	0
T8	14402	18	0	0
T9	17613	129	0	0
T10	96772	57	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	473834	0	0
T1	37223	571	0	0
T2	52123	657	0	0
T3	524515	223	0	0
T4	131745	400	0	0
T7	377366	10	0	0
T8	14402	18	0	0
T9	17613	133	0	0
T10	96772	57	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	2689	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	198481	0	0
T1	37223	552	0	0
T2	52123	634	0	0
T3	524515	19	0	0
T4	131745	304	0	0
T7	377366	10	0	0
T8	14402	18	0	0
T9	17613	129	0	0
T10	96772	57	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	195991	0	0
GntImpliesValid_A	362355569	195991	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	195991	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2713724	0	0
ReadyAndValidImplyGrant_A	362355569	195991	0	0
ReqAndReadyImplyGrant_A	362355569	195991	0	0
ReqImpliesValid_A	362355569	506325	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	195991	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195991	0	0
T1	37223	510	0	0
T2	52123	647	0	0
T3	524515	14	0	0
T4	131745	306	0	0
T7	377366	11	0	0
T8	14402	26	0	0
T9	17613	143	0	0
T10	96772	75	0	0
T11	2031	8	0	0
T12	24392	1028	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195991	0	0
T1	37223	510	0	0
T2	52123	647	0	0
T3	524515	14	0	0
T4	131745	306	0	0
T7	377366	11	0	0
T8	14402	26	0	0
T9	17613	143	0	0
T10	96772	75	0	0
T11	2031	8	0	0
T12	24392	1028	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195991	0	0
T1	37223	510	0	0
T2	52123	647	0	0
T3	524515	14	0	0
T4	131745	306	0	0
T7	377366	11	0	0
T8	14402	26	0	0
T9	17613	143	0	0
T10	96772	75	0	0
T11	2031	8	0	0
T12	24392	1028	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2713724	0	0
T1	37223	500	0	0
T2	52123	643	0	0
T3	524515	3637	0	0
T4	131745	2447	0	0
T7	377366	3787	0	0
T8	14402	177	0	0
T9	17613	143	0	0
T10	96772	78	0	0
T11	2031	8	0	0
T12	24392	3	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195991	0	0
T1	37223	510	0	0
T2	52123	647	0	0
T3	524515	14	0	0
T4	131745	306	0	0
T7	377366	11	0	0
T8	14402	26	0	0
T9	17613	143	0	0
T10	96772	75	0	0
T11	2031	8	0	0
T12	24392	1028	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195991	0	0
T1	37223	510	0	0
T2	52123	647	0	0
T3	524515	14	0	0
T4	131745	306	0	0
T7	377366	11	0	0
T8	14402	26	0	0
T9	17613	143	0	0
T10	96772	75	0	0
T11	2031	8	0	0
T12	24392	1028	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	506325	0	0
T1	37223	523	0	0
T2	52123	667	0	0
T3	524515	276	0	0
T4	131745	363	0	0
T7	377366	11	0	0
T8	14402	29	0	0
T9	17613	150	0	0
T10	96772	75	0	0
T11	2031	9	0	0
T12	24392	2054	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195991	0	0
T1	37223	510	0	0
T2	52123	647	0	0
T3	524515	14	0	0
T4	131745	306	0	0
T7	377366	11	0	0
T8	14402	26	0	0
T9	17613	143	0	0
T10	96772	75	0	0
T11	2031	8	0	0
T12	24392	1028	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	195826	0	0
GntImpliesValid_A	362355569	195826	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	195826	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2750905	0	0
ReadyAndValidImplyGrant_A	362355569	195826	0	0
ReqAndReadyImplyGrant_A	362355569	195826	0	0
ReqImpliesValid_A	362355569	488535	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	195826	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195826	0	0
T1	37223	566	0	0
T2	52123	685	0	0
T3	524515	11	0	0
T4	131745	283	0	0
T7	377366	10	0	0
T8	14402	32	0	0
T9	17613	104	0	0
T10	96772	84	0	0
T11	2031	8	0	0
T12	24392	0	0	0
T13	0	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195826	0	0
T1	37223	566	0	0
T2	52123	685	0	0
T3	524515	11	0	0
T4	131745	283	0	0
T7	377366	10	0	0
T8	14402	32	0	0
T9	17613	104	0	0
T10	96772	84	0	0
T11	2031	8	0	0
T12	24392	0	0	0
T13	0	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195826	0	0
T1	37223	566	0	0
T2	52123	685	0	0
T3	524515	11	0	0
T4	131745	283	0	0
T7	377366	10	0	0
T8	14402	32	0	0
T9	17613	104	0	0
T10	96772	84	0	0
T11	2031	8	0	0
T12	24392	0	0	0
T13	0	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2750905	0	0
T1	37223	536	0	0
T2	52123	686	0	0
T3	524515	4399	0	0
T4	131745	2062	0	0
T7	377366	1563	0	0
T8	14402	248	0	0
T9	17613	107	0	0
T10	96772	84	0	0
T11	2031	9	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195826	0	0
T1	37223	566	0	0
T2	52123	685	0	0
T3	524515	11	0	0
T4	131745	283	0	0
T7	377366	10	0	0
T8	14402	32	0	0
T9	17613	104	0	0
T10	96772	84	0	0
T11	2031	8	0	0
T12	24392	0	0	0
T13	0	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195826	0	0
T1	37223	566	0	0
T2	52123	685	0	0
T3	524515	11	0	0
T4	131745	283	0	0
T7	377366	10	0	0
T8	14402	32	0	0
T9	17613	104	0	0
T10	96772	84	0	0
T11	2031	8	0	0
T12	24392	0	0	0
T13	0	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	488535	0	0
T1	37223	599	0	0
T2	52123	700	0	0
T3	524515	11	0	0
T4	131745	357	0	0
T7	377366	354	0	0
T8	14402	33	0	0
T9	17613	108	0	0
T10	96772	87	0	0
T11	2031	8	0	0
T12	24392	0	0	0
T13	0	1560	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	195826	0	0
T1	37223	566	0	0
T2	52123	685	0	0
T3	524515	11	0	0
T4	131745	283	0	0
T7	377366	10	0	0
T8	14402	32	0	0
T9	17613	104	0	0
T10	96772	84	0	0
T11	2031	8	0	0
T12	24392	0	0	0
T13	0	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	211496	0	0
GntImpliesValid_A	362355569	211496	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	211496	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2744696	0	0
ReadyAndValidImplyGrant_A	362355569	211496	0	0
ReqAndReadyImplyGrant_A	362355569	211496	0	0
ReqImpliesValid_A	362355569	547765	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	211496	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	211496	0	0
T1	37223	523	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	341	0	0
T7	377366	13	0	0
T8	14402	28	0	0
T9	17613	124	0	0
T10	96772	1527	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	141	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	211496	0	0
T1	37223	523	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	341	0	0
T7	377366	13	0	0
T8	14402	28	0	0
T9	17613	124	0	0
T10	96772	1527	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	141	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	211496	0	0
T1	37223	523	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	341	0	0
T7	377366	13	0	0
T8	14402	28	0	0
T9	17613	124	0	0
T10	96772	1527	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	141	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2744696	0	0
T1	37223	497	0	0
T2	52123	628	0	0
T3	524515	5538	0	0
T4	131745	2464	0	0
T7	377366	3264	0	0
T8	14402	244	0	0
T9	17613	127	0	0
T10	96772	96	0	0
T11	2031	14	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	211496	0	0
T1	37223	523	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	341	0	0
T7	377366	13	0	0
T8	14402	28	0	0
T9	17613	124	0	0
T10	96772	1527	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	141	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	211496	0	0
T1	37223	523	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	341	0	0
T7	377366	13	0	0
T8	14402	28	0	0
T9	17613	124	0	0
T10	96772	1527	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	141	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	547765	0	0
T1	37223	552	0	0
T2	52123	679	0	0
T3	524515	949	0	0
T4	131745	413	0	0
T7	377366	13	0	0
T8	14402	32	0	0
T9	17613	128	0	0
T10	96772	2961	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	1376	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	211496	0	0
T1	37223	523	0	0
T2	52123	646	0	0
T3	524515	20	0	0
T4	131745	341	0	0
T7	377366	13	0	0
T8	14402	28	0	0
T9	17613	124	0	0
T10	96772	1527	0	0
T11	2031	13	0	0
T12	24392	0	0	0
T13	0	141	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	215386	0	0
GntImpliesValid_A	362355569	215386	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	215386	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2789461	0	0
ReadyAndValidImplyGrant_A	362355569	215386	0	0
ReqAndReadyImplyGrant_A	362355569	215386	0	0
ReqImpliesValid_A	362355569	550668	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	215386	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	215386	0	0
T1	37223	635	0	0
T2	52123	706	0	0
T3	524515	14	0	0
T4	131745	338	0	0
T7	377366	7	0	0
T8	14402	36	0	0
T9	17613	164	0	0
T10	96772	1098	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	149	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	215386	0	0
T1	37223	635	0	0
T2	52123	706	0	0
T3	524515	14	0	0
T4	131745	338	0	0
T7	377366	7	0	0
T8	14402	36	0	0
T9	17613	164	0	0
T10	96772	1098	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	149	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	215386	0	0
T1	37223	635	0	0
T2	52123	706	0	0
T3	524515	14	0	0
T4	131745	338	0	0
T7	377366	7	0	0
T8	14402	36	0	0
T9	17613	164	0	0
T10	96772	1098	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	149	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2789461	0	0
T1	37223	600	0	0
T2	52123	688	0	0
T3	524515	4901	0	0
T4	131745	2825	0	0
T7	377366	2602	0	0
T8	14402	298	0	0
T9	17613	164	0	0
T10	96772	207	0	0
T11	2031	13	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	215386	0	0
T1	37223	635	0	0
T2	52123	706	0	0
T3	524515	14	0	0
T4	131745	338	0	0
T7	377366	7	0	0
T8	14402	36	0	0
T9	17613	164	0	0
T10	96772	1098	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	149	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	215386	0	0
T1	37223	635	0	0
T2	52123	706	0	0
T3	524515	14	0	0
T4	131745	338	0	0
T7	377366	7	0	0
T8	14402	36	0	0
T9	17613	164	0	0
T10	96772	1098	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	149	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	550668	0	0
T1	37223	673	0	0
T2	52123	740	0	0
T3	524515	857	0	0
T4	131745	401	0	0
T7	377366	7	0	0
T8	14402	51	0	0
T9	17613	171	0	0
T10	96772	1992	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	4585	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	215386	0	0
T1	37223	635	0	0
T2	52123	706	0	0
T3	524515	14	0	0
T4	131745	338	0	0
T7	377366	7	0	0
T8	14402	36	0	0
T9	17613	164	0	0
T10	96772	1098	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	149	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	217352	0	0
GntImpliesValid_A	362355569	217352	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	217352	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2785282	0	0
ReadyAndValidImplyGrant_A	362355569	217352	0	0
ReqAndReadyImplyGrant_A	362355569	217352	0	0
ReqImpliesValid_A	362355569	549216	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	217352	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	217352	0	0
T1	37223	590	0	0
T2	52123	662	0	0
T3	524515	9	0	0
T4	131745	319	0	0
T7	377366	11	0	0
T8	14402	28	0	0
T9	17613	123	0	0
T10	96772	1629	0	0
T11	2031	17	0	0
T12	24392	510	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	217352	0	0
T1	37223	590	0	0
T2	52123	662	0	0
T3	524515	9	0	0
T4	131745	319	0	0
T7	377366	11	0	0
T8	14402	28	0	0
T9	17613	123	0	0
T10	96772	1629	0	0
T11	2031	17	0	0
T12	24392	510	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	217352	0	0
T1	37223	590	0	0
T2	52123	662	0	0
T3	524515	9	0	0
T4	131745	319	0	0
T7	377366	11	0	0
T8	14402	28	0	0
T9	17613	123	0	0
T10	96772	1629	0	0
T11	2031	17	0	0
T12	24392	510	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2785282	0	0
T1	37223	564	0	0
T2	52123	657	0	0
T3	524515	4799	0	0
T4	131745	2398	0	0
T7	377366	3155	0	0
T8	14402	225	0	0
T9	17613	127	0	0
T10	96772	90	0	0
T11	2031	18	0	0
T12	24392	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	217352	0	0
T1	37223	590	0	0
T2	52123	662	0	0
T3	524515	9	0	0
T4	131745	319	0	0
T7	377366	11	0	0
T8	14402	28	0	0
T9	17613	123	0	0
T10	96772	1629	0	0
T11	2031	17	0	0
T12	24392	510	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	217352	0	0
T1	37223	590	0	0
T2	52123	662	0	0
T3	524515	9	0	0
T4	131745	319	0	0
T7	377366	11	0	0
T8	14402	28	0	0
T9	17613	123	0	0
T10	96772	1629	0	0
T11	2031	17	0	0
T12	24392	510	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	549216	0	0
T1	37223	619	0	0
T2	52123	683	0	0
T3	524515	9	0	0
T4	131745	384	0	0
T7	377366	11	0	0
T8	14402	34	0	0
T9	17613	126	0	0
T10	96772	3171	0	0
T11	2031	17	0	0
T12	24392	1019	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	217352	0	0
T1	37223	590	0	0
T2	52123	662	0	0
T3	524515	9	0	0
T4	131745	319	0	0
T7	377366	11	0	0
T8	14402	28	0	0
T9	17613	123	0	0
T10	96772	1629	0	0
T11	2031	17	0	0
T12	24392	510	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	202972	0	0
GntImpliesValid_A	362355569	202972	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	202972	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2739030	0	0
ReadyAndValidImplyGrant_A	362355569	202972	0	0
ReqAndReadyImplyGrant_A	362355569	202972	0	0
ReqImpliesValid_A	362355569	543698	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	202972	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202972	0	0
T1	37223	565	0	0
T2	52123	816	0	0
T3	524515	18	0	0
T4	131745	321	0	0
T7	377366	4	0	0
T8	14402	37	0	0
T9	17613	128	0	0
T10	96772	571	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	125	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202972	0	0
T1	37223	565	0	0
T2	52123	816	0	0
T3	524515	18	0	0
T4	131745	321	0	0
T7	377366	4	0	0
T8	14402	37	0	0
T9	17613	128	0	0
T10	96772	571	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	125	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202972	0	0
T1	37223	565	0	0
T2	52123	816	0	0
T3	524515	18	0	0
T4	131745	321	0	0
T7	377366	4	0	0
T8	14402	37	0	0
T9	17613	128	0	0
T10	96772	571	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	125	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2739030	0	0
T1	37223	550	0	0
T2	52123	790	0	0
T3	524515	7027	0	0
T4	131745	2417	0	0
T7	377366	1159	0	0
T8	14402	319	0	0
T9	17613	127	0	0
T10	96772	84	0	0
T11	2031	13	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202972	0	0
T1	37223	565	0	0
T2	52123	816	0	0
T3	524515	18	0	0
T4	131745	321	0	0
T7	377366	4	0	0
T8	14402	37	0	0
T9	17613	128	0	0
T10	96772	571	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	125	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202972	0	0
T1	37223	565	0	0
T2	52123	816	0	0
T3	524515	18	0	0
T4	131745	321	0	0
T7	377366	4	0	0
T8	14402	37	0	0
T9	17613	128	0	0
T10	96772	571	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	125	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	543698	0	0
T1	37223	583	0	0
T2	52123	857	0	0
T3	524515	18	0	0
T4	131745	365	0	0
T7	377366	4	0	0
T8	14402	42	0	0
T9	17613	136	0	0
T10	96772	1061	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	1013	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202972	0	0
T1	37223	565	0	0
T2	52123	816	0	0
T3	524515	18	0	0
T4	131745	321	0	0
T7	377366	4	0	0
T8	14402	37	0	0
T9	17613	128	0	0
T10	96772	571	0	0
T11	2031	12	0	0
T12	24392	0	0	0
T13	0	125	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	209174	0	0
GntImpliesValid_A	362355569	209174	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	209174	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2773324	0	0
ReadyAndValidImplyGrant_A	362355569	209174	0	0
ReqAndReadyImplyGrant_A	362355569	209174	0	0
ReqImpliesValid_A	362355569	525330	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	209174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	209174	0	0
T1	37223	581	0	0
T2	52123	686	0	0
T3	524515	18	0	0
T4	131745	320	0	0
T7	377366	18	0	0
T8	14402	29	0	0
T9	17613	147	0	0
T10	96772	465	0	0
T11	2031	7	0	0
T12	24392	0	0	0
T13	0	138	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	209174	0	0
T1	37223	581	0	0
T2	52123	686	0	0
T3	524515	18	0	0
T4	131745	320	0	0
T7	377366	18	0	0
T8	14402	29	0	0
T9	17613	147	0	0
T10	96772	465	0	0
T11	2031	7	0	0
T12	24392	0	0	0
T13	0	138	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	209174	0	0
T1	37223	581	0	0
T2	52123	686	0	0
T3	524515	18	0	0
T4	131745	320	0	0
T7	377366	18	0	0
T8	14402	29	0	0
T9	17613	147	0	0
T10	96772	465	0	0
T11	2031	7	0	0
T12	24392	0	0	0
T13	0	138	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2773324	0	0
T1	37223	562	0	0
T2	52123	674	0	0
T3	524515	7616	0	0
T4	131745	2503	0	0
T7	377366	6863	0	0
T8	14402	199	0	0
T9	17613	146	0	0
T10	96772	66	0	0
T11	2031	8	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	209174	0	0
T1	37223	581	0	0
T2	52123	686	0	0
T3	524515	18	0	0
T4	131745	320	0	0
T7	377366	18	0	0
T8	14402	29	0	0
T9	17613	147	0	0
T10	96772	465	0	0
T11	2031	7	0	0
T12	24392	0	0	0
T13	0	138	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	209174	0	0
T1	37223	581	0	0
T2	52123	686	0	0
T3	524515	18	0	0
T4	131745	320	0	0
T7	377366	18	0	0
T8	14402	29	0	0
T9	17613	147	0	0
T10	96772	465	0	0
T11	2031	7	0	0
T12	24392	0	0	0
T13	0	138	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	525330	0	0
T1	37223	603	0	0
T2	52123	713	0	0
T3	524515	18	0	0
T4	131745	435	0	0
T7	377366	395	0	0
T8	14402	29	0	0
T9	17613	155	0	0
T10	96772	867	0	0
T11	2031	7	0	0
T12	24392	0	0	0
T13	0	3977	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	209174	0	0
T1	37223	581	0	0
T2	52123	686	0	0
T3	524515	18	0	0
T4	131745	320	0	0
T7	377366	18	0	0
T8	14402	29	0	0
T9	17613	147	0	0
T10	96772	465	0	0
T11	2031	7	0	0
T12	24392	0	0	0
T13	0	138	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	202603	0	0
GntImpliesValid_A	362355569	202603	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	202603	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2716579	0	0
ReadyAndValidImplyGrant_A	362355569	202603	0	0
ReqAndReadyImplyGrant_A	362355569	202603	0	0
ReqImpliesValid_A	362355569	516095	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	202603	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202603	0	0
T1	37223	547	0	0
T2	52123	665	0	0
T3	524515	8	0	0
T4	131745	311	0	0
T7	377366	9	0	0
T8	14402	23	0	0
T9	17613	127	0	0
T10	96772	974	0	0
T11	2031	15	0	0
T12	24392	450	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202603	0	0
T1	37223	547	0	0
T2	52123	665	0	0
T3	524515	8	0	0
T4	131745	311	0	0
T7	377366	9	0	0
T8	14402	23	0	0
T9	17613	127	0	0
T10	96772	974	0	0
T11	2031	15	0	0
T12	24392	450	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202603	0	0
T1	37223	547	0	0
T2	52123	665	0	0
T3	524515	8	0	0
T4	131745	311	0	0
T7	377366	9	0	0
T8	14402	23	0	0
T9	17613	127	0	0
T10	96772	974	0	0
T11	2031	15	0	0
T12	24392	450	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2716579	0	0
T1	37223	533	0	0
T2	52123	654	0	0
T3	524515	3554	0	0
T4	131745	2283	0	0
T7	377366	2978	0	0
T8	14402	215	0	0
T9	17613	131	0	0
T10	96772	92	0	0
T11	2031	13	0	0
T12	24392	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202603	0	0
T1	37223	547	0	0
T2	52123	665	0	0
T3	524515	8	0	0
T4	131745	311	0	0
T7	377366	9	0	0
T8	14402	23	0	0
T9	17613	127	0	0
T10	96772	974	0	0
T11	2031	15	0	0
T12	24392	450	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202603	0	0
T1	37223	547	0	0
T2	52123	665	0	0
T3	524515	8	0	0
T4	131745	311	0	0
T7	377366	9	0	0
T8	14402	23	0	0
T9	17613	127	0	0
T10	96772	974	0	0
T11	2031	15	0	0
T12	24392	450	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	516095	0	0
T1	37223	564	0	0
T2	52123	691	0	0
T3	524515	8	0	0
T4	131745	388	0	0
T7	377366	9	0	0
T8	14402	23	0	0
T9	17613	130	0	0
T10	96772	1859	0	0
T11	2031	18	0	0
T12	24392	899	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	202603	0	0
T1	37223	547	0	0
T2	52123	665	0	0
T3	524515	8	0	0
T4	131745	311	0	0
T7	377366	9	0	0
T8	14402	23	0	0
T9	17613	127	0	0
T10	96772	974	0	0
T11	2031	15	0	0
T12	24392	450	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	189906	0	0
GntImpliesValid_A	362355569	189906	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	189906	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	2705028	0	0
ReadyAndValidImplyGrant_A	362355569	189906	0	0
ReqAndReadyImplyGrant_A	362355569	189906	0	0
ReqImpliesValid_A	362355569	443089	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	0	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	189906	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	189906	0	0
T1	37223	586	0	0
T2	52123	628	0	0
T3	524515	12	0	0
T4	131745	301	0	0
T7	377366	10	0	0
T8	14402	16	0	0
T9	17613	288	0	0
T10	96772	82	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	189906	0	0
T1	37223	586	0	0
T2	52123	628	0	0
T3	524515	12	0	0
T4	131745	301	0	0
T7	377366	10	0	0
T8	14402	16	0	0
T9	17613	288	0	0
T10	96772	82	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	189906	0	0
T1	37223	586	0	0
T2	52123	628	0	0
T3	524515	12	0	0
T4	131745	301	0	0
T7	377366	10	0	0
T8	14402	16	0	0
T9	17613	288	0	0
T10	96772	82	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2705028	0	0
T1	37223	563	0	0
T2	52123	624	0	0
T3	524515	3783	0	0
T4	131745	2284	0	0
T7	377366	3308	0	0
T8	14402	125	0	0
T9	17613	255	0	0
T10	96772	82	0	0
T11	2031	16	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	189906	0	0
T1	37223	586	0	0
T2	52123	628	0	0
T3	524515	12	0	0
T4	131745	301	0	0
T7	377366	10	0	0
T8	14402	16	0	0
T9	17613	288	0	0
T10	96772	82	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	189906	0	0
T1	37223	586	0	0
T2	52123	628	0	0
T3	524515	12	0	0
T4	131745	301	0	0
T7	377366	10	0	0
T8	14402	16	0	0
T9	17613	288	0	0
T10	96772	82	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	443089	0	0
T1	37223	612	0	0
T2	52123	648	0	0
T3	524515	12	0	0
T4	131745	349	0	0
T7	377366	10	0	0
T8	14402	24	0	0
T9	17613	327	0	0
T10	96772	85	0	0
T11	2031	17	0	0
T12	24392	0	0	0
T13	0	3474	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	189906	0	0
T1	37223	586	0	0
T2	52123	628	0	0
T3	524515	12	0	0
T4	131745	301	0	0
T7	377366	10	0	0
T8	14402	16	0	0
T9	17613	288	0	0
T10	96772	82	0	0
T11	2031	16	0	0
T12	24392	0	0	0
T13	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	820982	0	0
GntImpliesValid_A	362355569	820982	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	820982	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	10472377	0	0
ReadyAndValidImplyGrant_A	362355569	820982	0	0
ReqAndReadyImplyGrant_A	362355569	820982	0	0
ReqImpliesValid_A	362355569	2090220	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	18411	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	820982	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	820982	0	0
T1	37223	2140	0	0
T2	52123	3714	0	0
T3	524515	50	0	0
T4	131745	1293	0	0
T7	377366	50	0	0
T8	14402	121	0	0
T9	17613	775	0	0
T10	96772	2247	0	0
T11	2031	45	0	0
T12	24392	1988	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	820982	0	0
T1	37223	2140	0	0
T2	52123	3714	0	0
T3	524515	50	0	0
T4	131745	1293	0	0
T7	377366	50	0	0
T8	14402	121	0	0
T9	17613	775	0	0
T10	96772	2247	0	0
T11	2031	45	0	0
T12	24392	1988	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	820982	0	0
T1	37223	2140	0	0
T2	52123	3714	0	0
T3	524515	50	0	0
T4	131745	1293	0	0
T7	377366	50	0	0
T8	14402	121	0	0
T9	17613	775	0	0
T10	96772	2247	0	0
T11	2031	45	0	0
T12	24392	1988	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	10472377	0	0
T1	37223	3	0	0
T2	52123	16	0	0
T3	524515	16592	0	0
T4	131745	8681	0	0
T7	377366	14656	0	0
T8	14402	771	0	0
T9	17613	7	0	0
T10	96772	3	0	0
T11	2031	1	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	820982	0	0
T1	37223	2140	0	0
T2	52123	3714	0	0
T3	524515	50	0	0
T4	131745	1293	0	0
T7	377366	50	0	0
T8	14402	121	0	0
T9	17613	775	0	0
T10	96772	2247	0	0
T11	2031	45	0	0
T12	24392	1988	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	820982	0	0
T1	37223	2140	0	0
T2	52123	3714	0	0
T3	524515	50	0	0
T4	131745	1293	0	0
T7	377366	50	0	0
T8	14402	121	0	0
T9	17613	775	0	0
T10	96772	2247	0	0
T11	2031	45	0	0
T12	24392	1988	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	2090220	0	0
T1	37223	2140	0	0
T2	52123	3714	0	0
T3	524515	890	0	0
T4	131745	1916	0	0
T7	377366	721	0	0
T8	14402	160	0	0
T9	17613	775	0	0
T10	96772	2247	0	0
T11	2031	45	0	0
T12	24392	1988	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	18411	0	900
T1	37223	46	0	1
T2	52123	143	0	1
T3	524515	0	0	1
T4	131745	2	0	1
T7	377366	0	0	1
T8	14402	0	0	1
T9	17613	9	0	1
T10	96772	1	0	1
T11	2031	0	0	1
T12	24392	585	0	1
T16	0	1	0	0
T18	0	22	0	0
T20	0	8	0	0
T21	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	820982	0	0
T1	37223	2140	0	0
T2	52123	3714	0	0
T3	524515	50	0	0
T4	131745	1293	0	0
T7	377366	50	0	0
T8	14402	121	0	0
T9	17613	775	0	0
T10	96772	2247	0	0
T11	2031	45	0	0
T12	24392	1988	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362355569	362228352	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	362355569	822915	0	0
GntImpliesValid_A	362355569	822915	0	0
GrantKnown_A	362355569	362228352	0	0
IdxKnown_A	362355569	362228352	0	0
IndexIsCorrect_A	362355569	822915	0	0
LockArbDecision_A	362355569	0	0	0
NoReadyValidNoGrant_A	362355569	304456907	0	0
ReadyAndValidImplyGrant_A	362355569	822915	0	0
ReqAndReadyImplyGrant_A	362355569	822915	0	0
ReqImpliesValid_A	362355569	12249742	0	0
ReqStaysHighUntilGranted0_M	362355569	0	0	0
RoundRobin_A	362355569	27252	0	900
ValidKnown_A	362355569	362228352	0	0
gen_data_port_assertion.DataFlow_A	362355569	822915	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	822915	0	0
T1	37223	2242	0	0
T2	52123	2906	0	0
T3	524515	66	0	0
T4	131745	1181	0	0
T7	377366	57	0	0
T8	14402	114	0	0
T9	17613	716	0	0
T10	96772	3089	0	0
T11	2031	41	0	0
T12	24392	665	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	822915	0	0
T1	37223	2242	0	0
T2	52123	2906	0	0
T3	524515	66	0	0
T4	131745	1181	0	0
T7	377366	57	0	0
T8	14402	114	0	0
T9	17613	716	0	0
T10	96772	3089	0	0
T11	2031	41	0	0
T12	24392	665	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	822915	0	0
T1	37223	2242	0	0
T2	52123	2906	0	0
T3	524515	66	0	0
T4	131745	1181	0	0
T7	377366	57	0	0
T8	14402	114	0	0
T9	17613	716	0	0
T10	96772	3089	0	0
T11	2031	41	0	0
T12	24392	665	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	304456907	0	0
T1	37223	1	0	0
T2	52123	1	0	0
T3	524515	503386	0	0
T4	131745	111289	0	0
T7	377366	348448	0	0
T8	14402	12293	0	0
T9	17613	1	0	0
T10	96772	1	0	0
T11	2031	1	0	0
T12	24392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	822915	0	0
T1	37223	2242	0	0
T2	52123	2906	0	0
T3	524515	66	0	0
T4	131745	1181	0	0
T7	377366	57	0	0
T8	14402	114	0	0
T9	17613	716	0	0
T10	96772	3089	0	0
T11	2031	41	0	0
T12	24392	665	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	822915	0	0
T1	37223	2242	0	0
T2	52123	2906	0	0
T3	524515	66	0	0
T4	131745	1181	0	0
T7	377366	57	0	0
T8	14402	114	0	0
T9	17613	716	0	0
T10	96772	3089	0	0
T11	2031	41	0	0
T12	24392	665	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	12249742	0	0
T1	37223	2242	0	0
T2	52123	2906	0	0
T3	524515	20129	0	0
T4	131745	9639	0	0
T7	377366	18936	0	0
T8	14402	878	0	0
T9	17613	716	0	0
T10	96772	3089	0	0
T11	2031	41	0	0
T12	24392	665	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	27252	0	900
T1	37223	35	0	1
T2	52123	44	0	1
T3	524515	0	0	1
T4	131745	0	0	1
T7	377366	0	0	1
T8	14402	0	0	1
T9	17613	11	0	1
T10	96772	374	0	1
T11	2031	0	0	1
T12	24392	0	0	1
T14	0	1	0	0
T15	0	13	0	0
T16	0	29	0	0
T17	0	1	0	0
T18	0	20	0	0
T19	0	402	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	362228352	0	0
T1	37223	37106	0	0
T2	52123	50822	0	0
T3	524515	524484	0	0
T4	131745	131597	0	0
T7	377366	377334	0	0
T8	14402	14369	0	0
T9	17613	16613	0	0
T10	96772	96594	0	0
T11	2031	2005	0	0
T12	24392	24372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362355569	822915	0	0
T1	37223	2242	0	0
T2	52123	2906	0	0
T3	524515	66	0	0
T4	131745	1181	0	0
T7	377366	57	0	0
T8	14402	114	0	0
T9	17613	716	0	0
T10	96772	3089	0	0
T11	2031	41	0	0
T12	24392	665	0	0