Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1471299	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

233288

1

T1

29

T2

67

T3

41

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	579395	1			T1	55		T2	272		T3	204
values[0x0]	544380	1			T1	67		T2	48		T3	26
values[0x1]	580812	1			T1	70		T2	277		T3	195

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1136038	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

568549

1

T1

59

T2

235

T3

172

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27222	1			T2	10		T9	60		T7	1
valid_sources[0x01]	27243	1			T1	3		T2	7		T3	1
valid_sources[0x02]	26470	1			T2	6		T3	5		T9	89
valid_sources[0x03]	27940	1			T2	6		T3	3		T9	74
valid_sources[0x04]	26692	1			T1	10		T2	12		T3	3
valid_sources[0x05]	26366	1			T2	8		T3	5		T9	88
valid_sources[0x06]	26625	1			T2	7		T9	88		T8	7
valid_sources[0x07]	26699	1			T2	10		T3	8		T9	56
valid_sources[0x08]	26016	1			T2	8		T3	5		T9	70
valid_sources[0x09]	27200	1			T1	33		T2	4		T3	4
valid_sources[0x0a]	26369	1			T2	12		T3	15		T9	82
valid_sources[0x0b]	25685	1			T2	7		T3	3		T9	29
valid_sources[0x0c]	26758	1			T2	9		T3	2		T9	15
valid_sources[0x0d]	26489	1			T2	8		T3	2		T9	50
valid_sources[0x0e]	26495	1			T1	11		T2	6		T3	5
valid_sources[0x0f]	26626	1			T2	10		T3	4		T9	106
valid_sources[0x10]	26854	1			T2	11		T3	9		T9	43
valid_sources[0x11]	26841	1			T2	12		T3	11		T9	170
valid_sources[0x12]	26010	1			T2	9		T3	10		T9	83
valid_sources[0x13]	27626	1			T1	2		T2	14		T3	14
valid_sources[0x14]	27476	1			T2	10		T3	2		T9	111
valid_sources[0x15]	26433	1			T1	11		T2	7		T3	6
valid_sources[0x16]	26530	1			T2	10		T3	3		T9	3
valid_sources[0x17]	26859	1			T2	7		T3	1		T9	58
valid_sources[0x18]	26312	1			T1	29		T2	6		T3	11
valid_sources[0x19]	25441	1			T2	7		T3	20		T9	147
valid_sources[0x1a]	27459	1			T1	7		T2	9		T3	6
valid_sources[0x1b]	26858	1			T2	10		T3	7		T9	54
valid_sources[0x1c]	26309	1			T2	7		T3	6		T9	77
valid_sources[0x1d]	26336	1			T2	11		T3	7		T9	124
valid_sources[0x1e]	25845	1			T2	11		T3	13		T9	14
valid_sources[0x1f]	26165	1			T2	12		T3	7		T9	120
valid_sources[0x20]	27144	1			T2	11		T3	3		T9	64

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24733

1

T1

1

T2

26

T3

11

values[0x0]

all_enables

biggest_size

183791

1

T1

28

T2

21

T3

16

values[0x1]

all_enables

biggest_size

24764

1

T2

20

T3

14

T9

72

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1476971	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

240258

1

T1

24

T2

66

T3

41

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	589273	1			T1	68		T2	282		T3	217
values[0x0]	538742	1			T1	43		T2	46		T3	34
values[0x1]	589214	1			T1	63		T2	306		T3	201

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1133010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

584219

1

T1

75

T2

237

T3

159

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26614	1			T1	1		T2	2		T3	6
valid_sources[0x01]	27336	1			T1	2		T2	10		T3	11
valid_sources[0x02]	26593	1			T1	1		T2	3		T3	5
valid_sources[0x03]	26792	1			T1	4		T2	6		T3	6
valid_sources[0x04]	26815	1			T1	2		T2	12		T3	5
valid_sources[0x05]	26211	1			T1	4		T2	9		T3	9
valid_sources[0x06]	26936	1			T2	15		T3	4		T9	110
valid_sources[0x07]	27496	1			T1	3		T2	12		T3	9
valid_sources[0x08]	26004	1			T1	1		T2	12		T3	4
valid_sources[0x09]	26905	1			T1	1		T2	15		T3	5
valid_sources[0x0a]	26540	1			T2	3		T3	6		T9	112
valid_sources[0x0b]	27418	1			T1	4		T2	2		T3	9
valid_sources[0x0c]	26871	1			T1	4		T2	8		T3	8
valid_sources[0x0d]	26183	1			T1	1		T2	3		T3	3
valid_sources[0x0e]	27270	1			T1	5		T2	19		T3	9
valid_sources[0x0f]	27368	1			T1	2		T2	16		T3	5
valid_sources[0x10]	26371	1			T1	2		T2	22		T3	5
valid_sources[0x11]	26613	1			T1	5		T2	10		T3	12
valid_sources[0x12]	26511	1			T1	8		T2	14		T3	5
valid_sources[0x13]	26346	1			T2	10		T3	11		T9	118
valid_sources[0x14]	28248	1			T1	1		T2	8		T3	8
valid_sources[0x15]	27308	1			T2	14		T3	6		T9	131
valid_sources[0x16]	26622	1			T2	7		T3	2		T9	104
valid_sources[0x17]	26822	1			T1	4		T2	7		T3	6
valid_sources[0x18]	26889	1			T1	11		T2	15		T3	8
valid_sources[0x19]	27195	1			T2	9		T3	8		T9	136
valid_sources[0x1a]	26688	1			T1	3		T2	2		T3	7
valid_sources[0x1b]	26764	1			T2	10		T3	6		T9	99
valid_sources[0x1c]	27735	1			T2	5		T3	6		T9	105
valid_sources[0x1d]	26626	1			T2	17		T3	9		T9	83
valid_sources[0x1e]	26233	1			T2	7		T3	7		T9	70
valid_sources[0x1f]	26787	1			T2	7		T3	8		T9	136
valid_sources[0x20]	26801	1			T1	1		T2	8		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25585

1

T1

2

T2

19

T3

14

values[0x0]

all_enables

biggest_size

189216

1

T1

20

T2

22

T3

12

values[0x1]

all_enables

biggest_size

25457

1

T1

2

T2

25

T3

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1477589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

235302

1

T1

16

T2

56

T3

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	583051	1			T1	28		T2	272		T3	227
values[0x0]	548632	1			T1	32		T2	44		T3	33
values[0x1]	581208	1			T1	40		T2	261		T3	176

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1141198	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

571693

1

T1

34

T2

227

T3

160

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26788	1			T2	12		T3	5		T9	80
valid_sources[0x01]	27240	1			T2	9		T3	3		T9	66
valid_sources[0x02]	26575	1			T2	4		T3	9		T9	66
valid_sources[0x03]	26568	1			T2	12		T3	8		T9	131
valid_sources[0x04]	26429	1			T2	12		T3	7		T9	48
valid_sources[0x05]	26640	1			T2	6		T3	8		T9	77
valid_sources[0x06]	27374	1			T2	10		T3	3		T9	85
valid_sources[0x07]	27166	1			T2	13		T3	6		T9	83
valid_sources[0x08]	26955	1			T2	8		T3	7		T9	79
valid_sources[0x09]	26846	1			T2	10		T3	5		T9	85
valid_sources[0x0a]	26271	1			T2	11		T3	6		T9	79
valid_sources[0x0b]	26820	1			T2	9		T3	9		T9	63
valid_sources[0x0c]	26863	1			T2	8		T3	5		T9	74
valid_sources[0x0d]	26996	1			T2	7		T3	8		T9	47
valid_sources[0x0e]	27186	1			T2	12		T3	10		T9	94
valid_sources[0x0f]	26469	1			T2	8		T3	4		T9	102
valid_sources[0x10]	26310	1			T2	17		T3	4		T9	75
valid_sources[0x11]	26656	1			T1	18		T2	16		T3	9
valid_sources[0x12]	26266	1			T2	11		T3	2		T9	100
valid_sources[0x13]	26214	1			T2	18		T3	11		T9	61
valid_sources[0x14]	27291	1			T2	8		T3	5		T9	84
valid_sources[0x15]	26815	1			T2	7		T3	6		T9	73
valid_sources[0x16]	26703	1			T2	2		T3	7		T9	55
valid_sources[0x17]	26694	1			T2	7		T3	7		T9	88
valid_sources[0x18]	27197	1			T2	4		T3	11		T9	85
valid_sources[0x19]	27136	1			T2	13		T3	3		T9	96
valid_sources[0x1a]	26424	1			T1	12		T2	2		T3	7
valid_sources[0x1b]	26738	1			T2	9		T3	8		T9	110
valid_sources[0x1c]	27129	1			T2	5		T3	7		T9	90
valid_sources[0x1d]	26797	1			T2	6		T3	15		T9	103
valid_sources[0x1e]	26104	1			T1	21		T2	5		T3	4
valid_sources[0x1f]	26385	1			T2	6		T3	10		T9	83
valid_sources[0x20]	27769	1			T1	5		T2	9		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25133

1

T2

18

T3

14

T9

87

values[0x0]

all_enables

biggest_size

185368

1

T1

13

T2

15

T3

18

values[0x1]

all_enables

biggest_size

24801

1

T1

3

T2

23

T3

16