Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1497267 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 237380 1 T1 570 T2 648 T3 198


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 589147 1 T1 1399 T2 1629 T3 407
values[0x0] 555701 1 T1 1380 T2 1549 T3 424
values[0x1] 589799 1 T1 1382 T2 1627 T3 443


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1156799 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 577848 1 T1 1367 T2 1576 T3 430


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26415 1 T1 71 T2 83 T3 15
valid_sources[0x01] 26705 1 T1 58 T2 107 T3 18
valid_sources[0x02] 26604 1 T1 73 T2 132 T3 19
valid_sources[0x03] 27212 1 T1 64 T2 105 T3 12
valid_sources[0x04] 26786 1 T1 82 T2 78 T3 21
valid_sources[0x05] 26640 1 T1 54 T2 63 T3 15
valid_sources[0x06] 26486 1 T1 55 T2 49 T3 20
valid_sources[0x07] 27628 1 T1 45 T2 64 T3 22
valid_sources[0x08] 27265 1 T1 53 T2 43 T3 17
valid_sources[0x09] 27133 1 T1 60 T2 112 T3 15
valid_sources[0x0a] 27471 1 T1 71 T2 80 T3 19
valid_sources[0x0b] 27182 1 T1 59 T2 80 T3 17
valid_sources[0x0c] 27568 1 T1 57 T2 49 T3 32
valid_sources[0x0d] 27031 1 T1 74 T2 164 T3 14
valid_sources[0x0e] 28281 1 T1 70 T2 40 T3 31
valid_sources[0x0f] 26929 1 T1 43 T2 50 T3 12
valid_sources[0x10] 27765 1 T1 61 T2 111 T3 24
valid_sources[0x11] 27650 1 T1 66 T2 60 T3 28
valid_sources[0x12] 27156 1 T1 61 T2 62 T3 19
valid_sources[0x13] 26805 1 T1 40 T2 67 T3 22
valid_sources[0x14] 27569 1 T1 55 T2 76 T3 28
valid_sources[0x15] 27047 1 T1 67 T2 72 T3 24
valid_sources[0x16] 27404 1 T1 72 T2 29 T3 18
valid_sources[0x17] 26110 1 T1 51 T2 74 T3 23
valid_sources[0x18] 26560 1 T1 60 T2 154 T3 21
valid_sources[0x19] 26561 1 T1 57 T2 119 T3 10
valid_sources[0x1a] 26644 1 T1 69 T2 129 T3 19
valid_sources[0x1b] 26107 1 T1 70 T2 32 T3 20
valid_sources[0x1c] 27286 1 T1 67 T2 34 T3 17
valid_sources[0x1d] 27951 1 T1 67 T2 123 T3 17
valid_sources[0x1e] 28421 1 T1 77 T2 63 T3 29
valid_sources[0x1f] 27642 1 T1 68 T2 60 T3 24
valid_sources[0x20] 27361 1 T1 70 T2 50 T3 17


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24960 1 T1 56 T2 74 T3 18
values[0x0] all_enables biggest_size 187210 1 T1 461 T2 510 T3 160
values[0x1] all_enables biggest_size 25210 1 T1 53 T2 64 T3 20


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1509989 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 244979 1 T1 585 T2 671 T3 219


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 601057 1 T1 1398 T2 1680 T3 525
values[0x0] 552062 1 T1 1329 T2 1520 T3 466
values[0x1] 601849 1 T1 1382 T2 1655 T3 512


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1159531 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 595437 1 T1 1423 T2 1615 T3 519


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27068 1 T1 64 T2 77 T3 17
valid_sources[0x01] 27626 1 T1 52 T2 77 T3 22
valid_sources[0x02] 26979 1 T1 66 T2 108 T3 28
valid_sources[0x03] 27658 1 T1 71 T2 84 T3 25
valid_sources[0x04] 27302 1 T1 63 T2 102 T3 29
valid_sources[0x05] 27862 1 T1 57 T2 43 T3 27
valid_sources[0x06] 27613 1 T1 67 T2 47 T3 19
valid_sources[0x07] 27753 1 T1 66 T2 74 T3 16
valid_sources[0x08] 27372 1 T1 64 T2 66 T3 20
valid_sources[0x09] 27529 1 T1 61 T2 65 T3 33
valid_sources[0x0a] 27748 1 T1 64 T2 73 T3 27
valid_sources[0x0b] 27764 1 T1 81 T2 107 T3 21
valid_sources[0x0c] 27843 1 T1 58 T2 44 T3 17
valid_sources[0x0d] 27282 1 T1 54 T2 78 T3 21
valid_sources[0x0e] 27613 1 T1 61 T2 71 T3 22
valid_sources[0x0f] 27706 1 T1 70 T2 61 T3 27
valid_sources[0x10] 27606 1 T1 67 T2 87 T3 21
valid_sources[0x11] 27593 1 T1 87 T2 77 T3 12
valid_sources[0x12] 27569 1 T1 73 T2 83 T3 10
valid_sources[0x13] 27564 1 T1 67 T2 70 T3 19
valid_sources[0x14] 27037 1 T1 62 T2 95 T3 21
valid_sources[0x15] 27564 1 T1 78 T2 70 T3 26
valid_sources[0x16] 27366 1 T1 76 T2 66 T3 19
valid_sources[0x17] 27978 1 T1 48 T2 65 T3 25
valid_sources[0x18] 27888 1 T1 70 T2 138 T3 20
valid_sources[0x19] 26670 1 T1 67 T2 104 T3 18
valid_sources[0x1a] 26616 1 T1 72 T2 88 T3 31
valid_sources[0x1b] 26796 1 T1 50 T2 90 T3 27
valid_sources[0x1c] 26917 1 T1 52 T2 54 T3 29
valid_sources[0x1d] 27368 1 T1 68 T2 98 T3 23
valid_sources[0x1e] 27751 1 T1 38 T2 77 T3 33
valid_sources[0x1f] 27873 1 T1 69 T2 75 T3 16
valid_sources[0x20] 27081 1 T1 49 T2 72 T3 14


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26174 1 T1 55 T2 75 T3 22
values[0x0] all_enables biggest_size 192999 1 T1 473 T2 538 T3 179
values[0x1] all_enables biggest_size 25806 1 T1 57 T2 58 T3 18


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1509905 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 238644 1 T1 600 T2 646 T3 193


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 595603 1 T1 1337 T2 1608 T3 434
values[0x0] 558315 1 T1 1414 T2 1603 T3 465
values[0x1] 594631 1 T1 1417 T2 1612 T3 449


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1165568 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 582981 1 T1 1410 T2 1588 T3 426


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27553 1 T1 73 T2 69 T3 23
valid_sources[0x01] 26626 1 T1 75 T2 85 T3 21
valid_sources[0x02] 26786 1 T1 55 T2 101 T3 13
valid_sources[0x03] 27580 1 T1 64 T2 64 T3 60
valid_sources[0x04] 26792 1 T1 75 T2 100 T3 35
valid_sources[0x05] 27218 1 T1 86 T2 50 T3 16
valid_sources[0x06] 26740 1 T1 63 T2 63 T3 29
valid_sources[0x07] 27492 1 T1 66 T2 91 T3 52
valid_sources[0x08] 26610 1 T1 53 T2 73 T3 29
valid_sources[0x09] 27090 1 T1 44 T2 59 T3 6
valid_sources[0x0a] 27626 1 T1 68 T2 67 T3 54
valid_sources[0x0b] 27732 1 T1 66 T2 82 T3 14
valid_sources[0x0c] 26892 1 T1 70 T2 47 T3 29
valid_sources[0x0d] 27659 1 T1 51 T2 68 T3 28
valid_sources[0x0e] 27728 1 T1 87 T2 41 T3 33
valid_sources[0x0f] 26556 1 T1 65 T2 61 T3 14
valid_sources[0x10] 27751 1 T1 65 T2 76 T3 11
valid_sources[0x11] 26898 1 T1 74 T2 87 T3 13
valid_sources[0x12] 27385 1 T1 58 T2 81 T3 35
valid_sources[0x13] 28004 1 T1 69 T2 84 T3 11
valid_sources[0x14] 28603 1 T1 71 T2 97 T3 18
valid_sources[0x15] 26871 1 T1 63 T2 53 T3 27
valid_sources[0x16] 26869 1 T1 74 T2 42 T3 14
valid_sources[0x17] 27610 1 T1 53 T2 84 T3 53
valid_sources[0x18] 28202 1 T1 65 T2 114 T3 19
valid_sources[0x19] 27071 1 T1 53 T2 117 T3 1
valid_sources[0x1a] 26433 1 T1 72 T2 64 T3 15
valid_sources[0x1b] 26531 1 T1 55 T2 56 T3 17
valid_sources[0x1c] 27197 1 T1 69 T2 80 T3 29
valid_sources[0x1d] 27866 1 T1 72 T2 109 T3 11
valid_sources[0x1e] 26871 1 T1 73 T2 72 T3 19
valid_sources[0x1f] 27805 1 T1 65 T2 79 T3 7
valid_sources[0x20] 26542 1 T1 65 T2 70 T3 24


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25319 1 T1 70 T2 57 T3 19
values[0x0] all_enables biggest_size 188043 1 T1 473 T2 529 T3 155
values[0x1] all_enables biggest_size 25282 1 T1 57 T2 60 T3 19

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%