Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7975695	0	0
GntImpliesValid_A	2147483647	7975695	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7975695	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	469036554	0	0
ReadyAndValidImplyGrant_A	2147483647	7975695	0	0
ReqAndReadyImplyGrant_A	2147483647	7975695	0	0
ReqImpliesValid_A	2147483647	39179770	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	38278	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7975695	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3165168	3164112	0	0
T2	3405456	3403104	0	0
T3	4317768	4317600	0	0
T7	5930616	5929584	0	0
T8	7228440	7227816	0	0
T9	302472	301680	0	0
T10	767496	767256	0	0
T11	456912	455568	0	0
T12	2116920	2114712	0	0
T13	2341632	2339712	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7975695	0	0
T1	1978230	12436	0	0
T2	3405456	14460	0	0
T3	4317768	4123	0	0
T7	5930616	20668	0	0
T8	7228440	478	0	0
T9	302472	494	0	0
T10	767496	3547	0	0
T11	456912	1257	0	0
T12	2116920	8292	0	0
T13	2341632	10054	0	0
T14	1628766	1584	0	0
T15	0	2672	0	0
T16	0	368	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7975695	0	0
T1	1978230	12436	0	0
T2	3405456	14460	0	0
T3	4317768	4123	0	0
T7	5930616	20668	0	0
T8	7228440	478	0	0
T9	302472	494	0	0
T10	767496	3547	0	0
T11	456912	1257	0	0
T12	2116920	8292	0	0
T13	2341632	10054	0	0
T14	1628766	1584	0	0
T15	0	2672	0	0
T16	0	368	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3165168	3164112	0	0
T2	3405456	3403104	0	0
T3	4317768	4317600	0	0
T7	5930616	5929584	0	0
T8	7228440	7227816	0	0
T9	302472	301680	0	0
T10	767496	767256	0	0
T11	456912	455568	0	0
T12	2116920	2114712	0	0
T13	2341632	2339712	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3165168	3164112	0	0
T2	3405456	3403104	0	0
T3	4317768	4317600	0	0
T7	5930616	5929584	0	0
T8	7228440	7227816	0	0
T9	302472	301680	0	0
T10	767496	767256	0	0
T11	456912	455568	0	0
T12	2116920	2114712	0	0
T13	2341632	2339712	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7975695	0	0
T1	1978230	12436	0	0
T2	3405456	14460	0	0
T3	4317768	4123	0	0
T7	5930616	20668	0	0
T8	7228440	478	0	0
T9	302472	494	0	0
T10	767496	3547	0	0
T11	456912	1257	0	0
T12	2116920	8292	0	0
T13	2341632	10054	0	0
T14	1628766	1584	0	0
T15	0	2672	0	0
T16	0	368	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	469036554	0	0
T1	3165168	153885	0	0
T2	3405456	200655	0	0
T3	4317768	1377649	0	0
T7	5930616	329051	0	0
T8	7228440	252657	0	0
T9	302472	15122	0	0
T10	767496	46675	0	0
T11	456912	25168	0	0
T12	2116920	140194	0	0
T13	2341632	106104	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7975695	0	0
T1	1978230	12436	0	0
T2	3405456	14460	0	0
T3	4317768	4123	0	0
T7	5930616	20668	0	0
T8	7228440	478	0	0
T9	302472	494	0	0
T10	767496	3547	0	0
T11	456912	1257	0	0
T12	2116920	8292	0	0
T13	2341632	10054	0	0
T14	1628766	1584	0	0
T15	0	2672	0	0
T16	0	368	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7975695	0	0
T1	1978230	12436	0	0
T2	3405456	14460	0	0
T3	4317768	4123	0	0
T7	5930616	20668	0	0
T8	7228440	478	0	0
T9	302472	494	0	0
T10	767496	3547	0	0
T11	456912	1257	0	0
T12	2116920	8292	0	0
T13	2341632	10054	0	0
T14	1628766	1584	0	0
T15	0	2672	0	0
T16	0	368	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39179770	0	0
T1	1978230	101089	0	0
T2	3405456	56592	0	0
T3	4317768	257933	0	0
T7	5930616	60921	0	0
T8	7228440	806	0	0
T9	302472	1002	0	0
T10	767496	7738	0	0
T11	456912	2872	0	0
T12	2116920	19951	0	0
T13	2341632	90765	0	0
T14	1628766	31304	0	0
T15	0	5963	0	0
T16	0	450	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38278	0	21600
T2	141894	13	0	1
T3	359814	2	0	2
T4	0	2	0	0
T5	0	88	0	0
T7	494218	0	0	2
T8	602370	0	0	2
T9	25206	0	0	2
T10	63958	2	0	2
T11	38076	0	0	2
T12	176410	1	0	2
T13	195136	0	0	2
T14	361948	0	0	2
T15	344753	0	0	1
T17	0	1	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	0	3	0	0
T21	0	2	0	0
T22	0	19	0	0
T23	0	3	0	0
T24	0	3	0	0
T25	0	74	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3165168	3164112	0	0
T2	3405456	3403104	0	0
T3	4317768	4317600	0	0
T7	5930616	5929584	0	0
T8	7228440	7227816	0	0
T9	302472	301680	0	0
T10	767496	767256	0	0
T11	456912	455568	0	0
T12	2116920	2114712	0	0
T13	2341632	2339712	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7975695	0	0
T1	1978230	12436	0	0
T2	3405456	14460	0	0
T3	4317768	4123	0	0
T7	5930616	20668	0	0
T8	7228440	478	0	0
T9	302472	494	0	0
T10	767496	3547	0	0
T11	456912	1257	0	0
T12	2116920	8292	0	0
T13	2341632	10054	0	0
T14	1628766	1584	0	0
T15	0	2672	0	0
T16	0	368	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	894121	0	0
GntImpliesValid_A	412031367	894121	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	894121	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	13901985	0	0
ReadyAndValidImplyGrant_A	412031367	894121	0	0
ReqAndReadyImplyGrant_A	412031367	894121	0	0
ReqImpliesValid_A	412031367	2772318	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	894121	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	894121	0	0
T1	131882	2287	0	0
T2	141894	1093	0	0
T3	179907	522	0	0
T7	247109	3226	0	0
T8	301185	55	0	0
T9	12603	51	0	0
T10	31979	398	0	0
T11	19038	118	0	0
T12	88205	925	0	0
T13	97568	1334	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	894121	0	0
T1	131882	2287	0	0
T2	141894	1093	0	0
T3	179907	522	0	0
T7	247109	3226	0	0
T8	301185	55	0	0
T9	12603	51	0	0
T10	31979	398	0	0
T11	19038	118	0	0
T12	88205	925	0	0
T13	97568	1334	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	894121	0	0
T1	131882	2287	0	0
T2	141894	1093	0	0
T3	179907	522	0	0
T7	247109	3226	0	0
T8	301185	55	0	0
T9	12603	51	0	0
T10	31979	398	0	0
T11	19038	118	0	0
T12	88205	925	0	0
T13	97568	1334	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	13901985	0	0
T1	131882	8461	0	0
T2	141894	7818	0	0
T3	179907	153912	0	0
T7	247109	17213	0	0
T8	301185	244	0	0
T9	12603	367	0	0
T10	31979	2839	0	0
T11	19038	835	0	0
T12	88205	6721	0	0
T13	97568	5737	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	894121	0	0
T1	131882	2287	0	0
T2	141894	1093	0	0
T3	179907	522	0	0
T7	247109	3226	0	0
T8	301185	55	0	0
T9	12603	51	0	0
T10	31979	398	0	0
T11	19038	118	0	0
T12	88205	925	0	0
T13	97568	1334	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	894121	0	0
T1	131882	2287	0	0
T2	141894	1093	0	0
T3	179907	522	0	0
T7	247109	3226	0	0
T8	301185	55	0	0
T9	12603	51	0	0
T10	31979	398	0	0
T11	19038	118	0	0
T12	88205	925	0	0
T13	97568	1334	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	2772318	0	0
T1	131882	15625	0	0
T2	141894	1586	0	0
T3	179907	16873	0	0
T7	247109	7966	0	0
T8	301185	91	0	0
T9	12603	77	0	0
T10	31979	753	0	0
T11	19038	151	0	0
T12	88205	1818	0	0
T13	97568	7706	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	894121	0	0
T1	131882	2287	0	0
T2	141894	1093	0	0
T3	179907	522	0	0
T7	247109	3226	0	0
T8	301185	55	0	0
T9	12603	51	0	0
T10	31979	398	0	0
T11	19038	118	0	0
T12	88205	925	0	0
T13	97568	1334	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	895667	0	0
GntImpliesValid_A	412031367	895667	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	895667	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	14014781	0	0
ReadyAndValidImplyGrant_A	412031367	895667	0	0
ReqAndReadyImplyGrant_A	412031367	895667	0	0
ReqImpliesValid_A	412031367	2720468	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	895667	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	895667	0	0
T1	131882	868	0	0
T2	141894	2621	0	0
T3	179907	458	0	0
T7	247109	4055	0	0
T8	301185	46	0	0
T9	12603	41	0	0
T10	31979	410	0	0
T11	19038	151	0	0
T12	88205	879	0	0
T13	97568	807	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	895667	0	0
T1	131882	868	0	0
T2	141894	2621	0	0
T3	179907	458	0	0
T7	247109	4055	0	0
T8	301185	46	0	0
T9	12603	41	0	0
T10	31979	410	0	0
T11	19038	151	0	0
T12	88205	879	0	0
T13	97568	807	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	895667	0	0
T1	131882	868	0	0
T2	141894	2621	0	0
T3	179907	458	0	0
T7	247109	4055	0	0
T8	301185	46	0	0
T9	12603	41	0	0
T10	31979	410	0	0
T11	19038	151	0	0
T12	88205	879	0	0
T13	97568	807	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	14014781	0	0
T1	131882	6551	0	0
T2	141894	13029	0	0
T3	179907	158974	0	0
T7	247109	21737	0	0
T8	301185	200	0	0
T9	12603	322	0	0
T10	31979	3008	0	0
T11	19038	1090	0	0
T12	88205	6569	0	0
T13	97568	5484	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	895667	0	0
T1	131882	868	0	0
T2	141894	2621	0	0
T3	179907	458	0	0
T7	247109	4055	0	0
T8	301185	46	0	0
T9	12603	41	0	0
T10	31979	410	0	0
T11	19038	151	0	0
T12	88205	879	0	0
T13	97568	807	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	895667	0	0
T1	131882	868	0	0
T2	141894	2621	0	0
T3	179907	458	0	0
T7	247109	4055	0	0
T8	301185	46	0	0
T9	12603	41	0	0
T10	31979	410	0	0
T11	19038	151	0	0
T12	88205	879	0	0
T13	97568	807	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	2720468	0	0
T1	131882	1324	0	0
T2	141894	13684	0	0
T3	179907	16143	0	0
T7	247109	18775	0	0
T8	301185	55	0	0
T9	12603	66	0	0
T10	31979	728	0	0
T11	19038	247	0	0
T12	88205	1563	0	0
T13	97568	1268	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	895667	0	0
T1	131882	868	0	0
T2	141894	2621	0	0
T3	179907	458	0	0
T7	247109	4055	0	0
T8	301185	46	0	0
T9	12603	41	0	0
T10	31979	410	0	0
T11	19038	151	0	0
T12	88205	879	0	0
T13	97568	807	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	229513	0	0
GntImpliesValid_A	412031367	229513	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	229513	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3472054	0	0
ReadyAndValidImplyGrant_A	412031367	229513	0	0
ReqAndReadyImplyGrant_A	412031367	229513	0	0
ReqImpliesValid_A	412031367	656822	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	229513	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229513	0	0
T1	131882	480	0	0
T2	141894	585	0	0
T3	179907	123	0	0
T7	247109	379	0	0
T8	301185	9	0	0
T9	12603	14	0	0
T10	31979	99	0	0
T11	19038	31	0	0
T12	88205	236	0	0
T13	97568	0	0	0
T14	0	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229513	0	0
T1	131882	480	0	0
T2	141894	585	0	0
T3	179907	123	0	0
T7	247109	379	0	0
T8	301185	9	0	0
T9	12603	14	0	0
T10	31979	99	0	0
T11	19038	31	0	0
T12	88205	236	0	0
T13	97568	0	0	0
T14	0	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229513	0	0
T1	131882	480	0	0
T2	141894	585	0	0
T3	179907	123	0	0
T7	247109	379	0	0
T8	301185	9	0	0
T9	12603	14	0	0
T10	31979	99	0	0
T11	19038	31	0	0
T12	88205	236	0	0
T13	97568	0	0	0
T14	0	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3472054	0	0
T1	131882	934	0	0
T2	141894	3186	0	0
T3	179907	39765	0	0
T7	247109	2969	0	0
T8	301185	45	0	0
T9	12603	70	0	0
T10	31979	676	0	0
T11	19038	224	0	0
T12	88205	1916	0	0
T13	97568	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229513	0	0
T1	131882	480	0	0
T2	141894	585	0	0
T3	179907	123	0	0
T7	247109	379	0	0
T8	301185	9	0	0
T9	12603	14	0	0
T10	31979	99	0	0
T11	19038	31	0	0
T12	88205	236	0	0
T13	97568	0	0	0
T14	0	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229513	0	0
T1	131882	480	0	0
T2	141894	585	0	0
T3	179907	123	0	0
T7	247109	379	0	0
T8	301185	9	0	0
T9	12603	14	0	0
T10	31979	99	0	0
T11	19038	31	0	0
T12	88205	236	0	0
T13	97568	0	0	0
T14	0	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	656822	0	0
T1	131882	4484	0	0
T2	141894	1279	0	0
T3	179907	2452	0	0
T7	247109	408	0	0
T8	301185	12	0	0
T9	12603	14	0	0
T10	31979	139	0	0
T11	19038	34	0	0
T12	88205	351	0	0
T13	97568	0	0	0
T14	0	3122	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229513	0	0
T1	131882	480	0	0
T2	141894	585	0	0
T3	179907	123	0	0
T7	247109	379	0	0
T8	301185	9	0	0
T9	12603	14	0	0
T10	31979	99	0	0
T11	19038	31	0	0
T12	88205	236	0	0
T13	97568	0	0	0
T14	0	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	224361	0	0
GntImpliesValid_A	412031367	224361	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	224361	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3406472	0	0
ReadyAndValidImplyGrant_A	412031367	224361	0	0
ReqAndReadyImplyGrant_A	412031367	224361	0	0
ReqImpliesValid_A	412031367	642509	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	224361	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224361	0	0
T1	131882	527	0	0
T2	141894	656	0	0
T3	179907	101	0	0
T7	247109	800	0	0
T8	301185	15	0	0
T9	12603	15	0	0
T10	31979	86	0	0
T11	19038	32	0	0
T12	88205	244	0	0
T13	97568	1028	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224361	0	0
T1	131882	527	0	0
T2	141894	656	0	0
T3	179907	101	0	0
T7	247109	800	0	0
T8	301185	15	0	0
T9	12603	15	0	0
T10	31979	86	0	0
T11	19038	32	0	0
T12	88205	244	0	0
T13	97568	1028	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224361	0	0
T1	131882	527	0	0
T2	141894	656	0	0
T3	179907	101	0	0
T7	247109	800	0	0
T8	301185	15	0	0
T9	12603	15	0	0
T10	31979	86	0	0
T11	19038	32	0	0
T12	88205	244	0	0
T13	97568	1028	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3406472	0	0
T1	131882	1143	0	0
T2	141894	4206	0	0
T3	179907	35872	0	0
T7	247109	4525	0	0
T8	301185	66	0	0
T9	12603	144	0	0
T10	31979	551	0	0
T11	19038	202	0	0
T12	88205	1697	0	0
T13	97568	1299	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224361	0	0
T1	131882	527	0	0
T2	141894	656	0	0
T3	179907	101	0	0
T7	247109	800	0	0
T8	301185	15	0	0
T9	12603	15	0	0
T10	31979	86	0	0
T11	19038	32	0	0
T12	88205	244	0	0
T13	97568	1028	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224361	0	0
T1	131882	527	0	0
T2	141894	656	0	0
T3	179907	101	0	0
T7	247109	800	0	0
T8	301185	15	0	0
T9	12603	15	0	0
T10	31979	86	0	0
T11	19038	32	0	0
T12	88205	244	0	0
T13	97568	1028	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	642509	0	0
T1	131882	4663	0	0
T2	141894	2459	0	0
T3	179907	1783	0	0
T7	247109	1540	0	0
T8	301185	18	0	0
T9	12603	30	0	0
T10	31979	109	0	0
T11	19038	32	0	0
T12	88205	367	0	0
T13	97568	10320	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224361	0	0
T1	131882	527	0	0
T2	141894	656	0	0
T3	179907	101	0	0
T7	247109	800	0	0
T8	301185	15	0	0
T9	12603	15	0	0
T10	31979	86	0	0
T11	19038	32	0	0
T12	88205	244	0	0
T13	97568	1028	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	228693	0	0
GntImpliesValid_A	412031367	228693	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	228693	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	6209191	0	0
ReadyAndValidImplyGrant_A	412031367	228693	0	0
ReqAndReadyImplyGrant_A	412031367	228693	0	0
ReqImpliesValid_A	412031367	1519555	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	228693	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	228693	0	0
T1	131882	884	0	0
T2	141894	1275	0	0
T3	179907	109	0	0
T7	247109	366	0	0
T8	301185	10	0	0
T9	12603	15	0	0
T10	31979	93	0	0
T11	19038	44	0	0
T12	88205	246	0	0
T13	97568	554	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	228693	0	0
T1	131882	884	0	0
T2	141894	1275	0	0
T3	179907	109	0	0
T7	247109	366	0	0
T8	301185	10	0	0
T9	12603	15	0	0
T10	31979	93	0	0
T11	19038	44	0	0
T12	88205	246	0	0
T13	97568	554	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	228693	0	0
T1	131882	884	0	0
T2	141894	1275	0	0
T3	179907	109	0	0
T7	247109	366	0	0
T8	301185	10	0	0
T9	12603	15	0	0
T10	31979	93	0	0
T11	19038	44	0	0
T12	88205	246	0	0
T13	97568	554	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	6209191	0	0
T1	131882	4960	0	0
T2	141894	6537	0	0
T3	179907	61026	0	0
T7	247109	3920	0	0
T8	301185	147	0	0
T9	12603	255	0	0
T10	31979	428	0	0
T11	19038	611	0	0
T12	88205	3876	0	0
T13	97568	206	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	228693	0	0
T1	131882	884	0	0
T2	141894	1275	0	0
T3	179907	109	0	0
T7	247109	366	0	0
T8	301185	10	0	0
T9	12603	15	0	0
T10	31979	93	0	0
T11	19038	44	0	0
T12	88205	246	0	0
T13	97568	554	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	228693	0	0
T1	131882	884	0	0
T2	141894	1275	0	0
T3	179907	109	0	0
T7	247109	366	0	0
T8	301185	10	0	0
T9	12603	15	0	0
T10	31979	93	0	0
T11	19038	44	0	0
T12	88205	246	0	0
T13	97568	554	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	1519555	0	0
T1	131882	22028	0	0
T2	141894	6368	0	0
T3	179907	4886	0	0
T7	247109	385	0	0
T8	301185	14	0	0
T9	12603	63	0	0
T10	31979	100	0	0
T11	19038	62	0	0
T12	88205	534	0	0
T13	97568	12228	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	228693	0	0
T1	131882	884	0	0
T2	141894	1275	0	0
T3	179907	109	0	0
T7	247109	366	0	0
T8	301185	10	0	0
T9	12603	15	0	0
T10	31979	93	0	0
T11	19038	44	0	0
T12	88205	246	0	0
T13	97568	554	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	229879	0	0
GntImpliesValid_A	412031367	229879	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	229879	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	6833985	0	0
ReadyAndValidImplyGrant_A	412031367	229879	0	0
ReqAndReadyImplyGrant_A	412031367	229879	0	0
ReqImpliesValid_A	412031367	1739422	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	229879	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229879	0	0
T1	131882	907	0	0
T2	141894	145	0	0
T3	179907	113	0	0
T7	247109	817	0	0
T8	301185	17	0	0
T9	12603	17	0	0
T10	31979	82	0	0
T11	19038	29	0	0
T12	88205	199	0	0
T13	97568	444	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229879	0	0
T1	131882	907	0	0
T2	141894	145	0	0
T3	179907	113	0	0
T7	247109	817	0	0
T8	301185	17	0	0
T9	12603	17	0	0
T10	31979	82	0	0
T11	19038	29	0	0
T12	88205	199	0	0
T13	97568	444	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229879	0	0
T1	131882	907	0	0
T2	141894	145	0	0
T3	179907	113	0	0
T7	247109	817	0	0
T8	301185	17	0	0
T9	12603	17	0	0
T10	31979	82	0	0
T11	19038	29	0	0
T12	88205	199	0	0
T13	97568	444	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	6833985	0	0
T1	131882	2881	0	0
T2	141894	2889	0	0
T3	179907	54764	0	0
T7	247109	6553	0	0
T8	301185	78	0	0
T9	12603	202	0	0
T10	31979	364	0	0
T11	19038	523	0	0
T12	88205	4587	0	0
T13	97568	1022	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229879	0	0
T1	131882	907	0	0
T2	141894	145	0	0
T3	179907	113	0	0
T7	247109	817	0	0
T8	301185	17	0	0
T9	12603	17	0	0
T10	31979	82	0	0
T11	19038	29	0	0
T12	88205	199	0	0
T13	97568	444	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229879	0	0
T1	131882	907	0	0
T2	141894	145	0	0
T3	179907	113	0	0
T7	247109	817	0	0
T8	301185	17	0	0
T9	12603	17	0	0
T10	31979	82	0	0
T11	19038	29	0	0
T12	88205	199	0	0
T13	97568	444	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	1739422	0	0
T1	131882	12191	0	0
T2	141894	145	0	0
T3	179907	9082	0	0
T7	247109	3049	0	0
T8	301185	19	0	0
T9	12603	20	0	0
T10	31979	89	0	0
T11	19038	78	0	0
T12	88205	463	0	0
T13	97568	5155	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	229879	0	0
T1	131882	907	0	0
T2	141894	145	0	0
T3	179907	113	0	0
T7	247109	817	0	0
T8	301185	17	0	0
T9	12603	17	0	0
T10	31979	82	0	0
T11	19038	29	0	0
T12	88205	199	0	0
T13	97568	444	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	221905	0	0
GntImpliesValid_A	412031367	221905	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	221905	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	5707591	0	0
ReadyAndValidImplyGrant_A	412031367	221905	0	0
ReqAndReadyImplyGrant_A	412031367	221905	0	0
ReqImpliesValid_A	412031367	1256469	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	221905	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	221905	0	0
T1	131882	1085	0	0
T2	141894	160	0	0
T3	179907	91	0	0
T7	247109	340	0	0
T8	301185	14	0	0
T9	12603	9	0	0
T10	31979	109	0	0
T11	19038	38	0	0
T12	88205	248	0	0
T13	97568	567	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	221905	0	0
T1	131882	1085	0	0
T2	141894	160	0	0
T3	179907	91	0	0
T7	247109	340	0	0
T8	301185	14	0	0
T9	12603	9	0	0
T10	31979	109	0	0
T11	19038	38	0	0
T12	88205	248	0	0
T13	97568	567	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	221905	0	0
T1	131882	1085	0	0
T2	141894	160	0	0
T3	179907	91	0	0
T7	247109	340	0	0
T8	301185	14	0	0
T9	12603	9	0	0
T10	31979	109	0	0
T11	19038	38	0	0
T12	88205	248	0	0
T13	97568	567	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	5707591	0	0
T1	131882	2319	0	0
T2	141894	2244	0	0
T3	179907	33613	0	0
T7	247109	3058	0	0
T8	301185	119	0	0
T9	12603	91	0	0
T10	31979	484	0	0
T11	19038	481	0	0
T12	88205	4307	0	0
T13	97568	161	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	221905	0	0
T1	131882	1085	0	0
T2	141894	160	0	0
T3	179907	91	0	0
T7	247109	340	0	0
T8	301185	14	0	0
T9	12603	9	0	0
T10	31979	109	0	0
T11	19038	38	0	0
T12	88205	248	0	0
T13	97568	567	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	221905	0	0
T1	131882	1085	0	0
T2	141894	160	0	0
T3	179907	91	0	0
T7	247109	340	0	0
T8	301185	14	0	0
T9	12603	9	0	0
T10	31979	109	0	0
T11	19038	38	0	0
T12	88205	248	0	0
T13	97568	567	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	1256469	0	0
T1	131882	9307	0	0
T2	141894	163	0	0
T3	179907	2354	0	0
T7	247109	344	0	0
T8	301185	14	0	0
T9	12603	9	0	0
T10	31979	116	0	0
T11	19038	74	0	0
T12	88205	689	0	0
T13	97568	11897	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	221905	0	0
T1	131882	1085	0	0
T2	141894	160	0	0
T3	179907	91	0	0
T7	247109	340	0	0
T8	301185	14	0	0
T9	12603	9	0	0
T10	31979	109	0	0
T11	19038	38	0	0
T12	88205	248	0	0
T13	97568	567	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	217722	0	0
GntImpliesValid_A	412031367	217722	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	217722	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	6052465	0	0
ReadyAndValidImplyGrant_A	412031367	217722	0	0
ReqAndReadyImplyGrant_A	412031367	217722	0	0
ReqImpliesValid_A	412031367	1451761	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	217722	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	217722	0	0
T1	131882	895	0	0
T2	141894	576	0	0
T3	179907	122	0	0
T7	247109	362	0	0
T8	301185	5	0	0
T9	12603	13	0	0
T10	31979	102	0	0
T11	19038	31	0	0
T12	88205	230	0	0
T13	97568	489	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	217722	0	0
T1	131882	895	0	0
T2	141894	576	0	0
T3	179907	122	0	0
T7	247109	362	0	0
T8	301185	5	0	0
T9	12603	13	0	0
T10	31979	102	0	0
T11	19038	31	0	0
T12	88205	230	0	0
T13	97568	489	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	217722	0	0
T1	131882	895	0	0
T2	141894	576	0	0
T3	179907	122	0	0
T7	247109	362	0	0
T8	301185	5	0	0
T9	12603	13	0	0
T10	31979	102	0	0
T11	19038	31	0	0
T12	88205	230	0	0
T13	97568	489	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	6052465	0	0
T1	131882	2017	0	0
T2	141894	5412	0	0
T3	179907	53912	0	0
T7	247109	3114	0	0
T8	301185	29	0	0
T9	12603	517	0	0
T10	31979	457	0	0
T11	19038	554	0	0
T12	88205	5840	0	0
T13	97568	502	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	217722	0	0
T1	131882	895	0	0
T2	141894	576	0	0
T3	179907	122	0	0
T7	247109	362	0	0
T8	301185	5	0	0
T9	12603	13	0	0
T10	31979	102	0	0
T11	19038	31	0	0
T12	88205	230	0	0
T13	97568	489	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	217722	0	0
T1	131882	895	0	0
T2	141894	576	0	0
T3	179907	122	0	0
T7	247109	362	0	0
T8	301185	5	0	0
T9	12603	13	0	0
T10	31979	102	0	0
T11	19038	31	0	0
T12	88205	230	0	0
T13	97568	489	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	1451761	0	0
T1	131882	6511	0	0
T2	141894	2811	0	0
T3	179907	3803	0	0
T7	247109	378	0	0
T8	301185	5	0	0
T9	12603	64	0	0
T10	31979	115	0	0
T11	19038	95	0	0
T12	88205	670	0	0
T13	97568	5448	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	217722	0	0
T1	131882	895	0	0
T2	141894	576	0	0
T3	179907	122	0	0
T7	247109	362	0	0
T8	301185	5	0	0
T9	12603	13	0	0
T10	31979	102	0	0
T11	19038	31	0	0
T12	88205	230	0	0
T13	97568	489	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	211212	0	0
GntImpliesValid_A	412031367	211212	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	211212	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3444118	0	0
ReadyAndValidImplyGrant_A	412031367	211212	0	0
ReqAndReadyImplyGrant_A	412031367	211212	0	0
ReqImpliesValid_A	412031367	628823	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	211212	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	211212	0	0
T1	131882	467	0	0
T2	141894	136	0	0
T3	179907	110	0	0
T7	247109	347	0	0
T8	301185	14	0	0
T9	12603	19	0	0
T10	31979	87	0	0
T11	19038	32	0	0
T12	88205	232	0	0
T13	97568	467	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	211212	0	0
T1	131882	467	0	0
T2	141894	136	0	0
T3	179907	110	0	0
T7	247109	347	0	0
T8	301185	14	0	0
T9	12603	19	0	0
T10	31979	87	0	0
T11	19038	32	0	0
T12	88205	232	0	0
T13	97568	467	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	211212	0	0
T1	131882	467	0	0
T2	141894	136	0	0
T3	179907	110	0	0
T7	247109	347	0	0
T8	301185	14	0	0
T9	12603	19	0	0
T10	31979	87	0	0
T11	19038	32	0	0
T12	88205	232	0	0
T13	97568	467	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3444118	0	0
T1	131882	1285	0	0
T2	141894	1116	0	0
T3	179907	37990	0	0
T7	247109	2703	0	0
T8	301185	47	0	0
T9	12603	121	0	0
T10	31979	670	0	0
T11	19038	250	0	0
T12	88205	1864	0	0
T13	97568	923	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	211212	0	0
T1	131882	467	0	0
T2	141894	136	0	0
T3	179907	110	0	0
T7	247109	347	0	0
T8	301185	14	0	0
T9	12603	19	0	0
T10	31979	87	0	0
T11	19038	32	0	0
T12	88205	232	0	0
T13	97568	467	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	211212	0	0
T1	131882	467	0	0
T2	141894	136	0	0
T3	179907	110	0	0
T7	247109	347	0	0
T8	301185	14	0	0
T9	12603	19	0	0
T10	31979	87	0	0
T11	19038	32	0	0
T12	88205	232	0	0
T13	97568	467	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	628823	0	0
T1	131882	3640	0	0
T2	141894	139	0	0
T3	179907	3028	0	0
T7	247109	369	0	0
T8	301185	14	0	0
T9	12603	19	0	0
T10	31979	103	0	0
T11	19038	32	0	0
T12	88205	330	0	0
T13	97568	2156	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	211212	0	0
T1	131882	467	0	0
T2	141894	136	0	0
T3	179907	110	0	0
T7	247109	347	0	0
T8	301185	14	0	0
T9	12603	19	0	0
T10	31979	87	0	0
T11	19038	32	0	0
T12	88205	232	0	0
T13	97568	467	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	223357	0	0
GntImpliesValid_A	412031367	223357	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	223357	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3395683	0	0
ReadyAndValidImplyGrant_A	412031367	223357	0	0
ReqAndReadyImplyGrant_A	412031367	223357	0	0
ReqImpliesValid_A	412031367	647912	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	223357	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	223357	0	0
T1	131882	515	0	0
T2	141894	175	0	0
T3	179907	101	0	0
T7	247109	375	0	0
T8	301185	17	0	0
T9	12603	15	0	0
T10	31979	103	0	0
T11	19038	29	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	0	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	223357	0	0
T1	131882	515	0	0
T2	141894	175	0	0
T3	179907	101	0	0
T7	247109	375	0	0
T8	301185	17	0	0
T9	12603	15	0	0
T10	31979	103	0	0
T11	19038	29	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	0	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	223357	0	0
T1	131882	515	0	0
T2	141894	175	0	0
T3	179907	101	0	0
T7	247109	375	0	0
T8	301185	17	0	0
T9	12603	15	0	0
T10	31979	103	0	0
T11	19038	29	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	0	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3395683	0	0
T1	131882	1362	0	0
T2	141894	1261	0	0
T3	179907	33447	0	0
T7	247109	2904	0	0
T8	301185	86	0	0
T9	12603	146	0	0
T10	31979	830	0	0
T11	19038	207	0	0
T12	88205	1702	0	0
T13	97568	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	223357	0	0
T1	131882	515	0	0
T2	141894	175	0	0
T3	179907	101	0	0
T7	247109	375	0	0
T8	301185	17	0	0
T9	12603	15	0	0
T10	31979	103	0	0
T11	19038	29	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	0	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	223357	0	0
T1	131882	515	0	0
T2	141894	175	0	0
T3	179907	101	0	0
T7	247109	375	0	0
T8	301185	17	0	0
T9	12603	15	0	0
T10	31979	103	0	0
T11	19038	29	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	0	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	647912	0	0
T1	131882	4359	0	0
T2	141894	182	0	0
T3	179907	1525	0	0
T7	247109	410	0	0
T8	301185	25	0	0
T9	12603	15	0	0
T10	31979	129	0	0
T11	19038	55	0	0
T12	88205	334	0	0
T13	97568	0	0	0
T14	0	1625	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	223357	0	0
T1	131882	515	0	0
T2	141894	175	0	0
T3	179907	101	0	0
T7	247109	375	0	0
T8	301185	17	0	0
T9	12603	15	0	0
T10	31979	103	0	0
T11	19038	29	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	0	133	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	226724	0	0
GntImpliesValid_A	412031367	226724	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	226724	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3482689	0	0
ReadyAndValidImplyGrant_A	412031367	226724	0	0
ReqAndReadyImplyGrant_A	412031367	226724	0	0
ReqImpliesValid_A	412031367	617512	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	226724	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226724	0	0
T2	141894	150	0	0
T3	179907	129	0	0
T7	247109	840	0	0
T8	301185	7	0	0
T9	12603	14	0	0
T10	31979	96	0	0
T11	19038	35	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	180974	159	0	0
T15	0	1063	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226724	0	0
T2	141894	150	0	0
T3	179907	129	0	0
T7	247109	840	0	0
T8	301185	7	0	0
T9	12603	14	0	0
T10	31979	96	0	0
T11	19038	35	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	180974	159	0	0
T15	0	1063	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226724	0	0
T2	141894	150	0	0
T3	179907	129	0	0
T7	247109	840	0	0
T8	301185	7	0	0
T9	12603	14	0	0
T10	31979	96	0	0
T11	19038	35	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	180974	159	0	0
T15	0	1063	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3482689	0	0
T1	131882	1	0	0
T2	141894	1139	0	0
T3	179907	47530	0	0
T7	247109	4777	0	0
T8	301185	24	0	0
T9	12603	104	0	0
T10	31979	696	0	0
T11	19038	298	0	0
T12	88205	1740	0	0
T13	97568	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226724	0	0
T2	141894	150	0	0
T3	179907	129	0	0
T7	247109	840	0	0
T8	301185	7	0	0
T9	12603	14	0	0
T10	31979	96	0	0
T11	19038	35	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	180974	159	0	0
T15	0	1063	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226724	0	0
T2	141894	150	0	0
T3	179907	129	0	0
T7	247109	840	0	0
T8	301185	7	0	0
T9	12603	14	0	0
T10	31979	96	0	0
T11	19038	35	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	180974	159	0	0
T15	0	1063	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	617512	0	0
T2	141894	153	0	0
T3	179907	7066	0	0
T7	247109	1804	0	0
T8	301185	7	0	0
T9	12603	14	0	0
T10	31979	144	0	0
T11	19038	36	0	0
T12	88205	308	0	0
T13	97568	0	0	0
T14	180974	1977	0	0
T15	0	2329	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226724	0	0
T2	141894	150	0	0
T3	179907	129	0	0
T7	247109	840	0	0
T8	301185	7	0	0
T9	12603	14	0	0
T10	31979	96	0	0
T11	19038	35	0	0
T12	88205	224	0	0
T13	97568	0	0	0
T14	180974	159	0	0
T15	0	1063	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	226750	0	0
GntImpliesValid_A	412031367	226750	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	226750	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3485295	0	0
ReadyAndValidImplyGrant_A	412031367	226750	0	0
ReqAndReadyImplyGrant_A	412031367	226750	0	0
ReqImpliesValid_A	412031367	644014	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	226750	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226750	0	0
T1	131882	572	0	0
T2	141894	187	0	0
T3	179907	97	0	0
T7	247109	349	0	0
T8	301185	19	0	0
T9	12603	26	0	0
T10	31979	102	0	0
T11	19038	37	0	0
T12	88205	241	0	0
T13	97568	486	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226750	0	0
T1	131882	572	0	0
T2	141894	187	0	0
T3	179907	97	0	0
T7	247109	349	0	0
T8	301185	19	0	0
T9	12603	26	0	0
T10	31979	102	0	0
T11	19038	37	0	0
T12	88205	241	0	0
T13	97568	486	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226750	0	0
T1	131882	572	0	0
T2	141894	187	0	0
T3	179907	97	0	0
T7	247109	349	0	0
T8	301185	19	0	0
T9	12603	26	0	0
T10	31979	102	0	0
T11	19038	37	0	0
T12	88205	241	0	0
T13	97568	486	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3485295	0	0
T1	131882	1506	0	0
T2	141894	1441	0	0
T3	179907	33977	0	0
T7	247109	2851	0	0
T8	301185	77	0	0
T9	12603	230	0	0
T10	31979	683	0	0
T11	19038	247	0	0
T12	88205	1742	0	0
T13	97568	825	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226750	0	0
T1	131882	572	0	0
T2	141894	187	0	0
T3	179907	97	0	0
T7	247109	349	0	0
T8	301185	19	0	0
T9	12603	26	0	0
T10	31979	102	0	0
T11	19038	37	0	0
T12	88205	241	0	0
T13	97568	486	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226750	0	0
T1	131882	572	0	0
T2	141894	187	0	0
T3	179907	97	0	0
T7	247109	349	0	0
T8	301185	19	0	0
T9	12603	26	0	0
T10	31979	102	0	0
T11	19038	37	0	0
T12	88205	241	0	0
T13	97568	486	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	644014	0	0
T1	131882	2215	0	0
T2	141894	199	0	0
T3	179907	1131	0	0
T7	247109	355	0	0
T8	301185	21	0	0
T9	12603	34	0	0
T10	31979	137	0	0
T11	19038	41	0	0
T12	88205	371	0	0
T13	97568	4709	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	226750	0	0
T1	131882	572	0	0
T2	141894	187	0	0
T3	179907	97	0	0
T7	247109	349	0	0
T8	301185	19	0	0
T9	12603	26	0	0
T10	31979	102	0	0
T11	19038	37	0	0
T12	88205	241	0	0
T13	97568	486	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	213637	0	0
GntImpliesValid_A	412031367	213637	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	213637	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3483063	0	0
ReadyAndValidImplyGrant_A	412031367	213637	0	0
ReqAndReadyImplyGrant_A	412031367	213637	0	0
ReqImpliesValid_A	412031367	619470	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	213637	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213637	0	0
T2	141894	595	0	0
T3	179907	104	0	0
T7	247109	363	0	0
T8	301185	12	0	0
T9	12603	12	0	0
T10	31979	114	0	0
T11	19038	32	0	0
T12	88205	209	0	0
T13	97568	0	0	0
T14	180974	106	0	0
T15	0	528	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213637	0	0
T2	141894	595	0	0
T3	179907	104	0	0
T7	247109	363	0	0
T8	301185	12	0	0
T9	12603	12	0	0
T10	31979	114	0	0
T11	19038	32	0	0
T12	88205	209	0	0
T13	97568	0	0	0
T14	180974	106	0	0
T15	0	528	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213637	0	0
T2	141894	595	0	0
T3	179907	104	0	0
T7	247109	363	0	0
T8	301185	12	0	0
T9	12603	12	0	0
T10	31979	114	0	0
T11	19038	32	0	0
T12	88205	209	0	0
T13	97568	0	0	0
T14	180974	106	0	0
T15	0	528	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3483063	0	0
T1	131882	1	0	0
T2	141894	3005	0	0
T3	179907	34363	0	0
T7	247109	2738	0	0
T8	301185	52	0	0
T9	12603	97	0	0
T10	31979	856	0	0
T11	19038	264	0	0
T12	88205	1632	0	0
T13	97568	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213637	0	0
T2	141894	595	0	0
T3	179907	104	0	0
T7	247109	363	0	0
T8	301185	12	0	0
T9	12603	12	0	0
T10	31979	114	0	0
T11	19038	32	0	0
T12	88205	209	0	0
T13	97568	0	0	0
T14	180974	106	0	0
T15	0	528	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213637	0	0
T2	141894	595	0	0
T3	179907	104	0	0
T7	247109	363	0	0
T8	301185	12	0	0
T9	12603	12	0	0
T10	31979	114	0	0
T11	19038	32	0	0
T12	88205	209	0	0
T13	97568	0	0	0
T14	180974	106	0	0
T15	0	528	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	619470	0	0
T2	141894	1512	0	0
T3	179907	1756	0	0
T7	247109	404	0	0
T8	301185	12	0	0
T9	12603	12	0	0
T10	31979	167	0	0
T11	19038	32	0	0
T12	88205	303	0	0
T13	97568	0	0	0
T14	180974	1346	0	0
T15	0	1239	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213637	0	0
T2	141894	595	0	0
T3	179907	104	0	0
T7	247109	363	0	0
T8	301185	12	0	0
T9	12603	12	0	0
T10	31979	114	0	0
T11	19038	32	0	0
T12	88205	209	0	0
T13	97568	0	0	0
T14	180974	106	0	0
T15	0	528	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	213438	0	0
GntImpliesValid_A	412031367	213438	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	213438	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3416389	0	0
ReadyAndValidImplyGrant_A	412031367	213438	0	0
ReqAndReadyImplyGrant_A	412031367	213438	0	0
ReqImpliesValid_A	412031367	613628	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	213438	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213438	0	0
T1	131882	537	0	0
T2	141894	158	0	0
T3	179907	105	0	0
T7	247109	375	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	107	0	0
T11	19038	43	0	0
T12	88205	250	0	0
T13	97568	473	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213438	0	0
T1	131882	537	0	0
T2	141894	158	0	0
T3	179907	105	0	0
T7	247109	375	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	107	0	0
T11	19038	43	0	0
T12	88205	250	0	0
T13	97568	473	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213438	0	0
T1	131882	537	0	0
T2	141894	158	0	0
T3	179907	105	0	0
T7	247109	375	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	107	0	0
T11	19038	43	0	0
T12	88205	250	0	0
T13	97568	473	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3416389	0	0
T1	131882	1510	0	0
T2	141894	1327	0	0
T3	179907	32404	0	0
T7	247109	2877	0	0
T8	301185	64	0	0
T9	12603	79	0	0
T10	31979	723	0	0
T11	19038	329	0	0
T12	88205	1789	0	0
T13	97568	795	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213438	0	0
T1	131882	537	0	0
T2	141894	158	0	0
T3	179907	105	0	0
T7	247109	375	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	107	0	0
T11	19038	43	0	0
T12	88205	250	0	0
T13	97568	473	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213438	0	0
T1	131882	537	0	0
T2	141894	158	0	0
T3	179907	105	0	0
T7	247109	375	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	107	0	0
T11	19038	43	0	0
T12	88205	250	0	0
T13	97568	473	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	613628	0	0
T1	131882	4812	0	0
T2	141894	165	0	0
T3	179907	3749	0	0
T7	247109	397	0	0
T8	301185	25	0	0
T9	12603	14	0	0
T10	31979	150	0	0
T11	19038	55	0	0
T12	88205	352	0	0
T13	97568	4520	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213438	0	0
T1	131882	537	0	0
T2	141894	158	0	0
T3	179907	105	0	0
T7	247109	375	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	107	0	0
T11	19038	43	0	0
T12	88205	250	0	0
T13	97568	473	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	224381	0	0
GntImpliesValid_A	412031367	224381	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	224381	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3500029	0	0
ReadyAndValidImplyGrant_A	412031367	224381	0	0
ReqAndReadyImplyGrant_A	412031367	224381	0	0
ReqImpliesValid_A	412031367	664181	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	224381	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224381	0	0
T2	141894	1050	0	0
T3	179907	100	0	0
T7	247109	354	0	0
T8	301185	7	0	0
T9	12603	11	0	0
T10	31979	103	0	0
T11	19038	33	0	0
T12	88205	214	0	0
T13	97568	0	0	0
T14	180974	136	0	0
T15	0	495	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224381	0	0
T2	141894	1050	0	0
T3	179907	100	0	0
T7	247109	354	0	0
T8	301185	7	0	0
T9	12603	11	0	0
T10	31979	103	0	0
T11	19038	33	0	0
T12	88205	214	0	0
T13	97568	0	0	0
T14	180974	136	0	0
T15	0	495	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224381	0	0
T2	141894	1050	0	0
T3	179907	100	0	0
T7	247109	354	0	0
T8	301185	7	0	0
T9	12603	11	0	0
T10	31979	103	0	0
T11	19038	33	0	0
T12	88205	214	0	0
T13	97568	0	0	0
T14	180974	136	0	0
T15	0	495	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3500029	0	0
T1	131882	1	0	0
T2	141894	6133	0	0
T3	179907	29524	0	0
T7	247109	2440	0	0
T8	301185	26	0	0
T9	12603	97	0	0
T10	31979	744	0	0
T11	19038	281	0	0
T12	88205	1723	0	0
T13	97568	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224381	0	0
T2	141894	1050	0	0
T3	179907	100	0	0
T7	247109	354	0	0
T8	301185	7	0	0
T9	12603	11	0	0
T10	31979	103	0	0
T11	19038	33	0	0
T12	88205	214	0	0
T13	97568	0	0	0
T14	180974	136	0	0
T15	0	495	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224381	0	0
T2	141894	1050	0	0
T3	179907	100	0	0
T7	247109	354	0	0
T8	301185	7	0	0
T9	12603	11	0	0
T10	31979	103	0	0
T11	19038	33	0	0
T12	88205	214	0	0
T13	97568	0	0	0
T14	180974	136	0	0
T15	0	495	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	664181	0	0
T2	141894	4745	0	0
T3	179907	2523	0	0
T7	247109	389	0	0
T8	301185	7	0	0
T9	12603	11	0	0
T10	31979	117	0	0
T11	19038	42	0	0
T12	88205	382	0	0
T13	97568	0	0	0
T14	180974	4362	0	0
T15	0	1114	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224381	0	0
T2	141894	1050	0	0
T3	179907	100	0	0
T7	247109	354	0	0
T8	301185	7	0	0
T9	12603	11	0	0
T10	31979	103	0	0
T11	19038	33	0	0
T12	88205	214	0	0
T13	97568	0	0	0
T14	180974	136	0	0
T15	0	495	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	210500	0	0
GntImpliesValid_A	412031367	210500	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	210500	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3450723	0	0
ReadyAndValidImplyGrant_A	412031367	210500	0	0
ReqAndReadyImplyGrant_A	412031367	210500	0	0
ReqImpliesValid_A	412031367	609811	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	210500	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	210500	0	0
T2	141894	155	0	0
T3	179907	103	0	0
T7	247109	369	0	0
T8	301185	11	0	0
T9	12603	17	0	0
T10	31979	111	0	0
T11	19038	29	0	0
T12	88205	230	0	0
T13	97568	0	0	0
T14	180974	128	0	0
T15	0	586	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	210500	0	0
T2	141894	155	0	0
T3	179907	103	0	0
T7	247109	369	0	0
T8	301185	11	0	0
T9	12603	17	0	0
T10	31979	111	0	0
T11	19038	29	0	0
T12	88205	230	0	0
T13	97568	0	0	0
T14	180974	128	0	0
T15	0	586	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	210500	0	0
T2	141894	155	0	0
T3	179907	103	0	0
T7	247109	369	0	0
T8	301185	11	0	0
T9	12603	17	0	0
T10	31979	111	0	0
T11	19038	29	0	0
T12	88205	230	0	0
T13	97568	0	0	0
T14	180974	128	0	0
T15	0	586	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3450723	0	0
T1	131882	1	0	0
T2	141894	1283	0	0
T3	179907	35850	0	0
T7	247109	2699	0	0
T8	301185	42	0	0
T9	12603	113	0	0
T10	31979	865	0	0
T11	19038	199	0	0
T12	88205	1735	0	0
T13	97568	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	210500	0	0
T2	141894	155	0	0
T3	179907	103	0	0
T7	247109	369	0	0
T8	301185	11	0	0
T9	12603	17	0	0
T10	31979	111	0	0
T11	19038	29	0	0
T12	88205	230	0	0
T13	97568	0	0	0
T14	180974	128	0	0
T15	0	586	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	210500	0	0
T2	141894	155	0	0
T3	179907	103	0	0
T7	247109	369	0	0
T8	301185	11	0	0
T9	12603	17	0	0
T10	31979	111	0	0
T11	19038	29	0	0
T12	88205	230	0	0
T13	97568	0	0	0
T14	180974	128	0	0
T15	0	586	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	609811	0	0
T2	141894	155	0	0
T3	179907	2475	0	0
T7	247109	392	0	0
T8	301185	11	0	0
T9	12603	19	0	0
T10	31979	165	0	0
T11	19038	44	0	0
T12	88205	376	0	0
T13	97568	0	0	0
T14	180974	2345	0	0
T15	0	1281	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	210500	0	0
T2	141894	155	0	0
T3	179907	103	0	0
T7	247109	369	0	0
T8	301185	11	0	0
T9	12603	17	0	0
T10	31979	111	0	0
T11	19038	29	0	0
T12	88205	230	0	0
T13	97568	0	0	0
T14	180974	128	0	0
T15	0	586	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	235222	0	0
GntImpliesValid_A	412031367	235222	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	235222	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3569995	0	0
ReadyAndValidImplyGrant_A	412031367	235222	0	0
ReqAndReadyImplyGrant_A	412031367	235222	0	0
ReqImpliesValid_A	412031367	653375	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	235222	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	235222	0	0
T2	141894	164	0	0
T3	179907	116	0	0
T7	247109	405	0	0
T8	301185	10	0	0
T9	12603	13	0	0
T10	31979	79	0	0
T11	19038	60	0	0
T12	88205	249	0	0
T13	97568	955	0	0
T14	180974	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	235222	0	0
T2	141894	164	0	0
T3	179907	116	0	0
T7	247109	405	0	0
T8	301185	10	0	0
T9	12603	13	0	0
T10	31979	79	0	0
T11	19038	60	0	0
T12	88205	249	0	0
T13	97568	955	0	0
T14	180974	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	235222	0	0
T2	141894	164	0	0
T3	179907	116	0	0
T7	247109	405	0	0
T8	301185	10	0	0
T9	12603	13	0	0
T10	31979	79	0	0
T11	19038	60	0	0
T12	88205	249	0	0
T13	97568	955	0	0
T14	180974	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3569995	0	0
T1	131882	1	0	0
T2	141894	1262	0	0
T3	179907	37349	0	0
T7	247109	3153	0	0
T8	301185	46	0	0
T9	12603	112	0	0
T10	31979	589	0	0
T11	19038	406	0	0
T12	88205	1972	0	0
T13	97568	1657	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	235222	0	0
T2	141894	164	0	0
T3	179907	116	0	0
T7	247109	405	0	0
T8	301185	10	0	0
T9	12603	13	0	0
T10	31979	79	0	0
T11	19038	60	0	0
T12	88205	249	0	0
T13	97568	955	0	0
T14	180974	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	235222	0	0
T2	141894	164	0	0
T3	179907	116	0	0
T7	247109	405	0	0
T8	301185	10	0	0
T9	12603	13	0	0
T10	31979	79	0	0
T11	19038	60	0	0
T12	88205	249	0	0
T13	97568	955	0	0
T14	180974	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	653375	0	0
T2	141894	164	0	0
T3	179907	2684	0	0
T7	247109	433	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	101	0	0
T11	19038	65	0	0
T12	88205	332	0	0
T13	97568	8830	0	0
T14	180974	2360	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	235222	0	0
T2	141894	164	0	0
T3	179907	116	0	0
T7	247109	405	0	0
T8	301185	10	0	0
T9	12603	13	0	0
T10	31979	79	0	0
T11	19038	60	0	0
T12	88205	249	0	0
T13	97568	955	0	0
T14	180974	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	218684	0	0
GntImpliesValid_A	412031367	218684	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	218684	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3390098	0	0
ReadyAndValidImplyGrant_A	412031367	218684	0	0
ReqAndReadyImplyGrant_A	412031367	218684	0	0
ReqImpliesValid_A	412031367	605503	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	218684	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	218684	0	0
T2	141894	159	0	0
T3	179907	99	0	0
T7	247109	344	0	0
T8	301185	19	0	0
T9	12603	15	0	0
T10	31979	98	0	0
T11	19038	27	0	0
T12	88205	231	0	0
T13	97568	437	0	0
T14	180974	137	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	218684	0	0
T2	141894	159	0	0
T3	179907	99	0	0
T7	247109	344	0	0
T8	301185	19	0	0
T9	12603	15	0	0
T10	31979	98	0	0
T11	19038	27	0	0
T12	88205	231	0	0
T13	97568	437	0	0
T14	180974	137	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	218684	0	0
T2	141894	159	0	0
T3	179907	99	0	0
T7	247109	344	0	0
T8	301185	19	0	0
T9	12603	15	0	0
T10	31979	98	0	0
T11	19038	27	0	0
T12	88205	231	0	0
T13	97568	437	0	0
T14	180974	137	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3390098	0	0
T1	131882	1	0	0
T2	141894	1230	0	0
T3	179907	28620	0	0
T7	247109	2703	0	0
T8	301185	65	0	0
T9	12603	129	0	0
T10	31979	745	0	0
T11	19038	182	0	0
T12	88205	1723	0	0
T13	97568	367	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	218684	0	0
T2	141894	159	0	0
T3	179907	99	0	0
T7	247109	344	0	0
T8	301185	19	0	0
T9	12603	15	0	0
T10	31979	98	0	0
T11	19038	27	0	0
T12	88205	231	0	0
T13	97568	437	0	0
T14	180974	137	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	218684	0	0
T2	141894	159	0	0
T3	179907	99	0	0
T7	247109	344	0	0
T8	301185	19	0	0
T9	12603	15	0	0
T10	31979	98	0	0
T11	19038	27	0	0
T12	88205	231	0	0
T13	97568	437	0	0
T14	180974	137	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	605503	0	0
T2	141894	181	0	0
T3	179907	1087	0	0
T7	247109	365	0	0
T8	301185	33	0	0
T9	12603	17	0	0
T10	31979	139	0	0
T11	19038	44	0	0
T12	88205	371	0	0
T13	97568	4788	0	0
T14	180974	1960	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	218684	0	0
T2	141894	159	0	0
T3	179907	99	0	0
T7	247109	344	0	0
T8	301185	19	0	0
T9	12603	15	0	0
T10	31979	98	0	0
T11	19038	27	0	0
T12	88205	231	0	0
T13	97568	437	0	0
T14	180974	137	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	224535	0	0
GntImpliesValid_A	412031367	224535	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	224535	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3506696	0	0
ReadyAndValidImplyGrant_A	412031367	224535	0	0
ReqAndReadyImplyGrant_A	412031367	224535	0	0
ReqImpliesValid_A	412031367	709356	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	224535	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224535	0	0
T2	141894	153	0	0
T3	179907	111	0	0
T7	247109	375	0	0
T8	301185	7	0	0
T9	12603	17	0	0
T10	31979	101	0	0
T11	19038	35	0	0
T12	88205	245	0	0
T13	97568	0	0	0
T14	180974	137	0	0
T16	0	171	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224535	0	0
T2	141894	153	0	0
T3	179907	111	0	0
T7	247109	375	0	0
T8	301185	7	0	0
T9	12603	17	0	0
T10	31979	101	0	0
T11	19038	35	0	0
T12	88205	245	0	0
T13	97568	0	0	0
T14	180974	137	0	0
T16	0	171	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224535	0	0
T2	141894	153	0	0
T3	179907	111	0	0
T7	247109	375	0	0
T8	301185	7	0	0
T9	12603	17	0	0
T10	31979	101	0	0
T11	19038	35	0	0
T12	88205	245	0	0
T13	97568	0	0	0
T14	180974	137	0	0
T16	0	171	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3506696	0	0
T1	131882	1	0	0
T2	141894	1276	0	0
T3	179907	32307	0	0
T7	247109	2627	0	0
T8	301185	32	0	0
T9	12603	111	0	0
T10	31979	702	0	0
T11	19038	260	0	0
T12	88205	1869	0	0
T13	97568	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224535	0	0
T2	141894	153	0	0
T3	179907	111	0	0
T7	247109	375	0	0
T8	301185	7	0	0
T9	12603	17	0	0
T10	31979	101	0	0
T11	19038	35	0	0
T12	88205	245	0	0
T13	97568	0	0	0
T14	180974	137	0	0
T16	0	171	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224535	0	0
T2	141894	153	0	0
T3	179907	111	0	0
T7	247109	375	0	0
T8	301185	7	0	0
T9	12603	17	0	0
T10	31979	101	0	0
T11	19038	35	0	0
T12	88205	245	0	0
T13	97568	0	0	0
T14	180974	137	0	0
T16	0	171	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	709356	0	0
T2	141894	155	0	0
T3	179907	1874	0	0
T7	247109	410	0	0
T8	301185	7	0	0
T9	12603	17	0	0
T10	31979	128	0	0
T11	19038	56	0	0
T12	88205	347	0	0
T13	97568	0	0	0
T14	180974	4536	0	0
T16	0	194	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	224535	0	0
T2	141894	153	0	0
T3	179907	111	0	0
T7	247109	375	0	0
T8	301185	7	0	0
T9	12603	17	0	0
T10	31979	101	0	0
T11	19038	35	0	0
T12	88205	245	0	0
T13	97568	0	0	0
T14	180974	137	0	0
T16	0	171	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	215225	0	0
GntImpliesValid_A	412031367	215225	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	215225	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3396386	0	0
ReadyAndValidImplyGrant_A	412031367	215225	0	0
ReqAndReadyImplyGrant_A	412031367	215225	0	0
ReqImpliesValid_A	412031367	599873	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	215225	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215225	0	0
T2	141894	155	0	0
T3	179907	120	0	0
T7	247109	390	0	0
T8	301185	12	0	0
T9	12603	8	0	0
T10	31979	87	0	0
T11	19038	29	0	0
T12	88205	248	0	0
T13	97568	443	0	0
T14	180974	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215225	0	0
T2	141894	155	0	0
T3	179907	120	0	0
T7	247109	390	0	0
T8	301185	12	0	0
T9	12603	8	0	0
T10	31979	87	0	0
T11	19038	29	0	0
T12	88205	248	0	0
T13	97568	443	0	0
T14	180974	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215225	0	0
T2	141894	155	0	0
T3	179907	120	0	0
T7	247109	390	0	0
T8	301185	12	0	0
T9	12603	8	0	0
T10	31979	87	0	0
T11	19038	29	0	0
T12	88205	248	0	0
T13	97568	443	0	0
T14	180974	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3396386	0	0
T1	131882	1	0	0
T2	141894	1158	0	0
T3	179907	39176	0	0
T7	247109	2922	0	0
T8	301185	57	0	0
T9	12603	82	0	0
T10	31979	695	0	0
T11	19038	207	0	0
T12	88205	1969	0	0
T13	97568	541	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215225	0	0
T2	141894	155	0	0
T3	179907	120	0	0
T7	247109	390	0	0
T8	301185	12	0	0
T9	12603	8	0	0
T10	31979	87	0	0
T11	19038	29	0	0
T12	88205	248	0	0
T13	97568	443	0	0
T14	180974	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215225	0	0
T2	141894	155	0	0
T3	179907	120	0	0
T7	247109	390	0	0
T8	301185	12	0	0
T9	12603	8	0	0
T10	31979	87	0	0
T11	19038	29	0	0
T12	88205	248	0	0
T13	97568	443	0	0
T14	180974	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	599873	0	0
T2	141894	161	0	0
T3	179907	1736	0	0
T7	247109	419	0	0
T8	301185	12	0	0
T9	12603	8	0	0
T10	31979	119	0	0
T11	19038	29	0	0
T12	88205	350	0	0
T13	97568	4651	0	0
T14	180974	2720	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215225	0	0
T2	141894	155	0	0
T3	179907	120	0	0
T7	247109	390	0	0
T8	301185	12	0	0
T9	12603	8	0	0
T10	31979	87	0	0
T11	19038	29	0	0
T12	88205	248	0	0
T13	97568	443	0	0
T14	180974	120	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	213842	0	0
GntImpliesValid_A	412031367	213842	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	213842	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3426812	0	0
ReadyAndValidImplyGrant_A	412031367	213842	0	0
ReqAndReadyImplyGrant_A	412031367	213842	0	0
ReqImpliesValid_A	412031367	626535	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	213842	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213842	0	0
T1	131882	570	0	0
T2	141894	160	0	0
T3	179907	89	0	0
T7	247109	929	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	105	0	0
T11	19038	40	0	0
T12	88205	225	0	0
T13	97568	0	0	0
T14	0	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213842	0	0
T1	131882	570	0	0
T2	141894	160	0	0
T3	179907	89	0	0
T7	247109	929	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	105	0	0
T11	19038	40	0	0
T12	88205	225	0	0
T13	97568	0	0	0
T14	0	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213842	0	0
T1	131882	570	0	0
T2	141894	160	0	0
T3	179907	89	0	0
T7	247109	929	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	105	0	0
T11	19038	40	0	0
T12	88205	225	0	0
T13	97568	0	0	0
T14	0	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3426812	0	0
T1	131882	1312	0	0
T2	141894	1308	0	0
T3	179907	30571	0	0
T7	247109	5757	0	0
T8	301185	67	0	0
T9	12603	72	0	0
T10	31979	691	0	0
T11	19038	305	0	0
T12	88205	1654	0	0
T13	97568	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213842	0	0
T1	131882	570	0	0
T2	141894	160	0	0
T3	179907	89	0	0
T7	247109	929	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	105	0	0
T11	19038	40	0	0
T12	88205	225	0	0
T13	97568	0	0	0
T14	0	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213842	0	0
T1	131882	570	0	0
T2	141894	160	0	0
T3	179907	89	0	0
T7	247109	929	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	105	0	0
T11	19038	40	0	0
T12	88205	225	0	0
T13	97568	0	0	0
T14	0	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	626535	0	0
T1	131882	2052	0	0
T2	141894	160	0	0
T3	179907	964	0	0
T7	247109	3455	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	157	0	0
T11	19038	48	0	0
T12	88205	336	0	0
T13	97568	0	0	0
T14	0	3052	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	213842	0	0
T1	131882	570	0	0
T2	141894	160	0	0
T3	179907	89	0	0
T7	247109	929	0	0
T8	301185	14	0	0
T9	12603	13	0	0
T10	31979	105	0	0
T11	19038	40	0	0
T12	88205	225	0	0
T13	97568	0	0	0
T14	0	132	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	215810	0	0
GntImpliesValid_A	412031367	215810	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	215810	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	3397663	0	0
ReadyAndValidImplyGrant_A	412031367	215810	0	0
ReqAndReadyImplyGrant_A	412031367	215810	0	0
ReqImpliesValid_A	412031367	611150	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	0	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	215810	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215810	0	0
T2	141894	153	0	0
T3	179907	106	0	0
T7	247109	873	0	0
T8	301185	13	0	0
T9	12603	20	0	0
T10	31979	107	0	0
T11	19038	27	0	0
T12	88205	251	0	0
T13	97568	0	0	0
T14	180974	143	0	0
T16	0	197	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215810	0	0
T2	141894	153	0	0
T3	179907	106	0	0
T7	247109	873	0	0
T8	301185	13	0	0
T9	12603	20	0	0
T10	31979	107	0	0
T11	19038	27	0	0
T12	88205	251	0	0
T13	97568	0	0	0
T14	180974	143	0	0
T16	0	197	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215810	0	0
T2	141894	153	0	0
T3	179907	106	0	0
T7	247109	873	0	0
T8	301185	13	0	0
T9	12603	20	0	0
T10	31979	107	0	0
T11	19038	27	0	0
T12	88205	251	0	0
T13	97568	0	0	0
T14	180974	143	0	0
T16	0	197	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	3397663	0	0
T1	131882	1	0	0
T2	141894	1191	0	0
T3	179907	37880	0	0
T7	247109	5625	0	0
T8	301185	76	0	0
T9	12603	166	0	0
T10	31979	828	0	0
T11	19038	208	0	0
T12	88205	1846	0	0
T13	97568	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215810	0	0
T2	141894	153	0	0
T3	179907	106	0	0
T7	247109	873	0	0
T8	301185	13	0	0
T9	12603	20	0	0
T10	31979	107	0	0
T11	19038	27	0	0
T12	88205	251	0	0
T13	97568	0	0	0
T14	180974	143	0	0
T16	0	197	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215810	0	0
T2	141894	153	0	0
T3	179907	106	0	0
T7	247109	873	0	0
T8	301185	13	0	0
T9	12603	20	0	0
T10	31979	107	0	0
T11	19038	27	0	0
T12	88205	251	0	0
T13	97568	0	0	0
T14	180974	143	0	0
T16	0	197	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	611150	0	0
T2	141894	162	0	0
T3	179907	2590	0	0
T7	247109	2711	0	0
T8	301185	16	0	0
T9	12603	20	0	0
T10	31979	152	0	0
T11	19038	42	0	0
T12	88205	353	0	0
T13	97568	0	0	0
T14	180974	1899	0	0
T16	0	256	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	215810	0	0
T2	141894	153	0	0
T3	179907	106	0	0
T7	247109	873	0	0
T8	301185	13	0	0
T9	12603	20	0	0
T10	31979	107	0	0
T11	19038	27	0	0
T12	88205	251	0	0
T13	97568	0	0	0
T14	180974	143	0	0
T16	0	197	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	881177	0	0
GntImpliesValid_A	412031367	881177	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	881177	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	13439822	0	0
ReadyAndValidImplyGrant_A	412031367	881177	0	0
ReqAndReadyImplyGrant_A	412031367	881177	0	0
ReqImpliesValid_A	412031367	2490534	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	15918	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	881177	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	881177	0	0
T1	131882	916	0	0
T2	141894	2697	0	0
T3	179907	482	0	0
T7	247109	1861	0	0
T8	301185	80	0	0
T9	12603	60	0	0
T10	31979	367	0	0
T11	19038	137	0	0
T12	88205	923	0	0
T13	97568	782	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	881177	0	0
T1	131882	916	0	0
T2	141894	2697	0	0
T3	179907	482	0	0
T7	247109	1861	0	0
T8	301185	80	0	0
T9	12603	60	0	0
T10	31979	367	0	0
T11	19038	137	0	0
T12	88205	923	0	0
T13	97568	782	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	881177	0	0
T1	131882	916	0	0
T2	141894	2697	0	0
T3	179907	482	0	0
T7	247109	1861	0	0
T8	301185	80	0	0
T9	12603	60	0	0
T10	31979	367	0	0
T11	19038	137	0	0
T12	88205	923	0	0
T13	97568	782	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	13439822	0	0
T1	131882	6048	0	0
T2	141894	13112	0	0
T3	179907	138682	0	0
T7	247109	11936	0	0
T8	301185	270	0	0
T9	12603	410	0	0
T10	31979	2186	0	0
T11	19038	867	0	0
T12	88205	5878	0	0
T13	97568	5265	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	881177	0	0
T1	131882	916	0	0
T2	141894	2697	0	0
T3	179907	482	0	0
T7	247109	1861	0	0
T8	301185	80	0	0
T9	12603	60	0	0
T10	31979	367	0	0
T11	19038	137	0	0
T12	88205	923	0	0
T13	97568	782	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	881177	0	0
T1	131882	916	0	0
T2	141894	2697	0	0
T3	179907	482	0	0
T7	247109	1861	0	0
T8	301185	80	0	0
T9	12603	60	0	0
T10	31979	367	0	0
T11	19038	137	0	0
T12	88205	923	0	0
T13	97568	782	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	2490534	0	0
T1	131882	1408	0	0
T2	141894	11379	0	0
T3	179907	13084	0	0
T7	247109	2380	0	0
T8	301185	116	0	0
T9	12603	67	0	0
T10	31979	685	0	0
T11	19038	201	0	0
T12	88205	1439	0	0
T13	97568	1130	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	15918	0	900
T2	141894	13	0	1
T3	179907	0	0	1
T4	0	2	0	0
T5	0	41	0	0
T7	247109	0	0	1
T8	301185	0	0	1
T9	12603	0	0	1
T10	31979	2	0	1
T11	19038	0	0	1
T12	88205	0	0	1
T13	97568	0	0	1
T14	180974	0	0	1
T19	0	1	0	0
T21	0	1	0	0
T22	0	8	0	0
T23	0	2	0	0
T24	0	3	0	0
T25	0	74	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	881177	0	0
T1	131882	916	0	0
T2	141894	2697	0	0
T3	179907	482	0	0
T7	247109	1861	0	0
T8	301185	80	0	0
T9	12603	60	0	0
T10	31979	367	0	0
T11	19038	137	0	0
T12	88205	923	0	0
T13	97568	782	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412031367	411888037	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	412031367	879340	0	0
GntImpliesValid_A	412031367	879340	0	0
GrantKnown_A	412031367	411888037	0	0
IdxKnown_A	412031367	411888037	0	0
IndexIsCorrect_A	412031367	879340	0	0
LockArbDecision_A	412031367	0	0	0
NoReadyValidNoGrant_A	412031367	347652569	0	0
ReadyAndValidImplyGrant_A	412031367	879340	0	0
ReqAndReadyImplyGrant_A	412031367	879340	0	0
ReqImpliesValid_A	412031367	15078769	0	0
ReqStaysHighUntilGranted0_M	412031367	0	0	0
RoundRobin_A	412031367	22360	0	900
ValidKnown_A	412031367	411888037	0	0
gen_data_port_assertion.DataFlow_A	412031367	879340	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	879340	0	0
T1	131882	926	0	0
T2	141894	1102	0	0
T3	179907	512	0	0
T7	247109	1774	0	0
T8	301185	51	0	0
T9	12603	46	0	0
T10	31979	401	0	0
T11	19038	158	0	0
T12	88205	889	0	0
T13	97568	788	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	879340	0	0
T1	131882	926	0	0
T2	141894	1102	0	0
T3	179907	512	0	0
T7	247109	1774	0	0
T8	301185	51	0	0
T9	12603	46	0	0
T10	31979	401	0	0
T11	19038	158	0	0
T12	88205	889	0	0
T13	97568	788	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	879340	0	0
T1	131882	926	0	0
T2	141894	1102	0	0
T3	179907	512	0	0
T7	247109	1774	0	0
T8	301185	51	0	0
T9	12603	46	0	0
T10	31979	401	0	0
T11	19038	158	0	0
T12	88205	889	0	0
T13	97568	788	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	347652569	0	0
T1	131882	111587	0	0
T2	141894	118092	0	0
T3	179907	156141	0	0
T7	247109	207250	0	0
T8	301185	250698	0	0
T9	12603	11085	0	0
T10	31979	25365	0	0
T11	19038	16138	0	0
T12	88205	73843	0	0
T13	97568	81311	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	879340	0	0
T1	131882	926	0	0
T2	141894	1102	0	0
T3	179907	512	0	0
T7	247109	1774	0	0
T8	301185	51	0	0
T9	12603	46	0	0
T10	31979	401	0	0
T11	19038	158	0	0
T12	88205	889	0	0
T13	97568	788	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	879340	0	0
T1	131882	926	0	0
T2	141894	1102	0	0
T3	179907	512	0	0
T7	247109	1774	0	0
T8	301185	51	0	0
T9	12603	46	0	0
T10	31979	401	0	0
T11	19038	158	0	0
T12	88205	889	0	0
T13	97568	788	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	15078769	0	0
T1	131882	6470	0	0
T2	141894	8485	0	0
T3	179907	153285	0	0
T7	247109	13383	0	0
T8	301185	244	0	0
T9	12603	366	0	0
T10	31979	2996	0	0
T11	19038	1277	0	0
T12	88205	7212	0	0
T13	97568	5959	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	22360	0	900
T3	179907	2	0	1
T5	0	47	0	0
T7	247109	0	0	1
T8	301185	0	0	1
T9	12603	0	0	1
T10	31979	0	0	1
T11	19038	0	0	1
T12	88205	1	0	1
T13	97568	0	0	1
T14	180974	0	0	1
T15	344753	0	0	1
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	3	0	0
T21	0	1	0	0
T22	0	11	0	0
T23	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	411888037	0	0
T1	131882	131838	0	0
T2	141894	141796	0	0
T3	179907	179900	0	0
T7	247109	247066	0	0
T8	301185	301159	0	0
T9	12603	12570	0	0
T10	31979	31969	0	0
T11	19038	18982	0	0
T12	88205	88113	0	0
T13	97568	97488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412031367	879340	0	0
T1	131882	926	0	0
T2	141894	1102	0	0
T3	179907	512	0	0
T7	247109	1774	0	0
T8	301185	51	0	0
T9	12603	46	0	0
T10	31979	401	0	0
T11	19038	158	0	0
T12	88205	889	0	0
T13	97568	788	0	0