Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1567042 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 249044 1 T1 1975 T2 431 T3 356


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 617818 1 T1 4820 T2 1174 T3 855
values[0x0] 583274 1 T1 4796 T2 1098 T3 798
values[0x1] 614994 1 T1 4920 T2 1108 T3 841


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1210394 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 605692 1 T1 4813 T2 1127 T3 860


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27888 1 T1 221 T2 52 T3 42
valid_sources[0x01] 29319 1 T1 239 T2 42 T3 31
valid_sources[0x02] 27877 1 T1 229 T2 48 T3 40
valid_sources[0x03] 28685 1 T1 267 T2 44 T3 38
valid_sources[0x04] 28208 1 T1 217 T2 47 T3 37
valid_sources[0x05] 28798 1 T1 261 T2 57 T3 44
valid_sources[0x06] 29895 1 T1 242 T2 56 T3 44
valid_sources[0x07] 28596 1 T1 218 T2 46 T3 40
valid_sources[0x08] 27546 1 T1 234 T2 47 T3 34
valid_sources[0x09] 28534 1 T1 250 T2 43 T3 37
valid_sources[0x0a] 27301 1 T1 222 T2 50 T3 35
valid_sources[0x0b] 28595 1 T1 223 T2 67 T3 44
valid_sources[0x0c] 29522 1 T1 217 T2 57 T3 38
valid_sources[0x0d] 28111 1 T1 220 T2 52 T3 43
valid_sources[0x0e] 28423 1 T1 246 T2 67 T3 40
valid_sources[0x0f] 29011 1 T1 206 T2 73 T3 41
valid_sources[0x10] 28003 1 T1 232 T2 47 T3 44
valid_sources[0x11] 27995 1 T1 227 T2 46 T3 43
valid_sources[0x12] 28233 1 T1 248 T2 68 T3 40
valid_sources[0x13] 29135 1 T1 238 T2 62 T3 39
valid_sources[0x14] 27881 1 T1 235 T2 50 T3 36
valid_sources[0x15] 27820 1 T1 208 T2 49 T3 32
valid_sources[0x16] 28486 1 T1 235 T2 53 T3 45
valid_sources[0x17] 28343 1 T1 236 T2 56 T3 33
valid_sources[0x18] 27451 1 T1 188 T2 60 T3 43
valid_sources[0x19] 28076 1 T1 203 T2 36 T3 42
valid_sources[0x1a] 28403 1 T1 223 T2 62 T3 43
valid_sources[0x1b] 28410 1 T1 216 T2 57 T3 34
valid_sources[0x1c] 27680 1 T1 221 T2 44 T3 36
valid_sources[0x1d] 27970 1 T1 226 T2 54 T3 30
valid_sources[0x1e] 29006 1 T1 240 T2 54 T3 38
valid_sources[0x1f] 29056 1 T1 233 T2 35 T3 44
valid_sources[0x20] 28907 1 T1 202 T2 76 T3 35


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26359 1 T1 195 T2 34 T3 51
values[0x0] all_enables biggest_size 196264 1 T1 1572 T2 360 T3 263
values[0x1] all_enables biggest_size 26421 1 T1 208 T2 37 T3 42


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1576362 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 255935 1 T1 2159 T2 504 T3 365


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 628489 1 T1 5123 T2 1220 T3 898
values[0x0] 577121 1 T1 4900 T2 1188 T3 786
values[0x1] 626687 1 T1 5133 T2 1167 T3 879


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1209566 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 622731 1 T1 5182 T2 1226 T3 869


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29161 1 T1 180 T2 51 T3 49
valid_sources[0x01] 28142 1 T1 263 T2 63 T3 33
valid_sources[0x02] 28166 1 T1 243 T2 47 T3 42
valid_sources[0x03] 29350 1 T1 269 T2 50 T3 38
valid_sources[0x04] 28943 1 T1 227 T2 64 T3 49
valid_sources[0x05] 28778 1 T1 251 T2 63 T3 36
valid_sources[0x06] 29029 1 T1 298 T2 70 T3 40
valid_sources[0x07] 28658 1 T1 216 T2 78 T3 37
valid_sources[0x08] 28875 1 T1 243 T2 54 T3 39
valid_sources[0x09] 27947 1 T1 271 T2 65 T3 40
valid_sources[0x0a] 28887 1 T1 240 T2 66 T3 44
valid_sources[0x0b] 28427 1 T1 235 T2 49 T3 44
valid_sources[0x0c] 28006 1 T1 232 T2 45 T3 30
valid_sources[0x0d] 28187 1 T1 223 T2 66 T3 38
valid_sources[0x0e] 28583 1 T1 230 T2 56 T3 27
valid_sources[0x0f] 28680 1 T1 235 T2 55 T3 44
valid_sources[0x10] 28460 1 T1 277 T2 78 T3 39
valid_sources[0x11] 28718 1 T1 244 T2 55 T3 34
valid_sources[0x12] 28357 1 T1 296 T2 58 T3 28
valid_sources[0x13] 28228 1 T1 245 T2 50 T3 40
valid_sources[0x14] 28212 1 T1 223 T2 53 T3 45
valid_sources[0x15] 28777 1 T1 252 T2 47 T3 28
valid_sources[0x16] 28729 1 T1 238 T2 58 T3 45
valid_sources[0x17] 29219 1 T1 219 T2 37 T3 53
valid_sources[0x18] 27993 1 T1 223 T2 54 T3 37
valid_sources[0x19] 28214 1 T1 229 T2 30 T3 47
valid_sources[0x1a] 28609 1 T1 212 T2 52 T3 48
valid_sources[0x1b] 28351 1 T1 258 T2 80 T3 43
valid_sources[0x1c] 27878 1 T1 261 T2 50 T3 49
valid_sources[0x1d] 28398 1 T1 245 T2 71 T3 42
valid_sources[0x1e] 27912 1 T1 239 T2 37 T3 38
valid_sources[0x1f] 28268 1 T1 242 T2 71 T3 51
valid_sources[0x20] 28804 1 T1 222 T2 49 T3 44


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26835 1 T1 214 T2 51 T3 48
values[0x0] all_enables biggest_size 202248 1 T1 1736 T2 402 T3 276
values[0x1] all_enables biggest_size 26852 1 T1 209 T2 51 T3 41


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1578619 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 250703 1 T1 2100 T2 466 T3 362


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 620801 1 T1 5094 T2 1165 T3 860
values[0x0] 586706 1 T1 4957 T2 1138 T3 922
values[0x1] 621815 1 T1 5151 T2 1214 T3 831


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1219604 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 609718 1 T1 5142 T2 1121 T3 845


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28995 1 T1 191 T2 60 T3 33
valid_sources[0x01] 27922 1 T1 250 T2 93 T3 50
valid_sources[0x02] 28879 1 T1 236 T2 54 T3 33
valid_sources[0x03] 28678 1 T1 281 T2 70 T3 36
valid_sources[0x04] 28992 1 T1 209 T2 49 T3 50
valid_sources[0x05] 28690 1 T1 252 T2 55 T3 34
valid_sources[0x06] 28391 1 T1 232 T2 54 T3 47
valid_sources[0x07] 28629 1 T1 232 T2 35 T3 41
valid_sources[0x08] 28968 1 T1 233 T2 71 T3 39
valid_sources[0x09] 28097 1 T1 291 T2 22 T3 42
valid_sources[0x0a] 28672 1 T1 231 T2 69 T3 51
valid_sources[0x0b] 28643 1 T1 245 T2 58 T3 41
valid_sources[0x0c] 28197 1 T1 252 T2 62 T3 39
valid_sources[0x0d] 28278 1 T1 216 T2 44 T3 45
valid_sources[0x0e] 29252 1 T1 244 T2 54 T3 47
valid_sources[0x0f] 28468 1 T1 237 T2 66 T3 37
valid_sources[0x10] 28167 1 T1 261 T2 77 T3 38
valid_sources[0x11] 28532 1 T1 222 T2 54 T3 38
valid_sources[0x12] 28241 1 T1 272 T2 37 T3 44
valid_sources[0x13] 29543 1 T1 230 T2 88 T3 35
valid_sources[0x14] 28471 1 T1 197 T2 34 T3 39
valid_sources[0x15] 28256 1 T1 238 T2 31 T3 43
valid_sources[0x16] 28372 1 T1 253 T2 29 T3 40
valid_sources[0x17] 28544 1 T1 223 T2 76 T3 39
valid_sources[0x18] 27376 1 T1 224 T2 45 T3 42
valid_sources[0x19] 28128 1 T1 259 T2 46 T3 39
valid_sources[0x1a] 28719 1 T1 233 T2 36 T3 48
valid_sources[0x1b] 28190 1 T1 286 T2 46 T3 42
valid_sources[0x1c] 29041 1 T1 258 T2 71 T3 33
valid_sources[0x1d] 29228 1 T1 243 T2 77 T3 44
valid_sources[0x1e] 27816 1 T1 202 T2 57 T3 43
valid_sources[0x1f] 28856 1 T1 241 T2 52 T3 39
valid_sources[0x20] 28060 1 T1 200 T2 62 T3 40


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26555 1 T1 209 T2 42 T3 41
values[0x0] all_enables biggest_size 197548 1 T1 1680 T2 381 T3 287
values[0x1] all_enables biggest_size 26600 1 T1 211 T2 43 T3 34

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%