Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1609285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255493

1

T1

14

T2

25

T3

123

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	632492	1			T1	67		T2	120		T3	343
values[0x0]	599550	1			T1	12		T2	22		T3	309
values[0x1]	632736	1			T1	66		T2	149		T3	327

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1243451	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

621327

1

T1

54

T2

100

T3

321

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29556	1			T1	1		T2	12		T3	11
valid_sources[0x01]	28662	1			T1	1		T2	3		T3	18
valid_sources[0x02]	28664	1			T1	6		T2	10		T3	18
valid_sources[0x03]	29117	1			T1	3		T2	5		T3	16
valid_sources[0x04]	29125	1			T2	5		T3	23		T7	4
valid_sources[0x05]	29395	1			T1	2		T2	6		T3	16
valid_sources[0x06]	30335	1			T1	1		T2	6		T3	16
valid_sources[0x07]	29140	1			T1	2		T2	2		T3	8
valid_sources[0x08]	27958	1			T1	2		T2	6		T3	11
valid_sources[0x09]	29085	1			T1	1		T3	18		T7	2
valid_sources[0x0a]	28946	1			T1	3		T2	6		T3	25
valid_sources[0x0b]	28844	1			T1	1		T2	1		T3	42
valid_sources[0x0c]	28990	1			T1	4		T2	6		T3	8
valid_sources[0x0d]	29474	1			T1	1		T2	7		T3	11
valid_sources[0x0e]	29803	1			T2	8		T3	21		T7	7
valid_sources[0x0f]	29057	1			T3	22		T7	10		T8	50
valid_sources[0x10]	27885	1			T1	1		T2	13		T3	16
valid_sources[0x11]	29014	1			T1	1		T2	2		T3	17
valid_sources[0x12]	28216	1			T2	6		T3	9		T7	7
valid_sources[0x13]	28679	1			T1	2		T2	2		T3	18
valid_sources[0x14]	30141	1			T1	4		T2	17		T3	17
valid_sources[0x15]	30238	1			T1	2		T2	2		T3	8
valid_sources[0x16]	28899	1			T1	5		T2	2		T3	10
valid_sources[0x17]	29680	1			T1	7		T2	5		T3	9
valid_sources[0x18]	30848	1			T1	4		T2	3		T3	15
valid_sources[0x19]	29480	1			T1	3		T3	14		T7	6
valid_sources[0x1a]	27715	1			T1	2		T2	4		T3	5
valid_sources[0x1b]	29180	1			T1	1		T3	5		T7	7
valid_sources[0x1c]	29791	1			T1	2		T2	7		T3	16
valid_sources[0x1d]	28906	1			T1	3		T2	7		T3	9
valid_sources[0x1e]	28633	1			T1	2		T2	12		T3	11
valid_sources[0x1f]	29456	1			T1	2		T2	4		T3	18
valid_sources[0x20]	28765	1			T1	1		T3	13		T7	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26670

1

T1

3

T2

2

T3

7

values[0x0]

all_enables

biggest_size

202067

1

T1

4

T2

12

T3

106

values[0x1]

all_enables

biggest_size

26756

1

T1

7

T2

11

T3

10

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1620163	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263824

1

T1

12

T2

35

T3

138

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	644337	1			T1	54		T2	136		T3	331
values[0x0]	595523	1			T1	6		T2	35		T3	304
values[0x1]	644127	1			T1	60		T2	173		T3	317

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1243056	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

640931

1

T1

50

T2

124

T3

358

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28796	1			T1	1		T2	12		T3	4
valid_sources[0x01]	29087	1			T2	5		T3	25		T7	12
valid_sources[0x02]	29382	1			T1	3		T2	9		T3	7
valid_sources[0x03]	29810	1			T1	2		T2	8		T3	20
valid_sources[0x04]	29790	1			T2	2		T3	27		T7	10
valid_sources[0x05]	28297	1			T2	3		T3	12		T7	2
valid_sources[0x06]	29910	1			T1	1		T2	3		T3	17
valid_sources[0x07]	29294	1			T1	2		T2	5		T3	7
valid_sources[0x08]	29824	1			T1	1		T2	10		T3	15
valid_sources[0x09]	29300	1			T2	4		T3	39		T7	8
valid_sources[0x0a]	29820	1			T1	1		T2	3		T3	28
valid_sources[0x0b]	29056	1			T1	1		T2	5		T3	20
valid_sources[0x0c]	29824	1			T1	2		T2	8		T3	13
valid_sources[0x0d]	28715	1			T1	2		T2	6		T3	2
valid_sources[0x0e]	29681	1			T1	3		T2	6		T7	15
valid_sources[0x0f]	29578	1			T1	4		T2	2		T3	13
valid_sources[0x10]	28601	1			T2	3		T3	10		T7	6
valid_sources[0x11]	29338	1			T2	5		T3	27		T7	5
valid_sources[0x12]	28288	1			T1	1		T2	10		T3	24
valid_sources[0x13]	29151	1			T1	5		T2	5		T3	41
valid_sources[0x14]	29847	1			T1	5		T2	3		T3	15
valid_sources[0x15]	29946	1			T1	1		T2	5		T3	21
valid_sources[0x16]	29705	1			T1	8		T2	8		T3	19
valid_sources[0x17]	29112	1			T1	2		T2	6		T3	2
valid_sources[0x18]	29560	1			T1	2		T2	5		T3	4
valid_sources[0x19]	29136	1			T1	1		T2	5		T3	1
valid_sources[0x1a]	29327	1			T1	1		T2	11		T3	25
valid_sources[0x1b]	30023	1			T1	3		T2	5		T3	16
valid_sources[0x1c]	29163	1			T1	1		T2	5		T3	3
valid_sources[0x1d]	29228	1			T1	2		T2	7		T3	25
valid_sources[0x1e]	29852	1			T2	6		T3	17		T7	8
valid_sources[0x1f]	28933	1			T1	1		T2	5		T3	7
valid_sources[0x20]	29165	1			T1	1		T2	1		T3	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27561

1

T1

5

T2

7

T3

17

values[0x0]

all_enables

biggest_size

208584

1

T1

3

T2

15

T3

114

values[0x1]

all_enables

biggest_size

27679

1

T1

4

T2

13

T3

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1614815	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

257019

1

T1

20

T2

31

T3

179

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	635054	1			T1	60		T2	121		T3	369
values[0x0]	602697	1			T1	7		T2	22		T3	370
values[0x1]	634083	1			T1	76		T2	156		T3	384

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1248296	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

623538

1

T1

75

T2

108

T3

397

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28674	1			T2	6		T3	22		T7	2
valid_sources[0x01]	29076	1			T1	1		T2	5		T3	4
valid_sources[0x02]	28921	1			T1	2		T2	4		T3	13
valid_sources[0x03]	29831	1			T1	3		T2	3		T3	19
valid_sources[0x04]	28925	1			T1	1		T2	5		T3	31
valid_sources[0x05]	29332	1			T1	9		T2	4		T3	7
valid_sources[0x06]	29947	1			T1	4		T2	7		T3	32
valid_sources[0x07]	29143	1			T3	10		T7	2		T8	49
valid_sources[0x08]	29281	1			T2	6		T3	4		T7	2
valid_sources[0x09]	29340	1			T2	3		T3	8		T7	4
valid_sources[0x0a]	29192	1			T1	1		T2	6		T3	16
valid_sources[0x0b]	30080	1			T1	1		T2	3		T3	9
valid_sources[0x0c]	29414	1			T1	5		T2	3		T3	12
valid_sources[0x0d]	28534	1			T1	3		T2	8		T3	8
valid_sources[0x0e]	30961	1			T2	8		T3	3		T7	9
valid_sources[0x0f]	28446	1			T1	3		T2	4		T3	15
valid_sources[0x10]	28556	1			T2	4		T3	5		T7	2
valid_sources[0x11]	29034	1			T2	3		T3	19		T7	4
valid_sources[0x12]	28384	1			T1	1		T2	4		T3	32
valid_sources[0x13]	29430	1			T1	5		T2	4		T3	26
valid_sources[0x14]	29231	1			T1	5		T2	2		T3	10
valid_sources[0x15]	30639	1			T1	5		T2	4		T3	6
valid_sources[0x16]	29310	1			T1	4		T2	9		T3	10
valid_sources[0x17]	29107	1			T1	2		T2	3		T3	19
valid_sources[0x18]	29146	1			T1	4		T2	7		T3	21
valid_sources[0x19]	29505	1			T2	7		T3	7		T7	5
valid_sources[0x1a]	29169	1			T1	3		T2	5		T3	9
valid_sources[0x1b]	29156	1			T1	2		T2	8		T3	33
valid_sources[0x1c]	29138	1			T1	2		T2	4		T3	46
valid_sources[0x1d]	29142	1			T1	3		T2	6		T3	13
valid_sources[0x1e]	28840	1			T1	1		T2	4		T3	11
valid_sources[0x1f]	28929	1			T1	1		T2	7		T3	56
valid_sources[0x20]	28720	1			T1	3		T2	4		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26812

1

T1

5

T2

11

T3

24

values[0x0]

all_enables

biggest_size

203490

1

T1

5

T2

9

T3

133

values[0x1]

all_enables

biggest_size

26717

1

T1

10

T2

11

T3

22