Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1658306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263053

1

T1

24

T2

30

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	650558	1			T1	68		T2	56		T3	60
values[0x0]	618778	1			T1	69		T2	70		T3	10
values[0x1]	652023	1			T1	61		T2	70		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1281694	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

639665

1

T1

63

T2

72

T3

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30024	1			T1	3		T2	3		T3	4
valid_sources[0x01]	29146	1			T1	3		T2	2		T7	27
valid_sources[0x02]	29960	1			T1	6		T2	4		T3	1
valid_sources[0x03]	30448	1			T1	11		T2	3		T3	3
valid_sources[0x04]	29209	1			T1	5		T2	1		T3	2
valid_sources[0x05]	30051	1			T2	4		T3	2		T7	26
valid_sources[0x06]	30031	1			T1	2		T2	5		T7	26
valid_sources[0x07]	30112	1			T1	5		T2	3		T3	2
valid_sources[0x08]	29501	1			T1	6		T2	2		T3	2
valid_sources[0x09]	30110	1			T1	2		T2	4		T3	1
valid_sources[0x0a]	29505	1			T1	5		T2	2		T3	1
valid_sources[0x0b]	30813	1			T1	6		T3	2		T7	17
valid_sources[0x0c]	29589	1			T3	4		T7	27		T9	7
valid_sources[0x0d]	29675	1			T1	2		T2	3		T3	4
valid_sources[0x0e]	30470	1			T1	6		T2	5		T3	4
valid_sources[0x0f]	29128	1			T1	2		T2	4		T7	26
valid_sources[0x10]	30128	1			T1	2		T2	1		T7	25
valid_sources[0x11]	30641	1			T1	9		T2	2		T3	1
valid_sources[0x12]	31108	1			T1	1		T2	3		T3	5
valid_sources[0x13]	30991	1			T1	2		T2	3		T3	4
valid_sources[0x14]	30663	1			T1	3		T2	2		T3	4
valid_sources[0x15]	30604	1			T1	3		T2	7		T3	4
valid_sources[0x16]	29764	1			T1	1		T2	2		T3	2
valid_sources[0x17]	31179	1			T1	1		T2	3		T3	2
valid_sources[0x18]	30321	1			T2	2		T3	1		T7	25
valid_sources[0x19]	30372	1			T1	2		T2	3		T3	4
valid_sources[0x1a]	30405	1			T1	1		T2	1		T3	4
valid_sources[0x1b]	29434	1			T2	3		T3	1		T7	24
valid_sources[0x1c]	28717	1			T2	6		T3	4		T7	23
valid_sources[0x1d]	30008	1			T1	3		T2	4		T3	3
valid_sources[0x1e]	28668	1			T1	12		T2	4		T3	1
valid_sources[0x1f]	29282	1			T1	2		T2	4		T3	2
valid_sources[0x20]	30513	1			T1	4		T2	4		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27555

1

T1

2

T3

6

T7

17

values[0x0]

all_enables

biggest_size

207965

1

T1

22

T2

27

T3

5

values[0x1]

all_enables

biggest_size

27533

1

T2

3

T3

4

T7

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1674001	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

272999

1

T1

15

T2

21

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	665313	1			T1	36		T2	42		T3	48
values[0x0]	616860	1			T1	32		T2	40		T3	3
values[0x1]	664827	1			T1	32		T2	46		T3	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1285266	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

661734

1

T1

33

T2

36

T3

44

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29548	1			T1	1		T3	3		T7	19
valid_sources[0x01]	29845	1			T1	2		T3	1		T7	24
valid_sources[0x02]	30819	1			T1	1		T2	1		T3	4
valid_sources[0x03]	30668	1			T1	3		T2	1		T3	3
valid_sources[0x04]	29029	1			T1	3		T3	1		T7	35
valid_sources[0x05]	30215	1			T1	1		T2	1		T3	3
valid_sources[0x06]	30751	1			T1	4		T2	2		T3	2
valid_sources[0x07]	31427	1			T1	1		T2	2		T3	3
valid_sources[0x08]	29511	1			T1	1		T2	4		T3	3
valid_sources[0x09]	30035	1			T1	1		T2	1		T7	18
valid_sources[0x0a]	30760	1			T1	1		T3	1		T7	25
valid_sources[0x0b]	30405	1			T1	1		T2	1		T3	3
valid_sources[0x0c]	30616	1			T1	2		T2	1		T7	27
valid_sources[0x0d]	30611	1			T1	1		T2	1		T3	2
valid_sources[0x0e]	30428	1			T1	1		T2	2		T7	29
valid_sources[0x0f]	30527	1			T1	2		T3	4		T7	20
valid_sources[0x10]	30796	1			T1	1		T2	1		T3	2
valid_sources[0x11]	30100	1			T1	2		T2	3		T3	1
valid_sources[0x12]	31512	1			T2	2		T3	1		T7	24
valid_sources[0x13]	30758	1			T1	1		T2	1		T3	1
valid_sources[0x14]	30412	1			T1	2		T2	3		T3	1
valid_sources[0x15]	30201	1			T2	3		T3	3		T7	20
valid_sources[0x16]	29581	1			T1	1		T2	5		T3	4
valid_sources[0x17]	30403	1			T1	3		T2	2		T3	2
valid_sources[0x18]	30975	1			T1	1		T2	2		T3	1
valid_sources[0x19]	30988	1			T1	2		T2	3		T3	1
valid_sources[0x1a]	31400	1			T1	1		T2	1		T3	2
valid_sources[0x1b]	30884	1			T1	4		T2	6		T3	3
valid_sources[0x1c]	29358	1			T1	2		T2	2		T7	20
valid_sources[0x1d]	30196	1			T1	4		T2	3		T3	1
valid_sources[0x1e]	29698	1			T1	3		T2	1		T7	31
valid_sources[0x1f]	30170	1			T1	1		T2	2		T3	3
valid_sources[0x20]	30657	1			T1	2		T2	3		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28548

1

T1

1

T3

2

T7

31

values[0x0]

all_enables

biggest_size

215936

1

T1

14

T2

17

T3

1

values[0x1]

all_enables

biggest_size

28515

1

T2

4

T3

5

T7

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1671786	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

265651

1

T1

25

T2

17

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	657344	1			T1	47		T2	47		T3	60
values[0x0]	623902	1			T1	55		T2	41		T3	6
values[0x1]	656191	1			T1	43		T2	44		T3	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1292496	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

644941

1

T1

45

T2

41

T3

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30340	1			T1	7		T2	3		T3	2
valid_sources[0x01]	30113	1			T1	1		T3	1		T7	21
valid_sources[0x02]	30687	1			T1	3		T2	2		T3	1
valid_sources[0x03]	30226	1			T1	1		T2	2		T7	19
valid_sources[0x04]	29755	1			T2	1		T3	3		T7	31
valid_sources[0x05]	30454	1			T1	2		T2	3		T3	1
valid_sources[0x06]	30899	1			T1	1		T2	1		T3	3
valid_sources[0x07]	30842	1			T1	2		T3	1		T7	23
valid_sources[0x08]	30094	1			T2	2		T3	3		T7	17
valid_sources[0x09]	29835	1			T1	2		T3	3		T7	26
valid_sources[0x0a]	30123	1			T2	1		T3	1		T7	20
valid_sources[0x0b]	30488	1			T2	5		T3	1		T7	17
valid_sources[0x0c]	30138	1			T1	2		T2	1		T7	18
valid_sources[0x0d]	29757	1			T1	6		T2	3		T3	2
valid_sources[0x0e]	30316	1			T1	6		T2	3		T3	2
valid_sources[0x0f]	31032	1			T2	5		T3	1		T7	22
valid_sources[0x10]	30405	1			T1	3		T2	1		T3	2
valid_sources[0x11]	30884	1			T1	3		T2	2		T7	18
valid_sources[0x12]	30892	1			T1	2		T2	4		T3	3
valid_sources[0x13]	30712	1			T2	2		T7	24		T8	21
valid_sources[0x14]	30667	1			T1	5		T2	1		T3	5
valid_sources[0x15]	30449	1			T1	2		T2	2		T7	19
valid_sources[0x16]	30583	1			T1	2		T2	1		T3	3
valid_sources[0x17]	29648	1			T1	4		T2	2		T3	1
valid_sources[0x18]	30321	1			T1	1		T2	1		T3	2
valid_sources[0x19]	30273	1			T1	2		T2	5		T3	1
valid_sources[0x1a]	30379	1			T2	3		T3	4		T7	16
valid_sources[0x1b]	31078	1			T2	5		T3	7		T7	30
valid_sources[0x1c]	29280	1			T2	1		T3	7		T7	21
valid_sources[0x1d]	30219	1			T1	2		T2	5		T3	2
valid_sources[0x1e]	29465	1			T1	1		T2	3		T3	3
valid_sources[0x1f]	30491	1			T1	2		T2	2		T7	19
valid_sources[0x20]	30270	1			T1	2		T2	2		T7	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27577

1

T2

4

T3

3

T7

19

values[0x0]

all_enables

biggest_size

210513

1

T1

21

T2

13

T3

2

values[0x1]

all_enables

biggest_size

27561

1

T1

4

T3

3

T7

12