Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7976718	0	0
GntImpliesValid_A	2147483647	7976718	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7976718	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	446258131	0	0
ReadyAndValidImplyGrant_A	2147483647	7976718	0	0
ReqAndReadyImplyGrant_A	2147483647	7976718	0	0
ReqImpliesValid_A	2147483647	35262610	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	41914	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7976718	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	53280	51888	0	0
T2	49392	48264	0	0
T3	1782144	1781232	0	0
T4	56544	54408	0	0
T7	4330920	4330872	0	0
T8	3093984	3093840	0	0
T9	13800840	13800096	0	0
T10	1549248	1548240	0	0
T11	12393528	12391848	0	0
T12	1842408	1841592	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976718	0	0
T1	53280	443	0	0
T2	49392	456	0	0
T3	1782144	7759	0	0
T4	56544	444	0	0
T7	4330920	4399	0	0
T8	3093984	3234	0	0
T9	13800840	1329	0	0
T10	1549248	36231	0	0
T11	12393528	490	0	0
T12	1842408	8224	0	0
T13	0	2109	0	0
T14	0	1361	0	0
T15	0	148	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976718	0	0
T1	53280	443	0	0
T2	49392	456	0	0
T3	1782144	7759	0	0
T4	56544	444	0	0
T7	4330920	4399	0	0
T8	3093984	3234	0	0
T9	13800840	1329	0	0
T10	1549248	36231	0	0
T11	12393528	490	0	0
T12	1842408	8224	0	0
T13	0	2109	0	0
T14	0	1361	0	0
T15	0	148	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	53280	51888	0	0
T2	49392	48264	0	0
T3	1782144	1781232	0	0
T4	56544	54408	0	0
T7	4330920	4330872	0	0
T8	3093984	3093840	0	0
T9	13800840	13800096	0	0
T10	1549248	1548240	0	0
T11	12393528	12391848	0	0
T12	1842408	1841592	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	53280	51888	0	0
T2	49392	48264	0	0
T3	1782144	1781232	0	0
T4	56544	54408	0	0
T7	4330920	4330872	0	0
T8	3093984	3093840	0	0
T9	13800840	13800096	0	0
T10	1549248	1548240	0	0
T11	12393528	12391848	0	0
T12	1842408	1841592	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976718	0	0
T1	53280	443	0	0
T2	49392	456	0	0
T3	1782144	7759	0	0
T4	56544	444	0	0
T7	4330920	4399	0	0
T8	3093984	3234	0	0
T9	13800840	1329	0	0
T10	1549248	36231	0	0
T11	12393528	490	0	0
T12	1842408	8224	0	0
T13	0	2109	0	0
T14	0	1361	0	0
T15	0	148	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	446258131	0	0
T1	53280	631	0	0
T2	49392	592	0	0
T3	1782144	111933	0	0
T4	56544	633	0	0
T7	4330920	163246	0	0
T8	3093984	1113658	0	0
T9	13800840	483000	0	0
T10	1549248	31208	0	0
T11	12393528	668173	0	0
T12	1842408	85980	0	0
T13	0	2164	0	0
T14	0	13274	0	0
T15	0	366	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976718	0	0
T1	53280	443	0	0
T2	49392	456	0	0
T3	1782144	7759	0	0
T4	56544	444	0	0
T7	4330920	4399	0	0
T8	3093984	3234	0	0
T9	13800840	1329	0	0
T10	1549248	36231	0	0
T11	12393528	490	0	0
T12	1842408	8224	0	0
T13	0	2109	0	0
T14	0	1361	0	0
T15	0	148	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976718	0	0
T1	53280	443	0	0
T2	49392	456	0	0
T3	1782144	7759	0	0
T4	56544	444	0	0
T7	4330920	4399	0	0
T8	3093984	3234	0	0
T9	13800840	1329	0	0
T10	1549248	36231	0	0
T11	12393528	490	0	0
T12	1842408	8224	0	0
T13	0	2109	0	0
T14	0	1361	0	0
T15	0	148	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35262610	0	0
T1	53280	504	0	0
T2	49392	521	0	0
T3	1782144	17819	0	0
T4	56544	501	0	0
T7	4330920	10244	0	0
T8	3093984	214639	0	0
T9	13800840	3077	0	0
T10	1549248	48970	0	0
T11	12393528	30078	0	0
T12	1842408	64160	0	0
T13	0	2404	0	0
T14	0	1667	0	0
T15	0	193	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41914	0	21600
T3	74256	1	0	1
T4	4712	0	0	2
T7	360910	11	0	2
T8	257832	0	0	2
T9	1150070	0	0	2
T10	129104	83	0	2
T11	1032794	0	0	2
T12	153534	0	0	2
T13	17948	11	0	2
T14	128142	0	0	2
T15	1765	3	0	1
T16	0	10	0	0
T17	0	29	0	0
T18	0	32	0	0
T19	0	2	0	0
T20	0	14	0	0
T21	0	560	0	0
T22	0	20	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	53280	51888	0	0
T2	49392	48264	0	0
T3	1782144	1781232	0	0
T4	56544	54408	0	0
T7	4330920	4330872	0	0
T8	3093984	3093840	0	0
T9	13800840	13800096	0	0
T10	1549248	1548240	0	0
T11	12393528	12391848	0	0
T12	1842408	1841592	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976718	0	0
T1	53280	443	0	0
T2	49392	456	0	0
T3	1782144	7759	0	0
T4	56544	444	0	0
T7	4330920	4399	0	0
T8	3093984	3234	0	0
T9	13800840	1329	0	0
T10	1549248	36231	0	0
T11	12393528	490	0	0
T12	1842408	8224	0	0
T13	0	2109	0	0
T14	0	1361	0	0
T15	0	148	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	888033	0	0
GntImpliesValid_A	407386072	888033	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	888033	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	12237289	0	0
ReadyAndValidImplyGrant_A	407386072	888033	0	0
ReqAndReadyImplyGrant_A	407386072	888033	0	0
ReqImpliesValid_A	407386072	2454469	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	888033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	888033	0	0
T1	2220	38	0	0
T2	2058	57	0	0
T3	74256	843	0	0
T4	2356	44	0	0
T7	180455	306	0	0
T8	128916	348	0	0
T9	575035	84	0	0
T10	64552	3581	0	0
T11	516397	55	0	0
T12	76767	1374	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	888033	0	0
T1	2220	38	0	0
T2	2058	57	0	0
T3	74256	843	0	0
T4	2356	44	0	0
T7	180455	306	0	0
T8	128916	348	0	0
T9	575035	84	0	0
T10	64552	3581	0	0
T11	516397	55	0	0
T12	76767	1374	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	888033	0	0
T1	2220	38	0	0
T2	2058	57	0	0
T3	74256	843	0	0
T4	2356	44	0	0
T7	180455	306	0	0
T8	128916	348	0	0
T9	575035	84	0	0
T10	64552	3581	0	0
T11	516397	55	0	0
T12	76767	1374	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	12237289	0	0
T1	2220	37	0	0
T2	2058	40	0	0
T3	74256	5751	0	0
T4	2356	34	0	0
T7	180455	1271	0	0
T8	128916	111623	0	0
T9	575035	343	0	0
T10	64552	2853	0	0
T11	516397	17022	0	0
T12	76767	4572	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	888033	0	0
T1	2220	38	0	0
T2	2058	57	0	0
T3	74256	843	0	0
T4	2356	44	0	0
T7	180455	306	0	0
T8	128916	348	0	0
T9	575035	84	0	0
T10	64552	3581	0	0
T11	516397	55	0	0
T12	76767	1374	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	888033	0	0
T1	2220	38	0	0
T2	2058	57	0	0
T3	74256	843	0	0
T4	2356	44	0	0
T7	180455	306	0	0
T8	128916	348	0	0
T9	575035	84	0	0
T10	64552	3581	0	0
T11	516397	55	0	0
T12	76767	1374	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	2454469	0	0
T1	2220	40	0	0
T2	2058	75	0	0
T3	74256	1411	0	0
T4	2356	55	0	0
T7	180455	447	0	0
T8	128916	10001	0	0
T9	575035	111	0	0
T10	64552	4311	0	0
T11	516397	2137	0	0
T12	76767	9830	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	888033	0	0
T1	2220	38	0	0
T2	2058	57	0	0
T3	74256	843	0	0
T4	2356	44	0	0
T7	180455	306	0	0
T8	128916	348	0	0
T9	575035	84	0	0
T10	64552	3581	0	0
T11	516397	55	0	0
T12	76767	1374	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	886863	0	0
GntImpliesValid_A	407386072	886863	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	886863	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	12497295	0	0
ReadyAndValidImplyGrant_A	407386072	886863	0	0
ReqAndReadyImplyGrant_A	407386072	886863	0	0
ReqImpliesValid_A	407386072	2535882	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	886863	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	886863	0	0
T1	2220	34	0	0
T2	2058	44	0	0
T3	74256	764	0	0
T4	2356	45	0	0
T7	180455	297	0	0
T8	128916	370	0	0
T9	575035	89	0	0
T10	64552	5759	0	0
T11	516397	57	0	0
T12	76767	1241	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	886863	0	0
T1	2220	34	0	0
T2	2058	44	0	0
T3	74256	764	0	0
T4	2356	45	0	0
T7	180455	297	0	0
T8	128916	370	0	0
T9	575035	89	0	0
T10	64552	5759	0	0
T11	516397	57	0	0
T12	76767	1241	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	886863	0	0
T1	2220	34	0	0
T2	2058	44	0	0
T3	74256	764	0	0
T4	2356	45	0	0
T7	180455	297	0	0
T8	128916	370	0	0
T9	575035	89	0	0
T10	64552	5759	0	0
T11	516397	57	0	0
T12	76767	1241	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	12497295	0	0
T1	2220	28	0	0
T2	2058	35	0	0
T3	74256	5789	0	0
T4	2356	34	0	0
T7	180455	1231	0	0
T8	128916	113458	0	0
T9	575035	369	0	0
T10	64552	3237	0	0
T11	516397	22041	0	0
T12	76767	5320	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	886863	0	0
T1	2220	34	0	0
T2	2058	44	0	0
T3	74256	764	0	0
T4	2356	45	0	0
T7	180455	297	0	0
T8	128916	370	0	0
T9	575035	89	0	0
T10	64552	5759	0	0
T11	516397	57	0	0
T12	76767	1241	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	886863	0	0
T1	2220	34	0	0
T2	2058	44	0	0
T3	74256	764	0	0
T4	2356	45	0	0
T7	180455	297	0	0
T8	128916	370	0	0
T9	575035	89	0	0
T10	64552	5759	0	0
T11	516397	57	0	0
T12	76767	1241	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	2535882	0	0
T1	2220	41	0	0
T2	2058	54	0	0
T3	74256	1450	0	0
T4	2356	57	0	0
T7	180455	433	0	0
T8	128916	8585	0	0
T9	575035	137	0	0
T10	64552	8283	0	0
T11	516397	725	0	0
T12	76767	3675	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	886863	0	0
T1	2220	34	0	0
T2	2058	44	0	0
T3	74256	764	0	0
T4	2356	45	0	0
T7	180455	297	0	0
T8	128916	370	0	0
T9	575035	89	0	0
T10	64552	5759	0	0
T11	516397	57	0	0
T12	76767	1241	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	221520	0	0
GntImpliesValid_A	407386072	221520	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	221520	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3054245	0	0
ReadyAndValidImplyGrant_A	407386072	221520	0	0
ReqAndReadyImplyGrant_A	407386072	221520	0	0
ReqImpliesValid_A	407386072	594996	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	221520	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221520	0	0
T1	2220	15	0	0
T2	2058	15	0	0
T3	74256	240	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	94	0	0
T9	575035	0	0	0
T10	64552	1620	0	0
T11	516397	8	0	0
T12	76767	0	0	0
T13	0	98	0	0
T14	0	74	0	0
T15	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221520	0	0
T1	2220	15	0	0
T2	2058	15	0	0
T3	74256	240	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	94	0	0
T9	575035	0	0	0
T10	64552	1620	0	0
T11	516397	8	0	0
T12	76767	0	0	0
T13	0	98	0	0
T14	0	74	0	0
T15	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221520	0	0
T1	2220	15	0	0
T2	2058	15	0	0
T3	74256	240	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	94	0	0
T9	575035	0	0	0
T10	64552	1620	0	0
T11	516397	8	0	0
T12	76767	0	0	0
T13	0	98	0	0
T14	0	74	0	0
T15	0	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3054245	0	0
T1	2220	16	0	0
T2	2058	14	0	0
T3	74256	1727	0	0
T4	2356	13	0	0
T7	180455	1	0	0
T8	128916	33051	0	0
T9	575035	1	0	0
T10	64552	750	0	0
T11	516397	1622	0	0
T12	76767	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221520	0	0
T1	2220	15	0	0
T2	2058	15	0	0
T3	74256	240	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	94	0	0
T9	575035	0	0	0
T10	64552	1620	0	0
T11	516397	8	0	0
T12	76767	0	0	0
T13	0	98	0	0
T14	0	74	0	0
T15	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221520	0	0
T1	2220	15	0	0
T2	2058	15	0	0
T3	74256	240	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	94	0	0
T9	575035	0	0	0
T10	64552	1620	0	0
T11	516397	8	0	0
T12	76767	0	0	0
T13	0	98	0	0
T14	0	74	0	0
T15	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	594996	0	0
T1	2220	15	0	0
T2	2058	17	0	0
T3	74256	401	0	0
T4	2356	14	0	0
T7	180455	0	0	0
T8	128916	2042	0	0
T9	575035	0	0	0
T10	64552	2492	0	0
T11	516397	250	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	74	0	0
T15	0	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221520	0	0
T1	2220	15	0	0
T2	2058	15	0	0
T3	74256	240	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	94	0	0
T9	575035	0	0	0
T10	64552	1620	0	0
T11	516397	8	0	0
T12	76767	0	0	0
T13	0	98	0	0
T14	0	74	0	0
T15	0	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	225995	0	0
GntImpliesValid_A	407386072	225995	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	225995	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3080253	0	0
ReadyAndValidImplyGrant_A	407386072	225995	0	0
ReqAndReadyImplyGrant_A	407386072	225995	0	0
ReqImpliesValid_A	407386072	582679	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	225995	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	225995	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	237	0	0
T4	2356	9	0	0
T7	180455	496	0	0
T8	128916	91	0	0
T9	575035	0	0	0
T10	64552	1581	0	0
T11	516397	20	0	0
T12	76767	0	0	0
T13	0	103	0	0
T14	0	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	225995	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	237	0	0
T4	2356	9	0	0
T7	180455	496	0	0
T8	128916	91	0	0
T9	575035	0	0	0
T10	64552	1581	0	0
T11	516397	20	0	0
T12	76767	0	0	0
T13	0	103	0	0
T14	0	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	225995	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	237	0	0
T4	2356	9	0	0
T7	180455	496	0	0
T8	128916	91	0	0
T9	575035	0	0	0
T10	64552	1581	0	0
T11	516397	20	0	0
T12	76767	0	0	0
T13	0	103	0	0
T14	0	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3080253	0	0
T1	2220	17	0	0
T2	2058	11	0	0
T3	74256	1852	0	0
T4	2356	9	0	0
T7	180455	1625	0	0
T8	128916	32617	0	0
T9	575035	1	0	0
T10	64552	1363	0	0
T11	516397	5722	0	0
T12	76767	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	225995	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	237	0	0
T4	2356	9	0	0
T7	180455	496	0	0
T8	128916	91	0	0
T9	575035	0	0	0
T10	64552	1581	0	0
T11	516397	20	0	0
T12	76767	0	0	0
T13	0	103	0	0
T14	0	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	225995	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	237	0	0
T4	2356	9	0	0
T7	180455	496	0	0
T8	128916	91	0	0
T9	575035	0	0	0
T10	64552	1581	0	0
T11	516397	20	0	0
T12	76767	0	0	0
T13	0	103	0	0
T14	0	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	582679	0	0
T1	2220	22	0	0
T2	2058	10	0	0
T3	74256	371	0	0
T4	2356	10	0	0
T7	180455	1180	0	0
T8	128916	891	0	0
T9	575035	0	0	0
T10	64552	1801	0	0
T11	516397	899	0	0
T12	76767	0	0	0
T13	0	113	0	0
T14	0	84	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	225995	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	237	0	0
T4	2356	9	0	0
T7	180455	496	0	0
T8	128916	91	0	0
T9	575035	0	0	0
T10	64552	1581	0	0
T11	516397	20	0	0
T12	76767	0	0	0
T13	0	103	0	0
T14	0	84	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	209586	0	0
GntImpliesValid_A	407386072	209586	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	209586	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	4696074	0	0
ReadyAndValidImplyGrant_A	407386072	209586	0	0
ReqAndReadyImplyGrant_A	407386072	209586	0	0
ReqImpliesValid_A	407386072	1034943	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	209586	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	209586	0	0
T1	2220	13	0	0
T2	2058	14	0	0
T3	74256	214	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	70	0	0
T9	575035	0	0	0
T10	64552	589	0	0
T11	516397	16	0	0
T12	76767	545	0	0
T13	0	118	0	0
T14	0	90	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	209586	0	0
T1	2220	13	0	0
T2	2058	14	0	0
T3	74256	214	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	70	0	0
T9	575035	0	0	0
T10	64552	589	0	0
T11	516397	16	0	0
T12	76767	545	0	0
T13	0	118	0	0
T14	0	90	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	209586	0	0
T1	2220	13	0	0
T2	2058	14	0	0
T3	74256	214	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	70	0	0
T9	575035	0	0	0
T10	64552	589	0	0
T11	516397	16	0	0
T12	76767	545	0	0
T13	0	118	0	0
T14	0	90	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	4696074	0	0
T1	2220	68	0	0
T2	2058	102	0	0
T3	74256	1839	0	0
T4	2356	74	0	0
T7	180455	0	0	0
T8	128916	64236	0	0
T9	575035	0	0	0
T10	64552	2825	0	0
T11	516397	6873	0	0
T12	76767	71	0	0
T13	0	569	0	0
T14	0	3322	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	209586	0	0
T1	2220	13	0	0
T2	2058	14	0	0
T3	74256	214	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	70	0	0
T9	575035	0	0	0
T10	64552	589	0	0
T11	516397	16	0	0
T12	76767	545	0	0
T13	0	118	0	0
T14	0	90	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	209586	0	0
T1	2220	13	0	0
T2	2058	14	0	0
T3	74256	214	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	70	0	0
T9	575035	0	0	0
T10	64552	589	0	0
T11	516397	16	0	0
T12	76767	545	0	0
T13	0	118	0	0
T14	0	90	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	1034943	0	0
T1	2220	22	0	0
T2	2058	23	0	0
T3	74256	297	0	0
T4	2356	16	0	0
T7	180455	0	0	0
T8	128916	2781	0	0
T9	575035	0	0	0
T10	64552	711	0	0
T11	516397	1253	0	0
T12	76767	9434	0	0
T13	0	147	0	0
T14	0	110	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	209586	0	0
T1	2220	13	0	0
T2	2058	14	0	0
T3	74256	214	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	70	0	0
T9	575035	0	0	0
T10	64552	589	0	0
T11	516397	16	0	0
T12	76767	545	0	0
T13	0	118	0	0
T14	0	90	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	222567	0	0
GntImpliesValid_A	407386072	222567	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	222567	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	4795954	0	0
ReadyAndValidImplyGrant_A	407386072	222567	0	0
ReqAndReadyImplyGrant_A	407386072	222567	0	0
ReqImpliesValid_A	407386072	1170081	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	222567	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222567	0	0
T1	2220	17	0	0
T2	2058	14	0	0
T3	74256	236	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1028	0	0
T11	516397	10	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	77	0	0
T15	0	22	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222567	0	0
T1	2220	17	0	0
T2	2058	14	0	0
T3	74256	236	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1028	0	0
T11	516397	10	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	77	0	0
T15	0	22	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222567	0	0
T1	2220	17	0	0
T2	2058	14	0	0
T3	74256	236	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1028	0	0
T11	516397	10	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	77	0	0
T15	0	22	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	4795954	0	0
T1	2220	114	0	0
T2	2058	69	0	0
T3	74256	1982	0	0
T4	2356	117	0	0
T7	180455	0	0	0
T8	128916	23564	0	0
T9	575035	0	0	0
T10	64552	3633	0	0
T11	516397	3345	0	0
T12	76767	0	0	0
T13	0	423	0	0
T14	0	1574	0	0
T15	0	130	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222567	0	0
T1	2220	17	0	0
T2	2058	14	0	0
T3	74256	236	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1028	0	0
T11	516397	10	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	77	0	0
T15	0	22	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222567	0	0
T1	2220	17	0	0
T2	2058	14	0	0
T3	74256	236	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1028	0	0
T11	516397	10	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	77	0	0
T15	0	22	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	1170081	0	0
T1	2220	32	0	0
T2	2058	14	0	0
T3	74256	337	0	0
T4	2356	23	0	0
T7	180455	0	0	0
T8	128916	1714	0	0
T9	575035	0	0	0
T10	64552	1979	0	0
T11	516397	10	0	0
T12	76767	0	0	0
T13	0	136	0	0
T14	0	99	0	0
T15	0	34	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222567	0	0
T1	2220	17	0	0
T2	2058	14	0	0
T3	74256	236	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1028	0	0
T11	516397	10	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	77	0	0
T15	0	22	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	221181	0	0
GntImpliesValid_A	407386072	221181	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	221181	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	4730510	0	0
ReadyAndValidImplyGrant_A	407386072	221181	0	0
ReqAndReadyImplyGrant_A	407386072	221181	0	0
ReqImpliesValid_A	407386072	1169922	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	221181	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221181	0	0
T1	2220	16	0	0
T2	2058	19	0	0
T3	74256	219	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	108	0	0
T9	575035	0	0	0
T10	64552	1125	0	0
T11	516397	15	0	0
T12	76767	460	0	0
T13	0	105	0	0
T14	0	94	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221181	0	0
T1	2220	16	0	0
T2	2058	19	0	0
T3	74256	219	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	108	0	0
T9	575035	0	0	0
T10	64552	1125	0	0
T11	516397	15	0	0
T12	76767	460	0	0
T13	0	105	0	0
T14	0	94	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221181	0	0
T1	2220	16	0	0
T2	2058	19	0	0
T3	74256	219	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	108	0	0
T9	575035	0	0	0
T10	64552	1125	0	0
T11	516397	15	0	0
T12	76767	460	0	0
T13	0	105	0	0
T14	0	94	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	4730510	0	0
T1	2220	77	0	0
T2	2058	80	0	0
T3	74256	4473	0	0
T4	2356	83	0	0
T7	180455	0	0	0
T8	128916	56827	0	0
T9	575035	0	0	0
T10	64552	4204	0	0
T11	516397	31025	0	0
T12	76767	761	0	0
T13	0	424	0	0
T14	0	7344	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221181	0	0
T1	2220	16	0	0
T2	2058	19	0	0
T3	74256	219	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	108	0	0
T9	575035	0	0	0
T10	64552	1125	0	0
T11	516397	15	0	0
T12	76767	460	0	0
T13	0	105	0	0
T14	0	94	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221181	0	0
T1	2220	16	0	0
T2	2058	19	0	0
T3	74256	219	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	108	0	0
T9	575035	0	0	0
T10	64552	1125	0	0
T11	516397	15	0	0
T12	76767	460	0	0
T13	0	105	0	0
T14	0	94	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	1169922	0	0
T1	2220	33	0	0
T2	2058	34	0	0
T3	74256	630	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	5095	0	0
T9	575035	0	0	0
T10	64552	5277	0	0
T11	516397	2732	0	0
T12	76767	4445	0	0
T13	0	140	0	0
T14	0	302	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	221181	0	0
T1	2220	16	0	0
T2	2058	19	0	0
T3	74256	219	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	108	0	0
T9	575035	0	0	0
T10	64552	1125	0	0
T11	516397	15	0	0
T12	76767	460	0	0
T13	0	105	0	0
T14	0	94	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	230575	0	0
GntImpliesValid_A	407386072	230575	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	230575	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	4642143	0	0
ReadyAndValidImplyGrant_A	407386072	230575	0	0
ReqAndReadyImplyGrant_A	407386072	230575	0	0
ReqImpliesValid_A	407386072	1186616	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	230575	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	230575	0	0
T1	2220	12	0	0
T2	2058	8	0	0
T3	74256	221	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	87	0	0
T9	575035	0	0	0
T10	64552	570	0	0
T11	516397	12	0	0
T12	76767	0	0	0
T13	0	108	0	0
T14	0	78	0	0
T15	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	230575	0	0
T1	2220	12	0	0
T2	2058	8	0	0
T3	74256	221	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	87	0	0
T9	575035	0	0	0
T10	64552	570	0	0
T11	516397	12	0	0
T12	76767	0	0	0
T13	0	108	0	0
T14	0	78	0	0
T15	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	230575	0	0
T1	2220	12	0	0
T2	2058	8	0	0
T3	74256	221	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	87	0	0
T9	575035	0	0	0
T10	64552	570	0	0
T11	516397	12	0	0
T12	76767	0	0	0
T13	0	108	0	0
T14	0	78	0	0
T15	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	4642143	0	0
T1	2220	75	0	0
T2	2058	37	0	0
T3	74256	1827	0	0
T4	2356	70	0	0
T7	180455	0	0	0
T8	128916	41309	0	0
T9	575035	0	0	0
T10	64552	2086	0	0
T11	516397	2032	0	0
T12	76767	0	0	0
T13	0	748	0	0
T14	0	1034	0	0
T15	0	236	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	230575	0	0
T1	2220	12	0	0
T2	2058	8	0	0
T3	74256	221	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	87	0	0
T9	575035	0	0	0
T10	64552	570	0	0
T11	516397	12	0	0
T12	76767	0	0	0
T13	0	108	0	0
T14	0	78	0	0
T15	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	230575	0	0
T1	2220	12	0	0
T2	2058	8	0	0
T3	74256	221	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	87	0	0
T9	575035	0	0	0
T10	64552	570	0	0
T11	516397	12	0	0
T12	76767	0	0	0
T13	0	108	0	0
T14	0	78	0	0
T15	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	1186616	0	0
T1	2220	12	0	0
T2	2058	8	0	0
T3	74256	395	0	0
T4	2356	15	0	0
T7	180455	0	0	0
T8	128916	3750	0	0
T9	575035	0	0	0
T10	64552	652	0	0
T11	516397	12	0	0
T12	76767	0	0	0
T13	0	215	0	0
T14	0	83	0	0
T15	0	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	230575	0	0
T1	2220	12	0	0
T2	2058	8	0	0
T3	74256	221	0	0
T4	2356	10	0	0
T7	180455	0	0	0
T8	128916	87	0	0
T9	575035	0	0	0
T10	64552	570	0	0
T11	516397	12	0	0
T12	76767	0	0	0
T13	0	108	0	0
T14	0	78	0	0
T15	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	220260	0	0
GntImpliesValid_A	407386072	220260	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	220260	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3040984	0	0
ReadyAndValidImplyGrant_A	407386072	220260	0	0
ReqAndReadyImplyGrant_A	407386072	220260	0	0
ReqImpliesValid_A	407386072	612955	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	220260	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220260	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	233	0	0
T4	2356	20	0	0
T7	180455	0	0	0
T8	128916	71	0	0
T9	575035	0	0	0
T10	64552	1005	0	0
T11	516397	15	0	0
T12	76767	0	0	0
T13	0	109	0	0
T14	0	69	0	0
T15	0	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220260	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	233	0	0
T4	2356	20	0	0
T7	180455	0	0	0
T8	128916	71	0	0
T9	575035	0	0	0
T10	64552	1005	0	0
T11	516397	15	0	0
T12	76767	0	0	0
T13	0	109	0	0
T14	0	69	0	0
T15	0	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220260	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	233	0	0
T4	2356	20	0	0
T7	180455	0	0	0
T8	128916	71	0	0
T9	575035	0	0	0
T10	64552	1005	0	0
T11	516397	15	0	0
T12	76767	0	0	0
T13	0	109	0	0
T14	0	69	0	0
T15	0	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3040984	0	0
T1	2220	20	0	0
T2	2058	10	0	0
T3	74256	1741	0	0
T4	2356	17	0	0
T7	180455	1	0	0
T8	128916	20307	0	0
T9	575035	1	0	0
T10	64552	559	0	0
T11	516397	6016	0	0
T12	76767	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220260	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	233	0	0
T4	2356	20	0	0
T7	180455	0	0	0
T8	128916	71	0	0
T9	575035	0	0	0
T10	64552	1005	0	0
T11	516397	15	0	0
T12	76767	0	0	0
T13	0	109	0	0
T14	0	69	0	0
T15	0	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220260	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	233	0	0
T4	2356	20	0	0
T7	180455	0	0	0
T8	128916	71	0	0
T9	575035	0	0	0
T10	64552	1005	0	0
T11	516397	15	0	0
T12	76767	0	0	0
T13	0	109	0	0
T14	0	69	0	0
T15	0	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	612955	0	0
T1	2220	19	0	0
T2	2058	11	0	0
T3	74256	327	0	0
T4	2356	24	0	0
T7	180455	0	0	0
T8	128916	325	0	0
T9	575035	0	0	0
T10	64552	1453	0	0
T11	516397	552	0	0
T12	76767	0	0	0
T13	0	114	0	0
T14	0	76	0	0
T15	0	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220260	0	0
T1	2220	19	0	0
T2	2058	10	0	0
T3	74256	233	0	0
T4	2356	20	0	0
T7	180455	0	0	0
T8	128916	71	0	0
T9	575035	0	0	0
T10	64552	1005	0	0
T11	516397	15	0	0
T12	76767	0	0	0
T13	0	109	0	0
T14	0	69	0	0
T15	0	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	220966	0	0
GntImpliesValid_A	407386072	220966	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	220966	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3042080	0	0
ReadyAndValidImplyGrant_A	407386072	220966	0	0
ReqAndReadyImplyGrant_A	407386072	220966	0	0
ReqImpliesValid_A	407386072	616917	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	220966	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220966	0	0
T1	2220	13	0	0
T2	2058	18	0	0
T3	74256	213	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	95	0	0
T9	575035	0	0	0
T10	64552	1967	0	0
T11	516397	13	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	70	0	0
T15	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220966	0	0
T1	2220	13	0	0
T2	2058	18	0	0
T3	74256	213	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	95	0	0
T9	575035	0	0	0
T10	64552	1967	0	0
T11	516397	13	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	70	0	0
T15	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220966	0	0
T1	2220	13	0	0
T2	2058	18	0	0
T3	74256	213	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	95	0	0
T9	575035	0	0	0
T10	64552	1967	0	0
T11	516397	13	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	70	0	0
T15	0	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3042080	0	0
T1	2220	14	0	0
T2	2058	18	0	0
T3	74256	1569	0	0
T4	2356	19	0	0
T7	180455	1	0	0
T8	128916	28938	0	0
T9	575035	1	0	0
T10	64552	847	0	0
T11	516397	5030	0	0
T12	76767	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220966	0	0
T1	2220	13	0	0
T2	2058	18	0	0
T3	74256	213	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	95	0	0
T9	575035	0	0	0
T10	64552	1967	0	0
T11	516397	13	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	70	0	0
T15	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220966	0	0
T1	2220	13	0	0
T2	2058	18	0	0
T3	74256	213	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	95	0	0
T9	575035	0	0	0
T10	64552	1967	0	0
T11	516397	13	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	70	0	0
T15	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	616917	0	0
T1	2220	13	0	0
T2	2058	19	0	0
T3	74256	369	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	3741	0	0
T9	575035	0	0	0
T10	64552	3089	0	0
T11	516397	13	0	0
T12	76767	0	0	0
T13	0	105	0	0
T14	0	70	0	0
T15	0	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220966	0	0
T1	2220	13	0	0
T2	2058	18	0	0
T3	74256	213	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	95	0	0
T9	575035	0	0	0
T10	64552	1967	0	0
T11	516397	13	0	0
T12	76767	0	0	0
T13	0	99	0	0
T14	0	70	0	0
T15	0	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	224119	0	0
GntImpliesValid_A	407386072	224119	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	224119	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3129552	0	0
ReadyAndValidImplyGrant_A	407386072	224119	0	0
ReqAndReadyImplyGrant_A	407386072	224119	0	0
ReqImpliesValid_A	407386072	600505	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	224119	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	224119	0	0
T1	2220	9	0	0
T2	2058	14	0	0
T3	74256	226	0	0
T4	2356	17	0	0
T7	180455	440	0	0
T8	128916	98	0	0
T9	575035	0	0	0
T10	64552	984	0	0
T11	516397	14	0	0
T12	76767	458	0	0
T13	0	86	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	224119	0	0
T1	2220	9	0	0
T2	2058	14	0	0
T3	74256	226	0	0
T4	2356	17	0	0
T7	180455	440	0	0
T8	128916	98	0	0
T9	575035	0	0	0
T10	64552	984	0	0
T11	516397	14	0	0
T12	76767	458	0	0
T13	0	86	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	224119	0	0
T1	2220	9	0	0
T2	2058	14	0	0
T3	74256	226	0	0
T4	2356	17	0	0
T7	180455	440	0	0
T8	128916	98	0	0
T9	575035	0	0	0
T10	64552	984	0	0
T11	516397	14	0	0
T12	76767	458	0	0
T13	0	86	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3129552	0	0
T1	2220	10	0	0
T2	2058	15	0	0
T3	74256	1621	0	0
T4	2356	17	0	0
T7	180455	1305	0	0
T8	128916	32595	0	0
T9	575035	1	0	0
T10	64552	574	0	0
T11	516397	4523	0	0
T12	76767	526	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	224119	0	0
T1	2220	9	0	0
T2	2058	14	0	0
T3	74256	226	0	0
T4	2356	17	0	0
T7	180455	440	0	0
T8	128916	98	0	0
T9	575035	0	0	0
T10	64552	984	0	0
T11	516397	14	0	0
T12	76767	458	0	0
T13	0	86	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	224119	0	0
T1	2220	9	0	0
T2	2058	14	0	0
T3	74256	226	0	0
T4	2356	17	0	0
T7	180455	440	0	0
T8	128916	98	0	0
T9	575035	0	0	0
T10	64552	984	0	0
T11	516397	14	0	0
T12	76767	458	0	0
T13	0	86	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	600505	0	0
T1	2220	9	0	0
T2	2058	14	0	0
T3	74256	300	0	0
T4	2356	18	0	0
T7	180455	1087	0	0
T8	128916	2342	0	0
T9	575035	0	0	0
T10	64552	1396	0	0
T11	516397	108	0	0
T12	76767	4594	0	0
T13	0	94	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	224119	0	0
T1	2220	9	0	0
T2	2058	14	0	0
T3	74256	226	0	0
T4	2356	17	0	0
T7	180455	440	0	0
T8	128916	98	0	0
T9	575035	0	0	0
T10	64552	984	0	0
T11	516397	14	0	0
T12	76767	458	0	0
T13	0	86	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	222375	0	0
GntImpliesValid_A	407386072	222375	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	222375	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3053295	0	0
ReadyAndValidImplyGrant_A	407386072	222375	0	0
ReqAndReadyImplyGrant_A	407386072	222375	0	0
ReqImpliesValid_A	407386072	589717	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	222375	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222375	0	0
T1	2220	18	0	0
T2	2058	11	0	0
T3	74256	204	0	0
T4	2356	7	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	591	0	0
T11	516397	14	0	0
T12	76767	0	0	0
T13	0	117	0	0
T14	0	87	0	0
T15	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222375	0	0
T1	2220	18	0	0
T2	2058	11	0	0
T3	74256	204	0	0
T4	2356	7	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	591	0	0
T11	516397	14	0	0
T12	76767	0	0	0
T13	0	117	0	0
T14	0	87	0	0
T15	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222375	0	0
T1	2220	18	0	0
T2	2058	11	0	0
T3	74256	204	0	0
T4	2356	7	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	591	0	0
T11	516397	14	0	0
T12	76767	0	0	0
T13	0	117	0	0
T14	0	87	0	0
T15	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3053295	0	0
T1	2220	19	0	0
T2	2058	12	0	0
T3	74256	1472	0	0
T4	2356	7	0	0
T7	180455	1	0	0
T8	128916	31367	0	0
T9	575035	1	0	0
T10	64552	579	0	0
T11	516397	3017	0	0
T12	76767	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222375	0	0
T1	2220	18	0	0
T2	2058	11	0	0
T3	74256	204	0	0
T4	2356	7	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	591	0	0
T11	516397	14	0	0
T12	76767	0	0	0
T13	0	117	0	0
T14	0	87	0	0
T15	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222375	0	0
T1	2220	18	0	0
T2	2058	11	0	0
T3	74256	204	0	0
T4	2356	7	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	591	0	0
T11	516397	14	0	0
T12	76767	0	0	0
T13	0	117	0	0
T14	0	87	0	0
T15	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	589717	0	0
T1	2220	18	0	0
T2	2058	11	0	0
T3	74256	253	0	0
T4	2356	8	0	0
T7	180455	0	0	0
T8	128916	2275	0	0
T9	575035	0	0	0
T10	64552	605	0	0
T11	516397	721	0	0
T12	76767	0	0	0
T13	0	125	0	0
T14	0	93	0	0
T15	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	222375	0	0
T1	2220	18	0	0
T2	2058	11	0	0
T3	74256	204	0	0
T4	2356	7	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	591	0	0
T11	516397	14	0	0
T12	76767	0	0	0
T13	0	117	0	0
T14	0	87	0	0
T15	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	217489	0	0
GntImpliesValid_A	407386072	217489	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	217489	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3091825	0	0
ReadyAndValidImplyGrant_A	407386072	217489	0	0
ReqAndReadyImplyGrant_A	407386072	217489	0	0
ReqImpliesValid_A	407386072	584711	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	217489	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217489	0	0
T1	2220	8	0	0
T2	2058	16	0	0
T3	74256	210	0	0
T4	2356	10	0	0
T7	180455	443	0	0
T8	128916	89	0	0
T9	575035	0	0	0
T10	64552	562	0	0
T11	516397	14	0	0
T12	76767	529	0	0
T13	0	89	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217489	0	0
T1	2220	8	0	0
T2	2058	16	0	0
T3	74256	210	0	0
T4	2356	10	0	0
T7	180455	443	0	0
T8	128916	89	0	0
T9	575035	0	0	0
T10	64552	562	0	0
T11	516397	14	0	0
T12	76767	529	0	0
T13	0	89	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217489	0	0
T1	2220	8	0	0
T2	2058	16	0	0
T3	74256	210	0	0
T4	2356	10	0	0
T7	180455	443	0	0
T8	128916	89	0	0
T9	575035	0	0	0
T10	64552	562	0	0
T11	516397	14	0	0
T12	76767	529	0	0
T13	0	89	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3091825	0	0
T1	2220	9	0	0
T2	2058	16	0	0
T3	74256	1619	0	0
T4	2356	8	0	0
T7	180455	1464	0	0
T8	128916	30602	0	0
T9	575035	1	0	0
T10	64552	555	0	0
T11	516397	4190	0	0
T12	76767	1150	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217489	0	0
T1	2220	8	0	0
T2	2058	16	0	0
T3	74256	210	0	0
T4	2356	10	0	0
T7	180455	443	0	0
T8	128916	89	0	0
T9	575035	0	0	0
T10	64552	562	0	0
T11	516397	14	0	0
T12	76767	529	0	0
T13	0	89	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217489	0	0
T1	2220	8	0	0
T2	2058	16	0	0
T3	74256	210	0	0
T4	2356	10	0	0
T7	180455	443	0	0
T8	128916	89	0	0
T9	575035	0	0	0
T10	64552	562	0	0
T11	516397	14	0	0
T12	76767	529	0	0
T13	0	89	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	584711	0	0
T1	2220	8	0	0
T2	2058	17	0	0
T3	74256	279	0	0
T4	2356	13	0	0
T7	180455	1081	0	0
T8	128916	1974	0	0
T9	575035	0	0	0
T10	64552	571	0	0
T11	516397	524	0	0
T12	76767	2197	0	0
T13	0	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217489	0	0
T1	2220	8	0	0
T2	2058	16	0	0
T3	74256	210	0	0
T4	2356	10	0	0
T7	180455	443	0	0
T8	128916	89	0	0
T9	575035	0	0	0
T10	64552	562	0	0
T11	516397	14	0	0
T12	76767	529	0	0
T13	0	89	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	220773	0	0
GntImpliesValid_A	407386072	220773	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	220773	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3053266	0	0
ReadyAndValidImplyGrant_A	407386072	220773	0	0
ReqAndReadyImplyGrant_A	407386072	220773	0	0
ReqImpliesValid_A	407386072	585988	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	220773	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220773	0	0
T1	2220	19	0	0
T2	2058	5	0	0
T3	74256	231	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	92	0	0
T9	575035	506	0	0
T10	64552	1072	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	91	0	0
T14	0	79	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220773	0	0
T1	2220	19	0	0
T2	2058	5	0	0
T3	74256	231	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	92	0	0
T9	575035	506	0	0
T10	64552	1072	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	91	0	0
T14	0	79	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220773	0	0
T1	2220	19	0	0
T2	2058	5	0	0
T3	74256	231	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	92	0	0
T9	575035	506	0	0
T10	64552	1072	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	91	0	0
T14	0	79	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3053266	0	0
T1	2220	19	0	0
T2	2058	6	0	0
T3	74256	1703	0	0
T4	2356	14	0	0
T7	180455	1	0	0
T8	128916	31835	0	0
T9	575035	1762	0	0
T10	64552	906	0	0
T11	516397	4058	0	0
T12	76767	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220773	0	0
T1	2220	19	0	0
T2	2058	5	0	0
T3	74256	231	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	92	0	0
T9	575035	506	0	0
T10	64552	1072	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	91	0	0
T14	0	79	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220773	0	0
T1	2220	19	0	0
T2	2058	5	0	0
T3	74256	231	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	92	0	0
T9	575035	506	0	0
T10	64552	1072	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	91	0	0
T14	0	79	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	585988	0	0
T1	2220	20	0	0
T2	2058	5	0	0
T3	74256	271	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	2491	0	0
T9	575035	1218	0	0
T10	64552	1240	0	0
T11	516397	72	0	0
T12	76767	0	0	0
T13	0	93	0	0
T14	0	89	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220773	0	0
T1	2220	19	0	0
T2	2058	5	0	0
T3	74256	231	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	92	0	0
T9	575035	506	0	0
T10	64552	1072	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	91	0	0
T14	0	79	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	217947	0	0
GntImpliesValid_A	407386072	217947	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	217947	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3037618	0	0
ReadyAndValidImplyGrant_A	407386072	217947	0	0
ReqAndReadyImplyGrant_A	407386072	217947	0	0
ReqImpliesValid_A	407386072	562368	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	217947	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217947	0	0
T1	2220	15	0	0
T2	2058	11	0	0
T3	74256	195	0	0
T4	2356	23	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	543	0	0
T11	516397	17	0	0
T12	76767	0	0	0
T13	0	104	0	0
T14	0	67	0	0
T15	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217947	0	0
T1	2220	15	0	0
T2	2058	11	0	0
T3	74256	195	0	0
T4	2356	23	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	543	0	0
T11	516397	17	0	0
T12	76767	0	0	0
T13	0	104	0	0
T14	0	67	0	0
T15	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217947	0	0
T1	2220	15	0	0
T2	2058	11	0	0
T3	74256	195	0	0
T4	2356	23	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	543	0	0
T11	516397	17	0	0
T12	76767	0	0	0
T13	0	104	0	0
T14	0	67	0	0
T15	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3037618	0	0
T1	2220	13	0	0
T2	2058	12	0	0
T3	74256	1540	0	0
T4	2356	24	0	0
T7	180455	1	0	0
T8	128916	28839	0	0
T9	575035	1	0	0
T10	64552	538	0	0
T11	516397	5200	0	0
T12	76767	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217947	0	0
T1	2220	15	0	0
T2	2058	11	0	0
T3	74256	195	0	0
T4	2356	23	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	543	0	0
T11	516397	17	0	0
T12	76767	0	0	0
T13	0	104	0	0
T14	0	67	0	0
T15	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217947	0	0
T1	2220	15	0	0
T2	2058	11	0	0
T3	74256	195	0	0
T4	2356	23	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	543	0	0
T11	516397	17	0	0
T12	76767	0	0	0
T13	0	104	0	0
T14	0	67	0	0
T15	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	562368	0	0
T1	2220	18	0	0
T2	2058	11	0	0
T3	74256	249	0	0
T4	2356	23	0	0
T7	180455	0	0	0
T8	128916	1350	0	0
T9	575035	0	0	0
T10	64552	550	0	0
T11	516397	17	0	0
T12	76767	0	0	0
T13	0	113	0	0
T14	0	67	0	0
T15	0	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217947	0	0
T1	2220	15	0	0
T2	2058	11	0	0
T3	74256	195	0	0
T4	2356	23	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	543	0	0
T11	516397	17	0	0
T12	76767	0	0	0
T13	0	104	0	0
T14	0	67	0	0
T15	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	219912	0	0
GntImpliesValid_A	407386072	219912	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	219912	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3047531	0	0
ReadyAndValidImplyGrant_A	407386072	219912	0	0
ReqAndReadyImplyGrant_A	407386072	219912	0	0
ReqImpliesValid_A	407386072	569951	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	219912	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219912	0	0
T1	2220	12	0	0
T2	2058	22	0	0
T3	74256	233	0	0
T4	2356	8	0	0
T7	180455	0	0	0
T8	128916	103	0	0
T9	575035	0	0	0
T10	64552	563	0	0
T11	516397	10	0	0
T12	76767	448	0	0
T13	0	97	0	0
T14	0	68	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219912	0	0
T1	2220	12	0	0
T2	2058	22	0	0
T3	74256	233	0	0
T4	2356	8	0	0
T7	180455	0	0	0
T8	128916	103	0	0
T9	575035	0	0	0
T10	64552	563	0	0
T11	516397	10	0	0
T12	76767	448	0	0
T13	0	97	0	0
T14	0	68	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219912	0	0
T1	2220	12	0	0
T2	2058	22	0	0
T3	74256	233	0	0
T4	2356	8	0	0
T7	180455	0	0	0
T8	128916	103	0	0
T9	575035	0	0	0
T10	64552	563	0	0
T11	516397	10	0	0
T12	76767	448	0	0
T13	0	97	0	0
T14	0	68	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3047531	0	0
T1	2220	12	0	0
T2	2058	22	0	0
T3	74256	1735	0	0
T4	2356	9	0	0
T7	180455	1	0	0
T8	128916	35990	0	0
T9	575035	1	0	0
T10	64552	558	0	0
T11	516397	3579	0	0
T12	76767	845	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219912	0	0
T1	2220	12	0	0
T2	2058	22	0	0
T3	74256	233	0	0
T4	2356	8	0	0
T7	180455	0	0	0
T8	128916	103	0	0
T9	575035	0	0	0
T10	64552	563	0	0
T11	516397	10	0	0
T12	76767	448	0	0
T13	0	97	0	0
T14	0	68	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219912	0	0
T1	2220	12	0	0
T2	2058	22	0	0
T3	74256	233	0	0
T4	2356	8	0	0
T7	180455	0	0	0
T8	128916	103	0	0
T9	575035	0	0	0
T10	64552	563	0	0
T11	516397	10	0	0
T12	76767	448	0	0
T13	0	97	0	0
T14	0	68	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	569951	0	0
T1	2220	13	0	0
T2	2058	23	0	0
T3	74256	348	0	0
T4	2356	8	0	0
T7	180455	0	0	0
T8	128916	1438	0	0
T9	575035	0	0	0
T10	64552	570	0	0
T11	516397	10	0	0
T12	76767	4135	0	0
T13	0	101	0	0
T14	0	71	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219912	0	0
T1	2220	12	0	0
T2	2058	22	0	0
T3	74256	233	0	0
T4	2356	8	0	0
T7	180455	0	0	0
T8	128916	103	0	0
T9	575035	0	0	0
T10	64552	563	0	0
T11	516397	10	0	0
T12	76767	448	0	0
T13	0	97	0	0
T14	0	68	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	240545	0	0
GntImpliesValid_A	407386072	240545	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	240545	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3153895	0	0
ReadyAndValidImplyGrant_A	407386072	240545	0	0
ReqAndReadyImplyGrant_A	407386072	240545	0	0
ReqImpliesValid_A	407386072	653914	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	240545	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	240545	0	0
T1	2220	20	0	0
T2	2058	18	0	0
T3	74256	210	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	104	0	0
T9	575035	0	0	0
T10	64552	715	0	0
T11	516397	6	0	0
T12	76767	519	0	0
T13	0	149	0	0
T14	0	77	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	240545	0	0
T1	2220	20	0	0
T2	2058	18	0	0
T3	74256	210	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	104	0	0
T9	575035	0	0	0
T10	64552	715	0	0
T11	516397	6	0	0
T12	76767	519	0	0
T13	0	149	0	0
T14	0	77	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	240545	0	0
T1	2220	20	0	0
T2	2058	18	0	0
T3	74256	210	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	104	0	0
T9	575035	0	0	0
T10	64552	715	0	0
T11	516397	6	0	0
T12	76767	519	0	0
T13	0	149	0	0
T14	0	77	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3153895	0	0
T1	2220	18	0	0
T2	2058	19	0	0
T3	74256	1557	0	0
T4	2356	19	0	0
T7	180455	1	0	0
T8	128916	36975	0	0
T9	575035	1	0	0
T10	64552	698	0	0
T11	516397	1852	0	0
T12	76767	255	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	240545	0	0
T1	2220	20	0	0
T2	2058	18	0	0
T3	74256	210	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	104	0	0
T9	575035	0	0	0
T10	64552	715	0	0
T11	516397	6	0	0
T12	76767	519	0	0
T13	0	149	0	0
T14	0	77	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	240545	0	0
T1	2220	20	0	0
T2	2058	18	0	0
T3	74256	210	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	104	0	0
T9	575035	0	0	0
T10	64552	715	0	0
T11	516397	6	0	0
T12	76767	519	0	0
T13	0	149	0	0
T14	0	77	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	653914	0	0
T1	2220	23	0	0
T2	2058	18	0	0
T3	74256	299	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	2571	0	0
T9	575035	0	0	0
T10	64552	734	0	0
T11	516397	6	0	0
T12	76767	5902	0	0
T13	0	156	0	0
T14	0	81	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	240545	0	0
T1	2220	20	0	0
T2	2058	18	0	0
T3	74256	210	0	0
T4	2356	18	0	0
T7	180455	0	0	0
T8	128916	104	0	0
T9	575035	0	0	0
T10	64552	715	0	0
T11	516397	6	0	0
T12	76767	519	0	0
T13	0	149	0	0
T14	0	77	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	219155	0	0
GntImpliesValid_A	407386072	219155	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	219155	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3096720	0	0
ReadyAndValidImplyGrant_A	407386072	219155	0	0
ReqAndReadyImplyGrant_A	407386072	219155	0	0
ReqImpliesValid_A	407386072	600159	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	219155	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219155	0	0
T1	2220	10	0	0
T2	2058	12	0	0
T3	74256	210	0	0
T4	2356	11	0	0
T7	180455	0	0	0
T8	128916	75	0	0
T9	575035	0	0	0
T10	64552	1025	0	0
T11	516397	17	0	0
T12	76767	473	0	0
T13	0	100	0	0
T14	0	96	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219155	0	0
T1	2220	10	0	0
T2	2058	12	0	0
T3	74256	210	0	0
T4	2356	11	0	0
T7	180455	0	0	0
T8	128916	75	0	0
T9	575035	0	0	0
T10	64552	1025	0	0
T11	516397	17	0	0
T12	76767	473	0	0
T13	0	100	0	0
T14	0	96	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219155	0	0
T1	2220	10	0	0
T2	2058	12	0	0
T3	74256	210	0	0
T4	2356	11	0	0
T7	180455	0	0	0
T8	128916	75	0	0
T9	575035	0	0	0
T10	64552	1025	0	0
T11	516397	17	0	0
T12	76767	473	0	0
T13	0	100	0	0
T14	0	96	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3096720	0	0
T1	2220	11	0	0
T2	2058	13	0	0
T3	74256	1530	0	0
T4	2356	12	0	0
T7	180455	1	0	0
T8	128916	22492	0	0
T9	575035	1	0	0
T10	64552	947	0	0
T11	516397	4951	0	0
T12	76767	657	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219155	0	0
T1	2220	10	0	0
T2	2058	12	0	0
T3	74256	210	0	0
T4	2356	11	0	0
T7	180455	0	0	0
T8	128916	75	0	0
T9	575035	0	0	0
T10	64552	1025	0	0
T11	516397	17	0	0
T12	76767	473	0	0
T13	0	100	0	0
T14	0	96	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219155	0	0
T1	2220	10	0	0
T2	2058	12	0	0
T3	74256	210	0	0
T4	2356	11	0	0
T7	180455	0	0	0
T8	128916	75	0	0
T9	575035	0	0	0
T10	64552	1025	0	0
T11	516397	17	0	0
T12	76767	473	0	0
T13	0	100	0	0
T14	0	96	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	600159	0	0
T1	2220	10	0	0
T2	2058	12	0	0
T3	74256	322	0	0
T4	2356	11	0	0
T7	180455	0	0	0
T8	128916	1080	0	0
T9	575035	0	0	0
T10	64552	1105	0	0
T11	516397	213	0	0
T12	76767	4669	0	0
T13	0	104	0	0
T14	0	98	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	219155	0	0
T1	2220	10	0	0
T2	2058	12	0	0
T3	74256	210	0	0
T4	2356	11	0	0
T7	180455	0	0	0
T8	128916	75	0	0
T9	575035	0	0	0
T10	64552	1025	0	0
T11	516397	17	0	0
T12	76767	473	0	0
T13	0	100	0	0
T14	0	96	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	220555	0	0
GntImpliesValid_A	407386072	220555	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	220555	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3035651	0	0
ReadyAndValidImplyGrant_A	407386072	220555	0	0
ReqAndReadyImplyGrant_A	407386072	220555	0	0
ReqImpliesValid_A	407386072	589321	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	220555	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220555	0	0
T1	2220	23	0	0
T2	2058	15	0	0
T3	74256	194	0	0
T4	2356	11	0	0
T7	180455	446	0	0
T8	128916	85	0	0
T9	575035	0	0	0
T10	64552	1095	0	0
T11	516397	18	0	0
T12	76767	0	0	0
T13	0	113	0	0
T14	0	83	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220555	0	0
T1	2220	23	0	0
T2	2058	15	0	0
T3	74256	194	0	0
T4	2356	11	0	0
T7	180455	446	0	0
T8	128916	85	0	0
T9	575035	0	0	0
T10	64552	1095	0	0
T11	516397	18	0	0
T12	76767	0	0	0
T13	0	113	0	0
T14	0	83	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220555	0	0
T1	2220	23	0	0
T2	2058	15	0	0
T3	74256	194	0	0
T4	2356	11	0	0
T7	180455	446	0	0
T8	128916	85	0	0
T9	575035	0	0	0
T10	64552	1095	0	0
T11	516397	18	0	0
T12	76767	0	0	0
T13	0	113	0	0
T14	0	83	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3035651	0	0
T1	2220	24	0	0
T2	2058	16	0	0
T3	74256	1378	0	0
T4	2356	12	0	0
T7	180455	1308	0	0
T8	128916	24283	0	0
T9	575035	1	0	0
T10	64552	931	0	0
T11	516397	5579	0	0
T12	76767	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220555	0	0
T1	2220	23	0	0
T2	2058	15	0	0
T3	74256	194	0	0
T4	2356	11	0	0
T7	180455	446	0	0
T8	128916	85	0	0
T9	575035	0	0	0
T10	64552	1095	0	0
T11	516397	18	0	0
T12	76767	0	0	0
T13	0	113	0	0
T14	0	83	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220555	0	0
T1	2220	23	0	0
T2	2058	15	0	0
T3	74256	194	0	0
T4	2356	11	0	0
T7	180455	446	0	0
T8	128916	85	0	0
T9	575035	0	0	0
T10	64552	1095	0	0
T11	516397	18	0	0
T12	76767	0	0	0
T13	0	113	0	0
T14	0	83	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	589321	0	0
T1	2220	23	0	0
T2	2058	15	0	0
T3	74256	269	0	0
T4	2356	11	0	0
T7	180455	1170	0	0
T8	128916	2181	0	0
T9	575035	0	0	0
T10	64552	1261	0	0
T11	516397	33	0	0
T12	76767	0	0	0
T13	0	119	0	0
T14	0	83	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	220555	0	0
T1	2220	23	0	0
T2	2058	15	0	0
T3	74256	194	0	0
T4	2356	11	0	0
T7	180455	446	0	0
T8	128916	85	0	0
T9	575035	0	0	0
T10	64552	1095	0	0
T11	516397	18	0	0
T12	76767	0	0	0
T13	0	113	0	0
T14	0	83	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	216996	0	0
GntImpliesValid_A	407386072	216996	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	216996	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3078445	0	0
ReadyAndValidImplyGrant_A	407386072	216996	0	0
ReqAndReadyImplyGrant_A	407386072	216996	0	0
ReqImpliesValid_A	407386072	587317	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	216996	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	216996	0	0
T1	2220	7	0	0
T2	2058	19	0	0
T3	74256	242	0	0
T4	2356	9	0	0
T7	180455	0	0	0
T8	128916	100	0	0
T9	575035	489	0	0
T10	64552	1067	0	0
T11	516397	14	0	0
T12	76767	505	0	0
T13	0	117	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	216996	0	0
T1	2220	7	0	0
T2	2058	19	0	0
T3	74256	242	0	0
T4	2356	9	0	0
T7	180455	0	0	0
T8	128916	100	0	0
T9	575035	489	0	0
T10	64552	1067	0	0
T11	516397	14	0	0
T12	76767	505	0	0
T13	0	117	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	216996	0	0
T1	2220	7	0	0
T2	2058	19	0	0
T3	74256	242	0	0
T4	2356	9	0	0
T7	180455	0	0	0
T8	128916	100	0	0
T9	575035	489	0	0
T10	64552	1067	0	0
T11	516397	14	0	0
T12	76767	505	0	0
T13	0	117	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3078445	0	0
T1	2220	8	0	0
T2	2058	18	0	0
T3	74256	1808	0	0
T4	2356	10	0	0
T7	180455	1	0	0
T8	128916	34301	0	0
T9	575035	1610	0	0
T10	64552	972	0	0
T11	516397	4667	0	0
T12	76767	881	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	216996	0	0
T1	2220	7	0	0
T2	2058	19	0	0
T3	74256	242	0	0
T4	2356	9	0	0
T7	180455	0	0	0
T8	128916	100	0	0
T9	575035	489	0	0
T10	64552	1067	0	0
T11	516397	14	0	0
T12	76767	505	0	0
T13	0	117	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	216996	0	0
T1	2220	7	0	0
T2	2058	19	0	0
T3	74256	242	0	0
T4	2356	9	0	0
T7	180455	0	0	0
T8	128916	100	0	0
T9	575035	489	0	0
T10	64552	1067	0	0
T11	516397	14	0	0
T12	76767	505	0	0
T13	0	117	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	587317	0	0
T1	2220	7	0	0
T2	2058	21	0	0
T3	74256	382	0	0
T4	2356	9	0	0
T7	180455	0	0	0
T8	128916	1689	0	0
T9	575035	1150	0	0
T10	64552	1164	0	0
T11	516397	14	0	0
T12	76767	4819	0	0
T13	0	123	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	216996	0	0
T1	2220	7	0	0
T2	2058	19	0	0
T3	74256	242	0	0
T4	2356	9	0	0
T7	180455	0	0	0
T8	128916	100	0	0
T9	575035	489	0	0
T10	64552	1067	0	0
T11	516397	14	0	0
T12	76767	505	0	0
T13	0	117	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	217501	0	0
GntImpliesValid_A	407386072	217501	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	217501	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3016586	0	0
ReadyAndValidImplyGrant_A	407386072	217501	0	0
ReqAndReadyImplyGrant_A	407386072	217501	0	0
ReqImpliesValid_A	407386072	591957	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	217501	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217501	0	0
T1	2220	6	0	0
T2	2058	23	0	0
T3	74256	256	0	0
T4	2356	16	0	0
T7	180455	542	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1521	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	114	0	0
T14	0	90	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217501	0	0
T1	2220	6	0	0
T2	2058	23	0	0
T3	74256	256	0	0
T4	2356	16	0	0
T7	180455	542	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1521	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	114	0	0
T14	0	90	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217501	0	0
T1	2220	6	0	0
T2	2058	23	0	0
T3	74256	256	0	0
T4	2356	16	0	0
T7	180455	542	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1521	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	114	0	0
T14	0	90	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3016586	0	0
T1	2220	7	0	0
T2	2058	19	0	0
T3	74256	1819	0	0
T4	2356	17	0	0
T7	180455	1847	0	0
T8	128916	23130	0	0
T9	575035	1	0	0
T10	64552	996	0	0
T11	516397	3522	0	0
T12	76767	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217501	0	0
T1	2220	6	0	0
T2	2058	23	0	0
T3	74256	256	0	0
T4	2356	16	0	0
T7	180455	542	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1521	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	114	0	0
T14	0	90	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217501	0	0
T1	2220	6	0	0
T2	2058	23	0	0
T3	74256	256	0	0
T4	2356	16	0	0
T7	180455	542	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1521	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	114	0	0
T14	0	90	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	591957	0	0
T1	2220	6	0	0
T2	2058	28	0	0
T3	74256	344	0	0
T4	2356	16	0	0
T7	180455	1174	0	0
T8	128916	1683	0	0
T9	575035	0	0	0
T10	64552	2048	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	118	0	0
T14	0	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	217501	0	0
T1	2220	6	0	0
T2	2058	23	0	0
T3	74256	256	0	0
T4	2356	16	0	0
T7	180455	542	0	0
T8	128916	72	0	0
T9	575035	0	0	0
T10	64552	1521	0	0
T11	516397	11	0	0
T12	76767	0	0	0
T13	0	114	0	0
T14	0	90	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	232769	0	0
GntImpliesValid_A	407386072	232769	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	232769	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	3072582	0	0
ReadyAndValidImplyGrant_A	407386072	232769	0	0
ReqAndReadyImplyGrant_A	407386072	232769	0	0
ReqImpliesValid_A	407386072	641912	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	0	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	232769	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	232769	0	0
T1	2220	12	0	0
T2	2058	5	0	0
T3	74256	228	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	602	0	0
T11	516397	10	0	0
T12	76767	576	0	0
T13	0	93	0	0
T14	0	78	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	232769	0	0
T1	2220	12	0	0
T2	2058	5	0	0
T3	74256	228	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	602	0	0
T11	516397	10	0	0
T12	76767	576	0	0
T13	0	93	0	0
T14	0	78	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	232769	0	0
T1	2220	12	0	0
T2	2058	5	0	0
T3	74256	228	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	602	0	0
T11	516397	10	0	0
T12	76767	576	0	0
T13	0	93	0	0
T14	0	78	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	3072582	0	0
T1	2220	13	0	0
T2	2058	6	0	0
T3	74256	1790	0	0
T4	2356	12	0	0
T7	180455	1	0	0
T8	128916	29890	0	0
T9	575035	1	0	0
T10	64552	594	0	0
T11	516397	1543	0	0
T12	76767	796	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	232769	0	0
T1	2220	12	0	0
T2	2058	5	0	0
T3	74256	228	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	602	0	0
T11	516397	10	0	0
T12	76767	576	0	0
T13	0	93	0	0
T14	0	78	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	232769	0	0
T1	2220	12	0	0
T2	2058	5	0	0
T3	74256	228	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	602	0	0
T11	516397	10	0	0
T12	76767	576	0	0
T13	0	93	0	0
T14	0	78	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	641912	0	0
T1	2220	12	0	0
T2	2058	5	0	0
T3	74256	309	0	0
T4	2356	13	0	0
T7	180455	0	0	0
T8	128916	1912	0	0
T9	575035	0	0	0
T10	64552	612	0	0
T11	516397	749	0	0
T12	76767	5550	0	0
T13	0	96	0	0
T14	0	94	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	232769	0	0
T1	2220	12	0	0
T2	2058	5	0	0
T3	74256	228	0	0
T4	2356	12	0	0
T7	180455	0	0	0
T8	128916	93	0	0
T9	575035	0	0	0
T10	64552	602	0	0
T11	516397	10	0	0
T12	76767	576	0	0
T13	0	93	0	0
T14	0	78	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	878292	0	0
GntImpliesValid_A	407386072	878292	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	878292	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	11786259	0	0
ReadyAndValidImplyGrant_A	407386072	878292	0	0
ReqAndReadyImplyGrant_A	407386072	878292	0	0
ReqImpliesValid_A	407386072	2322113	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	16916	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	878292	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	878292	0	0
T1	2220	40	0	0
T2	2058	31	0	0
T3	74256	801	0	0
T4	2356	47	0	0
T7	180455	1089	0	0
T8	128916	342	0	0
T9	575035	80	0	0
T10	64552	3574	0	0
T11	516397	56	0	0
T12	76767	568	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	878292	0	0
T1	2220	40	0	0
T2	2058	31	0	0
T3	74256	801	0	0
T4	2356	47	0	0
T7	180455	1089	0	0
T8	128916	342	0	0
T9	575035	80	0	0
T10	64552	3574	0	0
T11	516397	56	0	0
T12	76767	568	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	878292	0	0
T1	2220	40	0	0
T2	2058	31	0	0
T3	74256	801	0	0
T4	2356	47	0	0
T7	180455	1089	0	0
T8	128916	342	0	0
T9	575035	80	0	0
T10	64552	3574	0	0
T11	516397	56	0	0
T12	76767	568	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	11786259	0	0
T1	2220	1	0	0
T2	2058	1	0	0
T3	74256	5053	0	0
T4	2356	1	0	0
T7	180455	3024	0	0
T8	128916	110566	0	0
T9	575035	267	0	0
T10	64552	2	0	0
T11	516397	23102	0	0
T12	76767	3885	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	878292	0	0
T1	2220	40	0	0
T2	2058	31	0	0
T3	74256	801	0	0
T4	2356	47	0	0
T7	180455	1089	0	0
T8	128916	342	0	0
T9	575035	80	0	0
T10	64552	3574	0	0
T11	516397	56	0	0
T12	76767	568	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	878292	0	0
T1	2220	40	0	0
T2	2058	31	0	0
T3	74256	801	0	0
T4	2356	47	0	0
T7	180455	1089	0	0
T8	128916	342	0	0
T9	575035	80	0	0
T10	64552	3574	0	0
T11	516397	56	0	0
T12	76767	568	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	2322113	0	0
T1	2220	40	0	0
T2	2058	31	0	0
T3	74256	1252	0	0
T4	2356	47	0	0
T7	180455	2099	0	0
T8	128916	14455	0	0
T9	575035	95	0	0
T10	64552	3574	0	0
T11	516397	1313	0	0
T12	76767	882	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	16916	0	900
T4	2356	0	0	1
T7	180455	11	0	1
T8	128916	0	0	1
T9	575035	0	0	1
T10	64552	41	0	1
T11	516397	0	0	1
T12	76767	0	0	1
T13	8974	5	0	1
T14	64071	0	0	1
T15	1765	1	0	1
T16	0	7	0	0
T17	0	15	0	0
T18	0	16	0	0
T20	0	11	0	0
T21	0	560	0	0
T22	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	878292	0	0
T1	2220	40	0	0
T2	2058	31	0	0
T3	74256	801	0	0
T4	2356	47	0	0
T7	180455	1089	0	0
T8	128916	342	0	0
T9	575035	80	0	0
T10	64552	3574	0	0
T11	516397	56	0	0
T12	76767	568	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407386072	407256422	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407386072	880744	0	0
GntImpliesValid_A	407386072	880744	0	0
GrantKnown_A	407386072	407256422	0	0
IdxKnown_A	407386072	407256422	0	0
IndexIsCorrect_A	407386072	880744	0	0
LockArbDecision_A	407386072	0	0	0
NoReadyValidNoGrant_A	407386072	341788079	0	0
ReadyAndValidImplyGrant_A	407386072	880744	0	0
ReqAndReadyImplyGrant_A	407386072	880744	0	0
ReqImpliesValid_A	407386072	13823217	0	0
ReqStaysHighUntilGranted0_M	407386072	0	0	0
RoundRobin_A	407386072	24998	0	900
ValidKnown_A	407386072	407256422	0	0
gen_data_port_assertion.DataFlow_A	407386072	880744	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	880744	0	0
T1	2220	48	0	0
T2	2058	45	0	0
T3	74256	899	0	0
T4	2356	48	0	0
T7	180455	340	0	0
T8	128916	389	0	0
T9	575035	81	0	0
T10	64552	3492	0	0
T11	516397	57	0	0
T12	76767	528	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	880744	0	0
T1	2220	48	0	0
T2	2058	45	0	0
T3	74256	899	0	0
T4	2356	48	0	0
T7	180455	340	0	0
T8	128916	389	0	0
T9	575035	81	0	0
T10	64552	3492	0	0
T11	516397	57	0	0
T12	76767	528	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	880744	0	0
T1	2220	48	0	0
T2	2058	45	0	0
T3	74256	899	0	0
T4	2356	48	0	0
T7	180455	340	0	0
T8	128916	389	0	0
T9	575035	81	0	0
T10	64552	3492	0	0
T11	516397	57	0	0
T12	76767	528	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	341788079	0	0
T1	2220	1	0	0
T2	2058	1	0	0
T3	74256	58758	0	0
T4	2356	1	0	0
T7	180455	150160	0	0
T8	128916	114863	0	0
T9	575035	478635	0	0
T10	64552	1	0	0
T11	516397	497662	0	0
T12	76767	66252	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	880744	0	0
T1	2220	48	0	0
T2	2058	45	0	0
T3	74256	899	0	0
T4	2356	48	0	0
T7	180455	340	0	0
T8	128916	389	0	0
T9	575035	81	0	0
T10	64552	3492	0	0
T11	516397	57	0	0
T12	76767	528	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	880744	0	0
T1	2220	48	0	0
T2	2058	45	0	0
T3	74256	899	0	0
T4	2356	48	0	0
T7	180455	340	0	0
T8	128916	389	0	0
T9	575035	81	0	0
T10	64552	3492	0	0
T11	516397	57	0	0
T12	76767	528	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	13823217	0	0
T1	2220	48	0	0
T2	2058	45	0	0
T3	74256	6954	0	0
T4	2356	48	0	0
T7	180455	1573	0	0
T8	128916	138273	0	0
T9	575035	366	0	0
T10	64552	3492	0	0
T11	516397	17704	0	0
T12	76767	4028	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	24998	0	900
T3	74256	1	0	1
T4	2356	0	0	1
T7	180455	0	0	1
T8	128916	0	0	1
T9	575035	0	0	1
T10	64552	42	0	1
T11	516397	0	0	1
T12	76767	0	0	1
T13	8974	6	0	1
T14	64071	0	0	1
T15	0	2	0	0
T16	0	3	0	0
T17	0	14	0	0
T18	0	16	0	0
T19	0	2	0	0
T20	0	3	0	0
T22	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	407256422	0	0
T1	2220	2162	0	0
T2	2058	2011	0	0
T3	74256	74218	0	0
T4	2356	2267	0	0
T7	180455	180453	0	0
T8	128916	128910	0	0
T9	575035	575004	0	0
T10	64552	64510	0	0
T11	516397	516327	0	0
T12	76767	76733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407386072	880744	0	0
T1	2220	48	0	0
T2	2058	45	0	0
T3	74256	899	0	0
T4	2356	48	0	0
T7	180455	340	0	0
T8	128916	389	0	0
T9	575035	81	0	0
T10	64552	3492	0	0
T11	516397	57	0	0
T12	76767	528	0	0