Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1463383	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

231582

1

T1

35

T2

228

T3

450

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	576376	1			T1	90		T2	588		T3	1098
values[0x0]	543125	1			T1	82		T2	566		T3	1089
values[0x1]	575464	1			T1	85		T2	595		T3	1098

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1130470	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

564495

1

T1

89

T2

557

T3

1079

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27805	1			T1	4		T2	27		T3	51
valid_sources[0x01]	28024	1			T1	3		T2	18		T3	42
valid_sources[0x02]	26639	1			T1	4		T2	28		T3	47
valid_sources[0x03]	26398	1			T1	7		T2	32		T3	55
valid_sources[0x04]	26237	1			T1	4		T2	19		T3	50
valid_sources[0x05]	26353	1			T1	1		T2	34		T3	59
valid_sources[0x06]	27281	1			T1	3		T2	49		T3	54
valid_sources[0x07]	27124	1			T1	4		T2	13		T3	50
valid_sources[0x08]	25454	1			T1	3		T2	26		T3	50
valid_sources[0x09]	26919	1			T1	1		T2	36		T3	47
valid_sources[0x0a]	26509	1			T1	6		T2	35		T3	43
valid_sources[0x0b]	26863	1			T1	4		T2	34		T3	52
valid_sources[0x0c]	26465	1			T1	5		T2	33		T3	48
valid_sources[0x0d]	26326	1			T1	3		T2	39		T3	56
valid_sources[0x0e]	26602	1			T1	3		T2	17		T3	47
valid_sources[0x0f]	26484	1			T1	3		T2	21		T3	59
valid_sources[0x10]	26041	1			T1	3		T2	15		T3	44
valid_sources[0x11]	25507	1			T1	1		T2	20		T3	53
valid_sources[0x12]	26047	1			T1	3		T2	31		T3	46
valid_sources[0x13]	26711	1			T1	7		T2	20		T3	53
valid_sources[0x14]	26635	1			T1	4		T2	24		T3	49
valid_sources[0x15]	26589	1			T1	3		T2	25		T3	55
valid_sources[0x16]	26974	1			T1	2		T2	28		T3	51
valid_sources[0x17]	26524	1			T1	3		T2	38		T3	44
valid_sources[0x18]	25912	1			T1	6		T2	15		T3	52
valid_sources[0x19]	26742	1			T1	2		T2	18		T3	56
valid_sources[0x1a]	26170	1			T1	3		T2	22		T3	44
valid_sources[0x1b]	26462	1			T1	9		T2	32		T3	39
valid_sources[0x1c]	26552	1			T1	8		T2	18		T3	53
valid_sources[0x1d]	25876	1			T1	7		T2	9		T3	62
valid_sources[0x1e]	26015	1			T1	2		T2	32		T3	44
valid_sources[0x1f]	25620	1			T1	4		T2	44		T3	57
valid_sources[0x20]	26829	1			T1	3		T2	41		T3	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24319

1

T1

3

T2

23

T3

40

values[0x0]

all_enables

biggest_size

182723

1

T1

31

T2

178

T3

370

values[0x1]

all_enables

biggest_size

24540

1

T1

1

T2

27

T3

40

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1468602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238225

1

T1

24

T2

243

T3

472

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	584910	1			T1	77		T2	662		T3	1119
values[0x0]	536883	1			T1	61		T2	582		T3	1112
values[0x1]	585034	1			T1	64		T2	635		T3	1197

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1126558	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

580269

1

T1

70

T2

642

T3

1124

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26788	1			T1	2		T2	26		T3	38
valid_sources[0x01]	27582	1			T1	1		T2	22		T3	25
valid_sources[0x02]	26758	1			T1	11		T2	21		T3	82
valid_sources[0x03]	26604	1			T2	28		T3	62		T8	72
valid_sources[0x04]	26347	1			T1	5		T2	67		T3	63
valid_sources[0x05]	26100	1			T2	66		T3	67		T8	61
valid_sources[0x06]	26039	1			T1	1		T2	5		T3	48
valid_sources[0x07]	26933	1			T1	5		T2	54		T3	50
valid_sources[0x08]	26517	1			T1	1		T2	14		T3	51
valid_sources[0x09]	26314	1			T2	41		T3	32		T8	56
valid_sources[0x0a]	26353	1			T2	55		T3	62		T8	73
valid_sources[0x0b]	26534	1			T1	5		T2	11		T3	59
valid_sources[0x0c]	26877	1			T1	1		T2	36		T3	41
valid_sources[0x0d]	26887	1			T1	8		T2	9		T3	37
valid_sources[0x0e]	27050	1			T1	6		T2	29		T3	73
valid_sources[0x0f]	26642	1			T2	42		T3	49		T8	74
valid_sources[0x10]	26592	1			T1	2		T2	34		T3	42
valid_sources[0x11]	26824	1			T1	8		T2	42		T3	31
valid_sources[0x12]	26322	1			T2	8		T3	40		T8	76
valid_sources[0x13]	26695	1			T2	36		T3	54		T8	50
valid_sources[0x14]	26949	1			T2	18		T3	100		T8	52
valid_sources[0x15]	26487	1			T1	5		T2	17		T3	32
valid_sources[0x16]	27394	1			T2	12		T3	78		T8	55
valid_sources[0x17]	26476	1			T1	1		T2	25		T3	48
valid_sources[0x18]	26054	1			T1	5		T2	21		T3	61
valid_sources[0x19]	26957	1			T1	2		T2	60		T3	67
valid_sources[0x1a]	26160	1			T1	3		T2	7		T3	53
valid_sources[0x1b]	26987	1			T1	2		T2	26		T3	67
valid_sources[0x1c]	26374	1			T1	5		T2	24		T3	116
valid_sources[0x1d]	26612	1			T1	1		T2	50		T3	29
valid_sources[0x1e]	26330	1			T2	4		T3	102		T8	81
valid_sources[0x1f]	27182	1			T2	12		T3	40		T8	91
valid_sources[0x20]	27415	1			T1	1		T2	47		T3	70

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25057

1

T1

3

T2

24

T3

43

values[0x0]

all_enables

biggest_size

187904

1

T1

19

T2

188

T3

375

values[0x1]

all_enables

biggest_size

25264

1

T1

2

T2

31

T3

54

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1470052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

233896

1

T1

30

T2

271

T3

422

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	578479	1			T1	90		T2	603		T3	1026
values[0x0]	547065	1			T1	81		T2	622		T3	1055
values[0x1]	578404	1			T1	91		T2	659		T3	1077

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1136322	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

567626

1

T1

84

T2

635

T3

1033

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26638	1			T1	2		T2	31		T3	58
valid_sources[0x01]	26963	1			T1	2		T2	61		T3	55
valid_sources[0x02]	27007	1			T1	1		T2	30		T3	49
valid_sources[0x03]	26763	1			T1	3		T2	20		T3	50
valid_sources[0x04]	26535	1			T1	3		T2	47		T3	41
valid_sources[0x05]	26328	1			T1	2		T2	48		T3	55
valid_sources[0x06]	26440	1			T1	8		T2	22		T3	50
valid_sources[0x07]	27411	1			T1	6		T2	53		T3	39
valid_sources[0x08]	25852	1			T1	9		T2	18		T3	52
valid_sources[0x09]	26468	1			T1	5		T2	22		T3	45
valid_sources[0x0a]	26097	1			T1	6		T2	16		T3	47
valid_sources[0x0b]	26616	1			T1	3		T2	12		T3	53
valid_sources[0x0c]	26502	1			T1	4		T2	39		T3	50
valid_sources[0x0d]	26770	1			T1	5		T2	22		T3	50
valid_sources[0x0e]	27415	1			T1	4		T2	59		T3	52
valid_sources[0x0f]	25943	1			T1	3		T2	56		T3	49
valid_sources[0x10]	27073	1			T1	5		T2	6		T3	48
valid_sources[0x11]	26657	1			T1	5		T2	35		T3	45
valid_sources[0x12]	26391	1			T1	2		T2	27		T3	52
valid_sources[0x13]	26979	1			T1	4		T2	33		T3	46
valid_sources[0x14]	26508	1			T1	3		T2	35		T3	52
valid_sources[0x15]	26751	1			T1	8		T2	46		T3	48
valid_sources[0x16]	26458	1			T1	3		T2	15		T3	44
valid_sources[0x17]	27070	1			T1	2		T2	57		T3	49
valid_sources[0x18]	26304	1			T1	3		T2	34		T3	45
valid_sources[0x19]	26867	1			T1	3		T2	40		T3	45
valid_sources[0x1a]	25862	1			T1	4		T2	74		T3	46
valid_sources[0x1b]	26517	1			T1	4		T2	15		T3	46
valid_sources[0x1c]	26796	1			T1	5		T2	23		T3	52
valid_sources[0x1d]	26047	1			T1	2		T2	55		T3	67
valid_sources[0x1e]	26508	1			T1	6		T2	44		T3	47
valid_sources[0x1f]	26403	1			T1	7		T2	24		T3	48
valid_sources[0x20]	26547	1			T1	4		T2	68		T3	66

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24637

1

T1

4

T2

20

T3

39

values[0x0]

all_enables

biggest_size

184435

1

T1

25

T2

220

T3

337

values[0x1]

all_enables

biggest_size

24824

1

T1

1

T2

31

T3

46