Group : xbar_env_pkg::max_delay_cg_obj::max_delay_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::max_delay_cg_obj::max_delay_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

27 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
aes 100.00 1 100 1 64 64
csrng 100.00 1 100 1 64 64
edn0 100.00 1 100 1 64 64
edn1 100.00 1 100 1 64 64
entropy_src 100.00 1 100 1 64 64
flash_ctrl__core 100.00 1 100 1 64 64
flash_ctrl__mem 100.00 1 100 1 64 64
flash_ctrl__prim 100.00 1 100 1 64 64
hmac 100.00 1 100 1 64 64
keymgr 100.00 1 100 1 64 64
kmac 100.00 1 100 1 64 64
otbn 100.00 1 100 1 64 64
peri 100.00 1 100 1 64 64
rom_ctrl__regs 100.00 1 100 1 64 64
rom_ctrl__rom 100.00 1 100 1 64 64
rv_core_ibex__cfg 100.00 1 100 1 64 64
rv_core_ibex__cored 100.00 1 100 1 64 64
rv_core_ibex__corei 100.00 1 100 1 64 64
rv_dm__mem 100.00 1 100 1 64 64
rv_dm__regs 100.00 1 100 1 64 64
rv_dm__sba 100.00 1 100 1 64 64
rv_plic 100.00 1 100 1 64 64
spi_host0 100.00 1 100 1 64 64
spi_host1 100.00 1 100 1 64 64
sram_ctrl_main__ram 100.00 1 100 1 64 64
sram_ctrl_main__regs 100.00 1 100 1 64 64
usbdev 100.00 1 100 1 64 64




Group Instance : aes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance aes
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : csrng
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance csrng
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : edn0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance edn0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : edn1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance edn1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : entropy_src
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance entropy_src
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : flash_ctrl__core
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl__core

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance flash_ctrl__core
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : flash_ctrl__mem
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl__mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance flash_ctrl__mem
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : flash_ctrl__prim
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl__prim

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance flash_ctrl__prim
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : hmac
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance hmac

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance hmac
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : keymgr
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance keymgr
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : kmac
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance kmac
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : otbn
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance otbn
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : peri
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance peri

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance peri
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rom_ctrl__regs
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rom_ctrl__regs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rom_ctrl__regs
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rom_ctrl__rom
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rom_ctrl__rom

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rom_ctrl__rom
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rv_core_ibex__cfg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex__cfg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rv_core_ibex__cfg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rv_core_ibex__cored
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex__cored

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rv_core_ibex__cored
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rv_core_ibex__corei
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex__corei

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rv_core_ibex__corei
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rv_dm__mem
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_dm__mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rv_dm__mem
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rv_dm__regs
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_dm__regs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rv_dm__regs
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rv_dm__sba
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_dm__sba

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rv_dm__sba
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rv_plic
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_plic

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rv_plic
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : spi_host0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance spi_host0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : spi_host1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance spi_host1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : sram_ctrl_main__ram
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_main__ram

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance sram_ctrl_main__ram
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : sram_ctrl_main__regs
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_main__regs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance sram_ctrl_main__regs
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : usbdev
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance usbdev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance usbdev
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T1 1 T2 1 T3 1
small_delay 331 1 T12 1 T15 1 T16 1
zero 319 1 T14 1 T17 1 T19 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T2 1 T7 1 T10 1
small_delay 481 1 T1 1 T3 1 T8 1
zero 319 1 T14 1 T17 1 T19 1

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