Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1626136 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 257118 1 T1 57 T2 9 T3 411


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 638416 1 T1 132 T2 33 T3 922
values[0x0] 605754 1 T1 144 T2 5 T3 1000
values[0x1] 639084 1 T1 123 T2 43 T3 917


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1256687 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 626567 1 T1 120 T2 35 T3 950


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 30005 1 T3 50 T7 20 T8 781
valid_sources[0x01] 29329 1 T1 13 T3 45 T8 610
valid_sources[0x02] 29572 1 T3 44 T7 10 T8 803
valid_sources[0x03] 30030 1 T2 1 T3 34 T7 7
valid_sources[0x04] 30263 1 T1 11 T3 43 T7 58
valid_sources[0x05] 29181 1 T1 5 T3 46 T7 68
valid_sources[0x06] 29091 1 T3 54 T7 31 T8 630
valid_sources[0x07] 28968 1 T1 9 T3 37 T7 14
valid_sources[0x08] 30080 1 T1 5 T2 1 T3 61
valid_sources[0x09] 29436 1 T3 57 T7 43 T8 756
valid_sources[0x0a] 28920 1 T3 32 T7 27 T8 952
valid_sources[0x0b] 28705 1 T3 32 T7 23 T8 697
valid_sources[0x0c] 28365 1 T2 2 T3 41 T7 15
valid_sources[0x0d] 29603 1 T1 16 T2 3 T3 41
valid_sources[0x0e] 30223 1 T3 39 T7 15 T8 770
valid_sources[0x0f] 29226 1 T3 34 T7 17 T8 626
valid_sources[0x10] 29423 1 T1 7 T3 45 T7 39
valid_sources[0x11] 28917 1 T1 15 T2 8 T3 56
valid_sources[0x12] 29453 1 T2 2 T3 51 T7 13
valid_sources[0x13] 30085 1 T3 39 T7 8 T8 766
valid_sources[0x14] 29114 1 T3 52 T7 32 T8 749
valid_sources[0x15] 28032 1 T1 17 T2 1 T3 44
valid_sources[0x16] 29298 1 T1 25 T2 1 T3 46
valid_sources[0x17] 30533 1 T3 46 T7 29 T8 807
valid_sources[0x18] 29529 1 T2 4 T3 56 T7 9
valid_sources[0x19] 30090 1 T2 3 T3 41 T7 23
valid_sources[0x1a] 30635 1 T1 8 T2 5 T3 41
valid_sources[0x1b] 29740 1 T1 15 T2 1 T3 48
valid_sources[0x1c] 29270 1 T1 25 T3 33 T7 1
valid_sources[0x1d] 29045 1 T1 5 T3 57 T7 31
valid_sources[0x1e] 30057 1 T1 5 T3 43 T7 37
valid_sources[0x1f] 29457 1 T2 5 T3 56 T7 12
valid_sources[0x20] 29046 1 T1 19 T3 54 T7 11


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27015 1 T1 5 T2 2 T3 32
values[0x0] all_enables biggest_size 203155 1 T1 50 T2 3 T3 338
values[0x1] all_enables biggest_size 26948 1 T1 2 T2 4 T3 41


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1636735 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 266832 1 T1 61 T2 8 T3 365


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 651614 1 T1 146 T2 29 T3 946
values[0x0] 600808 1 T1 147 T2 5 T3 871
values[0x1] 651145 1 T1 135 T2 35 T3 892


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1256392 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 647175 1 T1 134 T2 23 T3 967


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29459 1 T3 58 T7 19 T8 662
valid_sources[0x01] 30086 1 T1 6 T2 7 T3 35
valid_sources[0x02] 29946 1 T2 5 T3 39 T7 6
valid_sources[0x03] 29476 1 T3 52 T7 32 T8 651
valid_sources[0x04] 29682 1 T1 14 T3 44 T7 24
valid_sources[0x05] 29850 1 T1 6 T3 37 T7 22
valid_sources[0x06] 29439 1 T3 42 T7 22 T8 712
valid_sources[0x07] 29318 1 T1 13 T3 29 T8 743
valid_sources[0x08] 30047 1 T1 8 T3 50 T7 35
valid_sources[0x09] 29948 1 T3 37 T7 58 T8 790
valid_sources[0x0a] 30264 1 T3 35 T7 28 T8 962
valid_sources[0x0b] 29366 1 T2 2 T3 29 T7 24
valid_sources[0x0c] 29521 1 T3 44 T7 31 T8 628
valid_sources[0x0d] 30156 1 T1 32 T2 7 T3 53
valid_sources[0x0e] 30378 1 T3 42 T7 19 T8 695
valid_sources[0x0f] 29362 1 T2 2 T3 58 T7 14
valid_sources[0x10] 30114 1 T1 15 T3 47 T7 29
valid_sources[0x11] 29735 1 T1 14 T3 39 T7 19
valid_sources[0x12] 30149 1 T2 1 T3 27 T7 30
valid_sources[0x13] 29641 1 T2 4 T3 33 T7 12
valid_sources[0x14] 29662 1 T2 2 T3 45 T7 37
valid_sources[0x15] 29427 1 T1 8 T3 36 T7 31
valid_sources[0x16] 29442 1 T1 36 T3 23 T7 11
valid_sources[0x17] 29482 1 T3 48 T7 29 T8 750
valid_sources[0x18] 29852 1 T3 48 T7 24 T8 740
valid_sources[0x19] 30201 1 T2 2 T3 44 T7 29
valid_sources[0x1a] 30673 1 T1 15 T3 30 T7 15
valid_sources[0x1b] 29331 1 T1 7 T2 2 T3 37
valid_sources[0x1c] 30058 1 T1 31 T2 1 T3 39
valid_sources[0x1d] 30037 1 T1 17 T3 51 T7 33
valid_sources[0x1e] 29959 1 T1 14 T2 1 T3 38
valid_sources[0x1f] 29825 1 T2 1 T3 17 T7 60
valid_sources[0x20] 29081 1 T1 19 T3 43 T7 54


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27939 1 T1 7 T2 2 T3 32
values[0x0] all_enables biggest_size 211048 1 T1 47 T2 1 T3 296
values[0x1] all_enables biggest_size 27845 1 T1 7 T2 5 T3 37


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1642046 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 259724 1 T1 57 T2 7 T3 387


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 644652 1 T1 155 T2 34 T3 938
values[0x0] 611224 1 T1 126 T2 7 T3 890
values[0x1] 645894 1 T1 147 T2 35 T3 946


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1269312 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 632458 1 T1 137 T2 25 T3 935


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29826 1 T2 1 T3 55 T7 44
valid_sources[0x01] 30165 1 T1 16 T3 43 T7 15
valid_sources[0x02] 29654 1 T2 1 T3 42 T7 16
valid_sources[0x03] 29141 1 T2 3 T3 37 T7 18
valid_sources[0x04] 29673 1 T1 8 T3 42 T7 23
valid_sources[0x05] 29825 1 T1 17 T2 1 T3 49
valid_sources[0x06] 29472 1 T3 43 T7 35 T8 576
valid_sources[0x07] 29628 1 T1 13 T3 53 T7 14
valid_sources[0x08] 29484 1 T1 5 T3 42 T7 9
valid_sources[0x09] 29363 1 T2 1 T3 40 T7 37
valid_sources[0x0a] 30165 1 T3 46 T7 30 T8 861
valid_sources[0x0b] 28751 1 T3 37 T7 21 T8 695
valid_sources[0x0c] 29881 1 T3 42 T7 23 T8 642
valid_sources[0x0d] 29668 1 T1 22 T2 1 T3 29
valid_sources[0x0e] 29866 1 T2 2 T3 44 T7 23
valid_sources[0x0f] 28943 1 T2 1 T3 55 T7 25
valid_sources[0x10] 29976 1 T1 20 T2 2 T3 46
valid_sources[0x11] 30700 1 T1 5 T3 46 T7 31
valid_sources[0x12] 30017 1 T2 2 T3 41 T7 12
valid_sources[0x13] 29924 1 T2 3 T3 47 T7 22
valid_sources[0x14] 29679 1 T2 1 T3 49 T7 23
valid_sources[0x15] 29642 1 T1 15 T3 43 T7 3
valid_sources[0x16] 29873 1 T1 33 T2 2 T3 56
valid_sources[0x17] 29514 1 T3 38 T7 18 T8 778
valid_sources[0x18] 29542 1 T2 1 T3 43 T7 15
valid_sources[0x19] 29916 1 T2 2 T3 52 T7 20
valid_sources[0x1a] 29970 1 T1 20 T2 1 T3 32
valid_sources[0x1b] 29199 1 T1 6 T3 29 T7 23
valid_sources[0x1c] 29403 1 T1 17 T2 3 T3 40
valid_sources[0x1d] 29498 1 T1 9 T2 1 T3 35
valid_sources[0x1e] 29396 1 T1 11 T3 38 T7 16
valid_sources[0x1f] 30202 1 T2 1 T3 40 T7 13
valid_sources[0x20] 29324 1 T1 7 T2 1 T3 45


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27254 1 T1 5 T2 1 T3 45
values[0x0] all_enables biggest_size 205163 1 T1 45 T2 3 T3 297
values[0x1] all_enables biggest_size 27307 1 T1 7 T2 3 T3 45

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%