Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8142223	0	0
GntImpliesValid_A	2147483647	8142223	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8142223	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	444626599	0	0
ReadyAndValidImplyGrant_A	2147483647	8142223	0	0
ReqAndReadyImplyGrant_A	2147483647	8142223	0	0
ReqImpliesValid_A	2147483647	34241119	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	48881	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8142223	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	540048	539136	0	0
T2	147984	146976	0	0
T3	1912680	1910568	0	0
T7	4730952	4730904	0	0
T8	6392352	6368904	0	0
T9	21625680	21625032	0	0
T10	1360368	1359096	0	0
T11	802536	801888	0	0
T12	5490408	5488752	0	0
T13	11164656	11162928	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8142223	0	0
T1	540048	1246	0	0
T2	147984	2314	0	0
T3	1912680	8320	0	0
T7	4730952	4698	0	0
T8	6392352	124398	0	0
T9	21625680	2827	0	0
T10	1360368	3687	0	0
T11	802536	3416	0	0
T12	5490408	372	0	0
T13	11164656	483	0	0
T14	0	1117	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8142223	0	0
T1	540048	1246	0	0
T2	147984	2314	0	0
T3	1912680	8320	0	0
T7	4730952	4698	0	0
T8	6392352	124398	0	0
T9	21625680	2827	0	0
T10	1360368	3687	0	0
T11	802536	3416	0	0
T12	5490408	372	0	0
T13	11164656	483	0	0
T14	0	1117	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	540048	539136	0	0
T2	147984	146976	0	0
T3	1912680	1910568	0	0
T7	4730952	4730904	0	0
T8	6392352	6368904	0	0
T9	21625680	21625032	0	0
T10	1360368	1359096	0	0
T11	802536	801888	0	0
T12	5490408	5488752	0	0
T13	11164656	11162928	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	540048	539136	0	0
T2	147984	146976	0	0
T3	1912680	1910568	0	0
T7	4730952	4730904	0	0
T8	6392352	6368904	0	0
T9	21625680	21625032	0	0
T10	1360368	1359096	0	0
T11	802536	801888	0	0
T12	5490408	5488752	0	0
T13	11164656	11162928	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8142223	0	0
T1	540048	1246	0	0
T2	147984	2314	0	0
T3	1912680	8320	0	0
T7	4730952	4698	0	0
T8	6392352	124398	0	0
T9	21625680	2827	0	0
T10	1360368	3687	0	0
T11	802536	3416	0	0
T12	5490408	372	0	0
T13	11164656	483	0	0
T14	0	1117	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	444626599	0	0
T1	540048	28937	0	0
T2	147984	3024	0	0
T3	1912680	87746	0	0
T7	4730952	1479137	0	0
T8	6392352	163770	0	0
T9	21625680	760131	0	0
T10	1360368	75465	0	0
T11	802536	53577	0	0
T12	5490408	191731	0	0
T13	11164656	597660	0	0
T14	0	1682	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8142223	0	0
T1	540048	1246	0	0
T2	147984	2314	0	0
T3	1912680	8320	0	0
T7	4730952	4698	0	0
T8	6392352	124398	0	0
T9	21625680	2827	0	0
T10	1360368	3687	0	0
T11	802536	3416	0	0
T12	5490408	372	0	0
T13	11164656	483	0	0
T14	0	1117	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8142223	0	0
T1	540048	1246	0	0
T2	147984	2314	0	0
T3	1912680	8320	0	0
T7	4730952	4698	0	0
T8	6392352	124398	0	0
T9	21625680	2827	0	0
T10	1360368	3687	0	0
T11	802536	3416	0	0
T12	5490408	372	0	0
T13	11164656	483	0	0
T14	0	1117	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34241119	0	0
T1	540048	2429	0	0
T2	147984	2648	0	0
T3	1912680	74949	0	0
T7	4730952	286753	0	0
T8	6392352	165004	0	0
T9	21625680	4704	0	0
T10	1360368	8090	0	0
T11	802536	7345	0	0
T12	5490408	692	0	0
T13	11164656	23134	0	0
T14	0	1535	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48881	0	21600
T8	532696	926	0	2
T9	1802140	1	0	2
T10	113364	3	0	2
T11	66878	2	0	2
T12	457534	0	0	2
T13	930388	0	0	2
T14	12898	9	0	2
T15	237918	1	0	2
T16	444164	2	0	2
T17	1265406	6	0	2
T18	0	6	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	116	0	0
T22	0	14	0	0
T23	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	540048	539136	0	0
T2	147984	146976	0	0
T3	1912680	1910568	0	0
T7	4730952	4730904	0	0
T8	6392352	6368904	0	0
T9	21625680	21625032	0	0
T10	1360368	1359096	0	0
T11	802536	801888	0	0
T12	5490408	5488752	0	0
T13	11164656	11162928	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8142223	0	0
T1	540048	1246	0	0
T2	147984	2314	0	0
T3	1912680	8320	0	0
T7	4730952	4698	0	0
T8	6392352	124398	0	0
T9	21625680	2827	0	0
T10	1360368	3687	0	0
T11	802536	3416	0	0
T12	5490408	372	0	0
T13	11164656	483	0	0
T14	0	1117	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	895973	0	0
GntImpliesValid_A	413383842	895973	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	895973	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	11444722	0	0
ReadyAndValidImplyGrant_A	413383842	895973	0	0
ReqAndReadyImplyGrant_A	413383842	895973	0	0
ReqImpliesValid_A	413383842	2416371	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	895973	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	895973	0	0
T1	22502	146	0	0
T2	6166	272	0	0
T3	79695	597	0	0
T7	197123	504	0	0
T8	266348	14637	0	0
T9	901070	317	0	0
T10	56682	418	0	0
T11	33439	382	0	0
T12	228767	46	0	0
T13	465194	56	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	895973	0	0
T1	22502	146	0	0
T2	6166	272	0	0
T3	79695	597	0	0
T7	197123	504	0	0
T8	266348	14637	0	0
T9	901070	317	0	0
T10	56682	418	0	0
T11	33439	382	0	0
T12	228767	46	0	0
T13	465194	56	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	895973	0	0
T1	22502	146	0	0
T2	6166	272	0	0
T3	79695	597	0	0
T7	197123	504	0	0
T8	266348	14637	0	0
T9	901070	317	0	0
T10	56682	418	0	0
T11	33439	382	0	0
T12	228767	46	0	0
T13	465194	56	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	11444722	0	0
T1	22502	1156	0	0
T2	6166	220	0	0
T3	79695	4282	0	0
T7	197123	171434	0	0
T8	266348	11193	0	0
T9	901070	1243	0	0
T10	56682	3128	0	0
T11	33439	2403	0	0
T12	228767	220	0	0
T13	465194	17031	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	895973	0	0
T1	22502	146	0	0
T2	6166	272	0	0
T3	79695	597	0	0
T7	197123	504	0	0
T8	266348	14637	0	0
T9	901070	317	0	0
T10	56682	418	0	0
T11	33439	382	0	0
T12	228767	46	0	0
T13	465194	56	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	895973	0	0
T1	22502	146	0	0
T2	6166	272	0	0
T3	79695	597	0	0
T7	197123	504	0	0
T8	266348	14637	0	0
T9	901070	317	0	0
T10	56682	418	0	0
T11	33439	382	0	0
T12	228767	46	0	0
T13	465194	56	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2416371	0	0
T1	22502	160	0	0
T2	6166	325	0	0
T3	79695	964	0	0
T7	197123	19508	0	0
T8	266348	18095	0	0
T9	901070	418	0	0
T10	56682	714	0	0
T11	33439	634	0	0
T12	228767	72	0	0
T13	465194	1081	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	895973	0	0
T1	22502	146	0	0
T2	6166	272	0	0
T3	79695	597	0	0
T7	197123	504	0	0
T8	266348	14637	0	0
T9	901070	317	0	0
T10	56682	418	0	0
T11	33439	382	0	0
T12	228767	46	0	0
T13	465194	56	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	924683	0	0
GntImpliesValid_A	413383842	924683	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	924683	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	11589148	0	0
ReadyAndValidImplyGrant_A	413383842	924683	0	0
ReqAndReadyImplyGrant_A	413383842	924683	0	0
ReqImpliesValid_A	413383842	2565977	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	924683	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	924683	0	0
T1	22502	122	0	0
T2	6166	251	0	0
T3	79695	1384	0	0
T7	197123	571	0	0
T8	266348	14705	0	0
T9	901070	303	0	0
T10	56682	396	0	0
T11	33439	374	0	0
T12	228767	37	0	0
T13	465194	37	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	924683	0	0
T1	22502	122	0	0
T2	6166	251	0	0
T3	79695	1384	0	0
T7	197123	571	0	0
T8	266348	14705	0	0
T9	901070	303	0	0
T10	56682	396	0	0
T11	33439	374	0	0
T12	228767	37	0	0
T13	465194	37	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	924683	0	0
T1	22502	122	0	0
T2	6166	251	0	0
T3	79695	1384	0	0
T7	197123	571	0	0
T8	266348	14705	0	0
T9	901070	303	0	0
T10	56682	396	0	0
T11	33439	374	0	0
T12	228767	37	0	0
T13	465194	37	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	11589148	0	0
T1	22502	1000	0	0
T2	6166	220	0	0
T3	79695	5000	0	0
T7	197123	185198	0	0
T8	266348	10470	0	0
T9	901070	1241	0	0
T10	56682	2869	0	0
T11	33439	2554	0	0
T12	228767	153	0	0
T13	465194	10445	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	924683	0	0
T1	22502	122	0	0
T2	6166	251	0	0
T3	79695	1384	0	0
T7	197123	571	0	0
T8	266348	14705	0	0
T9	901070	303	0	0
T10	56682	396	0	0
T11	33439	374	0	0
T12	228767	37	0	0
T13	465194	37	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	924683	0	0
T1	22502	122	0	0
T2	6166	251	0	0
T3	79695	1384	0	0
T7	197123	571	0	0
T8	266348	14705	0	0
T9	901070	303	0	0
T10	56682	396	0	0
T11	33439	374	0	0
T12	228767	37	0	0
T13	465194	37	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2565977	0	0
T1	22502	138	0	0
T2	6166	283	0	0
T3	79695	9675	0	0
T7	197123	19270	0	0
T8	266348	18954	0	0
T9	901070	422	0	0
T10	56682	520	0	0
T11	33439	749	0	0
T12	228767	55	0	0
T13	465194	1210	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	924683	0	0
T1	22502	122	0	0
T2	6166	251	0	0
T3	79695	1384	0	0
T7	197123	571	0	0
T8	266348	14705	0	0
T9	901070	303	0	0
T10	56682	396	0	0
T11	33439	374	0	0
T12	228767	37	0	0
T13	465194	37	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	221092	0	0
GntImpliesValid_A	413383842	221092	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	221092	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2869835	0	0
ReadyAndValidImplyGrant_A	413383842	221092	0	0
ReqAndReadyImplyGrant_A	413383842	221092	0	0
ReqImpliesValid_A	413383842	569433	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	221092	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221092	0	0
T1	22502	36	0	0
T2	6166	67	0	0
T3	79695	503	0	0
T7	197123	141	0	0
T8	266348	3627	0	0
T9	901070	69	0	0
T10	56682	111	0	0
T11	33439	93	0	0
T12	228767	8	0	0
T13	465194	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221092	0	0
T1	22502	36	0	0
T2	6166	67	0	0
T3	79695	503	0	0
T7	197123	141	0	0
T8	266348	3627	0	0
T9	901070	69	0	0
T10	56682	111	0	0
T11	33439	93	0	0
T12	228767	8	0	0
T13	465194	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221092	0	0
T1	22502	36	0	0
T2	6166	67	0	0
T3	79695	503	0	0
T7	197123	141	0	0
T8	266348	3627	0	0
T9	901070	69	0	0
T10	56682	111	0	0
T11	33439	93	0	0
T12	228767	8	0	0
T13	465194	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2869835	0	0
T1	22502	274	0	0
T2	6166	66	0	0
T3	79695	727	0	0
T7	197123	48568	0	0
T8	266348	2885	0	0
T9	901070	291	0	0
T10	56682	837	0	0
T11	33439	731	0	0
T12	228767	37	0	0
T13	465194	5071	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221092	0	0
T1	22502	36	0	0
T2	6166	67	0	0
T3	79695	503	0	0
T7	197123	141	0	0
T8	266348	3627	0	0
T9	901070	69	0	0
T10	56682	111	0	0
T11	33439	93	0	0
T12	228767	8	0	0
T13	465194	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221092	0	0
T1	22502	36	0	0
T2	6166	67	0	0
T3	79695	503	0	0
T7	197123	141	0	0
T8	266348	3627	0	0
T9	901070	69	0	0
T10	56682	111	0	0
T11	33439	93	0	0
T12	228767	8	0	0
T13	465194	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	569433	0	0
T1	22502	36	0	0
T2	6166	69	0	0
T3	79695	5034	0	0
T7	197123	1810	0	0
T8	266348	4383	0	0
T9	901070	74	0	0
T10	56682	159	0	0
T11	33439	112	0	0
T12	228767	8	0	0
T13	465194	333	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221092	0	0
T1	22502	36	0	0
T2	6166	67	0	0
T3	79695	503	0	0
T7	197123	141	0	0
T8	266348	3627	0	0
T9	901070	69	0	0
T10	56682	111	0	0
T11	33439	93	0	0
T12	228767	8	0	0
T13	465194	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	229303	0	0
GntImpliesValid_A	413383842	229303	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	229303	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2776230	0	0
ReadyAndValidImplyGrant_A	413383842	229303	0	0
ReqAndReadyImplyGrant_A	413383842	229303	0	0
ReqImpliesValid_A	413383842	599412	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	229303	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229303	0	0
T1	22502	30	0	0
T2	6166	58	0	0
T3	79695	0	0	0
T7	197123	104	0	0
T8	266348	4561	0	0
T9	901070	81	0	0
T10	56682	86	0	0
T11	33439	106	0	0
T12	228767	16	0	0
T13	465194	17	0	0
T14	0	82	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229303	0	0
T1	22502	30	0	0
T2	6166	58	0	0
T3	79695	0	0	0
T7	197123	104	0	0
T8	266348	4561	0	0
T9	901070	81	0	0
T10	56682	86	0	0
T11	33439	106	0	0
T12	228767	16	0	0
T13	465194	17	0	0
T14	0	82	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229303	0	0
T1	22502	30	0	0
T2	6166	58	0	0
T3	79695	0	0	0
T7	197123	104	0	0
T8	266348	4561	0	0
T9	901070	81	0	0
T10	56682	86	0	0
T11	33439	106	0	0
T12	228767	16	0	0
T13	465194	17	0	0
T14	0	82	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2776230	0	0
T1	22502	189	0	0
T2	6166	57	0	0
T3	79695	1	0	0
T7	197123	37503	0	0
T8	266348	3929	0	0
T9	901070	319	0	0
T10	56682	623	0	0
T11	33439	785	0	0
T12	228767	85	0	0
T13	465194	5943	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229303	0	0
T1	22502	30	0	0
T2	6166	58	0	0
T3	79695	0	0	0
T7	197123	104	0	0
T8	266348	4561	0	0
T9	901070	81	0	0
T10	56682	86	0	0
T11	33439	106	0	0
T12	228767	16	0	0
T13	465194	17	0	0
T14	0	82	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229303	0	0
T1	22502	30	0	0
T2	6166	58	0	0
T3	79695	0	0	0
T7	197123	104	0	0
T8	266348	4561	0	0
T9	901070	81	0	0
T10	56682	86	0	0
T11	33439	106	0	0
T12	228767	16	0	0
T13	465194	17	0	0
T14	0	82	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	599412	0	0
T1	22502	30	0	0
T2	6166	60	0	0
T3	79695	0	0	0
T7	197123	1792	0	0
T8	266348	5207	0	0
T9	901070	104	0	0
T10	56682	96	0	0
T11	33439	153	0	0
T12	228767	24	0	0
T13	465194	918	0	0
T14	0	86	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229303	0	0
T1	22502	30	0	0
T2	6166	58	0	0
T3	79695	0	0	0
T7	197123	104	0	0
T8	266348	4561	0	0
T9	901070	81	0	0
T10	56682	86	0	0
T11	33439	106	0	0
T12	228767	16	0	0
T13	465194	17	0	0
T14	0	82	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	217717	0	0
GntImpliesValid_A	413383842	217717	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	217717	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	5388886	0	0
ReadyAndValidImplyGrant_A	413383842	217717	0	0
ReqAndReadyImplyGrant_A	413383842	217717	0	0
ReqImpliesValid_A	413383842	1186635	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	217717	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	217717	0	0
T1	22502	33	0	0
T2	6166	60	0	0
T3	79695	478	0	0
T7	197123	134	0	0
T8	266348	3964	0	0
T9	901070	87	0	0
T10	56682	102	0	0
T11	33439	96	0	0
T12	228767	3	0	0
T13	465194	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	217717	0	0
T1	22502	33	0	0
T2	6166	60	0	0
T3	79695	478	0	0
T7	197123	134	0	0
T8	266348	3964	0	0
T9	901070	87	0	0
T10	56682	102	0	0
T11	33439	96	0	0
T12	228767	3	0	0
T13	465194	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	217717	0	0
T1	22502	33	0	0
T2	6166	60	0	0
T3	79695	478	0	0
T7	197123	134	0	0
T8	266348	3964	0	0
T9	901070	87	0	0
T10	56682	102	0	0
T11	33439	96	0	0
T12	228767	3	0	0
T13	465194	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	5388886	0	0
T1	22502	462	0	0
T2	6166	571	0	0
T3	79695	129	0	0
T7	197123	16928	0	0
T8	266348	23707	0	0
T9	901070	640	0	0
T10	56682	1115	0	0
T11	33439	966	0	0
T12	228767	25	0	0
T13	465194	15428	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	217717	0	0
T1	22502	33	0	0
T2	6166	60	0	0
T3	79695	478	0	0
T7	197123	134	0	0
T8	266348	3964	0	0
T9	901070	87	0	0
T10	56682	102	0	0
T11	33439	96	0	0
T12	228767	3	0	0
T13	465194	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	217717	0	0
T1	22502	33	0	0
T2	6166	60	0	0
T3	79695	478	0	0
T7	197123	134	0	0
T8	266348	3964	0	0
T9	901070	87	0	0
T10	56682	102	0	0
T11	33439	96	0	0
T12	228767	3	0	0
T13	465194	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	1186635	0	0
T1	22502	33	0	0
T2	6166	161	0	0
T3	79695	7831	0	0
T7	197123	608	0	0
T8	266348	17349	0	0
T9	901070	127	0	0
T10	56682	146	0	0
T11	33439	132	0	0
T12	228767	3	0	0
T13	465194	1148	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	217717	0	0
T1	22502	33	0	0
T2	6166	60	0	0
T3	79695	478	0	0
T7	197123	134	0	0
T8	266348	3964	0	0
T9	901070	87	0	0
T10	56682	102	0	0
T11	33439	96	0	0
T12	228767	3	0	0
T13	465194	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	214599	0	0
GntImpliesValid_A	413383842	214599	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	214599	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	4759438	0	0
ReadyAndValidImplyGrant_A	413383842	214599	0	0
ReqAndReadyImplyGrant_A	413383842	214599	0	0
ReqImpliesValid_A	413383842	1080821	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	214599	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	214599	0	0
T1	22502	49	0	0
T2	6166	56	0	0
T3	79695	586	0	0
T7	197123	104	0	0
T8	266348	2550	0	0
T9	901070	72	0	0
T10	56682	104	0	0
T11	33439	91	0	0
T12	228767	11	0	0
T13	465194	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	214599	0	0
T1	22502	49	0	0
T2	6166	56	0	0
T3	79695	586	0	0
T7	197123	104	0	0
T8	266348	2550	0	0
T9	901070	72	0	0
T10	56682	104	0	0
T11	33439	91	0	0
T12	228767	11	0	0
T13	465194	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	214599	0	0
T1	22502	49	0	0
T2	6166	56	0	0
T3	79695	586	0	0
T7	197123	104	0	0
T8	266348	2550	0	0
T9	901070	72	0	0
T10	56682	104	0	0
T11	33439	91	0	0
T12	228767	11	0	0
T13	465194	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	4759438	0	0
T1	22502	1014	0	0
T2	6166	346	0	0
T3	79695	282	0	0
T7	197123	9549	0	0
T8	266348	13545	0	0
T9	901070	502	0	0
T10	56682	2454	0	0
T11	33439	942	0	0
T12	228767	97	0	0
T13	465194	5882	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	214599	0	0
T1	22502	49	0	0
T2	6166	56	0	0
T3	79695	586	0	0
T7	197123	104	0	0
T8	266348	2550	0	0
T9	901070	72	0	0
T10	56682	104	0	0
T11	33439	91	0	0
T12	228767	11	0	0
T13	465194	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	214599	0	0
T1	22502	49	0	0
T2	6166	56	0	0
T3	79695	586	0	0
T7	197123	104	0	0
T8	266348	2550	0	0
T9	901070	72	0	0
T10	56682	104	0	0
T11	33439	91	0	0
T12	228767	11	0	0
T13	465194	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	1080821	0	0
T1	22502	65	0	0
T2	6166	123	0	0
T3	79695	10813	0	0
T7	197123	283	0	0
T8	266348	3440	0	0
T9	901070	99	0	0
T10	56682	305	0	0
T11	33439	112	0	0
T12	228767	23	0	0
T13	465194	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	214599	0	0
T1	22502	49	0	0
T2	6166	56	0	0
T3	79695	586	0	0
T7	197123	104	0	0
T8	266348	2550	0	0
T9	901070	72	0	0
T10	56682	104	0	0
T11	33439	91	0	0
T12	228767	11	0	0
T13	465194	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	232107	0	0
GntImpliesValid_A	413383842	232107	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	232107	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	4323376	0	0
ReadyAndValidImplyGrant_A	413383842	232107	0	0
ReqAndReadyImplyGrant_A	413383842	232107	0	0
ReqImpliesValid_A	413383842	1161462	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	232107	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	232107	0	0
T1	22502	44	0	0
T2	6166	69	0	0
T3	79695	0	0	0
T7	197123	136	0	0
T8	266348	3510	0	0
T9	901070	83	0	0
T10	56682	99	0	0
T11	33439	85	0	0
T12	228767	7	0	0
T13	465194	10	0	0
T14	0	109	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	232107	0	0
T1	22502	44	0	0
T2	6166	69	0	0
T3	79695	0	0	0
T7	197123	136	0	0
T8	266348	3510	0	0
T9	901070	83	0	0
T10	56682	99	0	0
T11	33439	85	0	0
T12	228767	7	0	0
T13	465194	10	0	0
T14	0	109	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	232107	0	0
T1	22502	44	0	0
T2	6166	69	0	0
T3	79695	0	0	0
T7	197123	136	0	0
T8	266348	3510	0	0
T9	901070	83	0	0
T10	56682	99	0	0
T11	33439	85	0	0
T12	228767	7	0	0
T13	465194	10	0	0
T14	0	109	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	4323376	0	0
T1	22502	385	0	0
T2	6166	320	0	0
T3	79695	0	0	0
T7	197123	66649	0	0
T8	266348	43814	0	0
T9	901070	373	0	0
T10	56682	1354	0	0
T11	33439	2454	0	0
T12	228767	153	0	0
T13	465194	7700	0	0
T14	0	605	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	232107	0	0
T1	22502	44	0	0
T2	6166	69	0	0
T3	79695	0	0	0
T7	197123	136	0	0
T8	266348	3510	0	0
T9	901070	83	0	0
T10	56682	99	0	0
T11	33439	85	0	0
T12	228767	7	0	0
T13	465194	10	0	0
T14	0	109	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	232107	0	0
T1	22502	44	0	0
T2	6166	69	0	0
T3	79695	0	0	0
T7	197123	136	0	0
T8	266348	3510	0	0
T9	901070	83	0	0
T10	56682	99	0	0
T11	33439	85	0	0
T12	228767	7	0	0
T13	465194	10	0	0
T14	0	109	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	1161462	0	0
T1	22502	54	0	0
T2	6166	88	0	0
T3	79695	0	0	0
T7	197123	4440	0	0
T8	266348	13327	0	0
T9	901070	133	0	0
T10	56682	196	0	0
T11	33439	343	0	0
T12	228767	7	0	0
T13	465194	10	0	0
T14	0	190	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	232107	0	0
T1	22502	44	0	0
T2	6166	69	0	0
T3	79695	0	0	0
T7	197123	136	0	0
T8	266348	3510	0	0
T9	901070	83	0	0
T10	56682	99	0	0
T11	33439	85	0	0
T12	228767	7	0	0
T13	465194	10	0	0
T14	0	109	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	223416	0	0
GntImpliesValid_A	413383842	223416	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	223416	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	4896103	0	0
ReadyAndValidImplyGrant_A	413383842	223416	0	0
ReqAndReadyImplyGrant_A	413383842	223416	0	0
ReqImpliesValid_A	413383842	1222424	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	223416	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223416	0	0
T1	22502	31	0	0
T2	6166	47	0	0
T3	79695	0	0	0
T7	197123	122	0	0
T8	266348	2675	0	0
T9	901070	76	0	0
T10	56682	105	0	0
T11	33439	92	0	0
T12	228767	9	0	0
T13	465194	14	0	0
T14	0	108	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223416	0	0
T1	22502	31	0	0
T2	6166	47	0	0
T3	79695	0	0	0
T7	197123	122	0	0
T8	266348	2675	0	0
T9	901070	76	0	0
T10	56682	105	0	0
T11	33439	92	0	0
T12	228767	9	0	0
T13	465194	14	0	0
T14	0	108	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223416	0	0
T1	22502	31	0	0
T2	6166	47	0	0
T3	79695	0	0	0
T7	197123	122	0	0
T8	266348	2675	0	0
T9	901070	76	0	0
T10	56682	105	0	0
T11	33439	92	0	0
T12	228767	9	0	0
T13	465194	14	0	0
T14	0	108	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	4896103	0	0
T1	22502	551	0	0
T2	6166	280	0	0
T3	79695	0	0	0
T7	197123	11676	0	0
T8	266348	14643	0	0
T9	901070	364	0	0
T10	56682	1340	0	0
T11	33439	1823	0	0
T12	228767	81	0	0
T13	465194	8586	0	0
T14	0	1077	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223416	0	0
T1	22502	31	0	0
T2	6166	47	0	0
T3	79695	0	0	0
T7	197123	122	0	0
T8	266348	2675	0	0
T9	901070	76	0	0
T10	56682	105	0	0
T11	33439	92	0	0
T12	228767	9	0	0
T13	465194	14	0	0
T14	0	108	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223416	0	0
T1	22502	31	0	0
T2	6166	47	0	0
T3	79695	0	0	0
T7	197123	122	0	0
T8	266348	2675	0	0
T9	901070	76	0	0
T10	56682	105	0	0
T11	33439	92	0	0
T12	228767	9	0	0
T13	465194	14	0	0
T14	0	108	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	1222424	0	0
T1	22502	31	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	236	0	0
T8	266348	3707	0	0
T9	901070	87	0	0
T10	56682	165	0	0
T11	33439	154	0	0
T12	228767	9	0	0
T13	465194	645	0	0
T14	0	397	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223416	0	0
T1	22502	31	0	0
T2	6166	47	0	0
T3	79695	0	0	0
T7	197123	122	0	0
T8	266348	2675	0	0
T9	901070	76	0	0
T10	56682	105	0	0
T11	33439	92	0	0
T12	228767	9	0	0
T13	465194	14	0	0
T14	0	108	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	228184	0	0
GntImpliesValid_A	413383842	228184	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	228184	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2813157	0	0
ReadyAndValidImplyGrant_A	413383842	228184	0	0
ReqAndReadyImplyGrant_A	413383842	228184	0	0
ReqImpliesValid_A	413383842	608538	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	228184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	228184	0	0
T1	22502	23	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	3248	0	0
T9	901070	87	0	0
T10	56682	114	0	0
T11	33439	110	0	0
T12	228767	11	0	0
T13	465194	16	0	0
T14	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	228184	0	0
T1	22502	23	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	3248	0	0
T9	901070	87	0	0
T10	56682	114	0	0
T11	33439	110	0	0
T12	228767	11	0	0
T13	465194	16	0	0
T14	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	228184	0	0
T1	22502	23	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	3248	0	0
T9	901070	87	0	0
T10	56682	114	0	0
T11	33439	110	0	0
T12	228767	11	0	0
T13	465194	16	0	0
T14	0	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2813157	0	0
T1	22502	157	0	0
T2	6166	65	0	0
T3	79695	1	0	0
T7	197123	43913	0	0
T8	266348	2741	0	0
T9	901070	402	0	0
T10	56682	841	0	0
T11	33439	851	0	0
T12	228767	59	0	0
T13	465194	6188	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	228184	0	0
T1	22502	23	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	3248	0	0
T9	901070	87	0	0
T10	56682	114	0	0
T11	33439	110	0	0
T12	228767	11	0	0
T13	465194	16	0	0
T14	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	228184	0	0
T1	22502	23	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	3248	0	0
T9	901070	87	0	0
T10	56682	114	0	0
T11	33439	110	0	0
T12	228767	11	0	0
T13	465194	16	0	0
T14	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	608538	0	0
T1	22502	23	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	3663	0	0
T8	266348	3768	0	0
T9	901070	107	0	0
T10	56682	161	0	0
T11	33439	140	0	0
T12	228767	11	0	0
T13	465194	154	0	0
T14	0	127	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	228184	0	0
T1	22502	23	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	3248	0	0
T9	901070	87	0	0
T10	56682	114	0	0
T11	33439	110	0	0
T12	228767	11	0	0
T13	465194	16	0	0
T14	0	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	221584	0	0
GntImpliesValid_A	413383842	221584	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	221584	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2806165	0	0
ReadyAndValidImplyGrant_A	413383842	221584	0	0
ReqAndReadyImplyGrant_A	413383842	221584	0	0
ReqImpliesValid_A	413383842	612524	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	221584	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221584	0	0
T1	22502	28	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	2600	0	0
T9	901070	67	0	0
T10	56682	106	0	0
T11	33439	95	0	0
T12	228767	13	0	0
T13	465194	9	0	0
T14	0	127	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221584	0	0
T1	22502	28	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	2600	0	0
T9	901070	67	0	0
T10	56682	106	0	0
T11	33439	95	0	0
T12	228767	13	0	0
T13	465194	9	0	0
T14	0	127	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221584	0	0
T1	22502	28	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	2600	0	0
T9	901070	67	0	0
T10	56682	106	0	0
T11	33439	95	0	0
T12	228767	13	0	0
T13	465194	9	0	0
T14	0	127	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2806165	0	0
T1	22502	242	0	0
T2	6166	70	0	0
T3	79695	1	0	0
T7	197123	40027	0	0
T8	266348	2545	0	0
T9	901070	284	0	0
T10	56682	814	0	0
T11	33439	667	0	0
T12	228767	51	0	0
T13	465194	2391	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221584	0	0
T1	22502	28	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	2600	0	0
T9	901070	67	0	0
T10	56682	106	0	0
T11	33439	95	0	0
T12	228767	13	0	0
T13	465194	9	0	0
T14	0	127	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221584	0	0
T1	22502	28	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	2600	0	0
T9	901070	67	0	0
T10	56682	106	0	0
T11	33439	95	0	0
T12	228767	13	0	0
T13	465194	9	0	0
T14	0	127	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	612524	0	0
T1	22502	28	0	0
T2	6166	75	0	0
T3	79695	0	0	0
T7	197123	2932	0	0
T8	266348	2668	0	0
T9	901070	73	0	0
T10	56682	138	0	0
T11	33439	124	0	0
T12	228767	19	0	0
T13	465194	9	0	0
T14	0	130	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221584	0	0
T1	22502	28	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	131	0	0
T8	266348	2600	0	0
T9	901070	67	0	0
T10	56682	106	0	0
T11	33439	95	0	0
T12	228767	13	0	0
T13	465194	9	0	0
T14	0	127	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	223207	0	0
GntImpliesValid_A	413383842	223207	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	223207	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2792308	0	0
ReadyAndValidImplyGrant_A	413383842	223207	0	0
ReqAndReadyImplyGrant_A	413383842	223207	0	0
ReqImpliesValid_A	413383842	584351	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	223207	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223207	0	0
T1	22502	35	0	0
T2	6166	67	0	0
T3	79695	583	0	0
T7	197123	130	0	0
T8	266348	3935	0	0
T9	901070	94	0	0
T10	56682	96	0	0
T11	33439	102	0	0
T12	228767	17	0	0
T13	465194	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223207	0	0
T1	22502	35	0	0
T2	6166	67	0	0
T3	79695	583	0	0
T7	197123	130	0	0
T8	266348	3935	0	0
T9	901070	94	0	0
T10	56682	96	0	0
T11	33439	102	0	0
T12	228767	17	0	0
T13	465194	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223207	0	0
T1	22502	35	0	0
T2	6166	67	0	0
T3	79695	583	0	0
T7	197123	130	0	0
T8	266348	3935	0	0
T9	901070	94	0	0
T10	56682	96	0	0
T11	33439	102	0	0
T12	228767	17	0	0
T13	465194	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2792308	0	0
T1	22502	289	0	0
T2	6166	66	0	0
T3	79695	782	0	0
T7	197123	46327	0	0
T8	266348	2824	0	0
T9	901070	455	0	0
T10	56682	716	0	0
T11	33439	833	0	0
T12	228767	53	0	0
T13	465194	7065	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223207	0	0
T1	22502	35	0	0
T2	6166	67	0	0
T3	79695	583	0	0
T7	197123	130	0	0
T8	266348	3935	0	0
T9	901070	94	0	0
T10	56682	96	0	0
T11	33439	102	0	0
T12	228767	17	0	0
T13	465194	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223207	0	0
T1	22502	35	0	0
T2	6166	67	0	0
T3	79695	583	0	0
T7	197123	130	0	0
T8	266348	3935	0	0
T9	901070	94	0	0
T10	56682	96	0	0
T11	33439	102	0	0
T12	228767	17	0	0
T13	465194	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	584351	0	0
T1	22502	35	0	0
T2	6166	69	0	0
T3	79695	5890	0	0
T7	197123	762	0	0
T8	266348	5060	0	0
T9	901070	99	0	0
T10	56682	140	0	0
T11	33439	136	0	0
T12	228767	41	0	0
T13	465194	997	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223207	0	0
T1	22502	35	0	0
T2	6166	67	0	0
T3	79695	583	0	0
T7	197123	130	0	0
T8	266348	3935	0	0
T9	901070	94	0	0
T10	56682	96	0	0
T11	33439	102	0	0
T12	228767	17	0	0
T13	465194	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	230560	0	0
GntImpliesValid_A	413383842	230560	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	230560	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2823334	0	0
ReadyAndValidImplyGrant_A	413383842	230560	0	0
ReqAndReadyImplyGrant_A	413383842	230560	0	0
ReqImpliesValid_A	413383842	595658	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	230560	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	230560	0	0
T1	22502	30	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	132	0	0
T8	266348	2600	0	0
T9	901070	72	0	0
T10	56682	105	0	0
T11	33439	107	0	0
T12	228767	13	0	0
T13	465194	17	0	0
T14	0	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	230560	0	0
T1	22502	30	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	132	0	0
T8	266348	2600	0	0
T9	901070	72	0	0
T10	56682	105	0	0
T11	33439	107	0	0
T12	228767	13	0	0
T13	465194	17	0	0
T14	0	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	230560	0	0
T1	22502	30	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	132	0	0
T8	266348	2600	0	0
T9	901070	72	0	0
T10	56682	105	0	0
T11	33439	107	0	0
T12	228767	13	0	0
T13	465194	17	0	0
T14	0	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2823334	0	0
T1	22502	278	0	0
T2	6166	70	0	0
T3	79695	1	0	0
T7	197123	43085	0	0
T8	266348	2540	0	0
T9	901070	307	0	0
T10	56682	812	0	0
T11	33439	822	0	0
T12	228767	54	0	0
T13	465194	3830	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	230560	0	0
T1	22502	30	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	132	0	0
T8	266348	2600	0	0
T9	901070	72	0	0
T10	56682	105	0	0
T11	33439	107	0	0
T12	228767	13	0	0
T13	465194	17	0	0
T14	0	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	230560	0	0
T1	22502	30	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	132	0	0
T8	266348	2600	0	0
T9	901070	72	0	0
T10	56682	105	0	0
T11	33439	107	0	0
T12	228767	13	0	0
T13	465194	17	0	0
T14	0	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	595658	0	0
T1	22502	30	0	0
T2	6166	75	0	0
T3	79695	0	0	0
T7	197123	4618	0	0
T8	266348	2673	0	0
T9	901070	72	0	0
T10	56682	123	0	0
T11	33439	174	0	0
T12	228767	13	0	0
T13	465194	315	0	0
T14	0	94	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	230560	0	0
T1	22502	30	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	132	0	0
T8	266348	2600	0	0
T9	901070	72	0	0
T10	56682	105	0	0
T11	33439	107	0	0
T12	228767	13	0	0
T13	465194	17	0	0
T14	0	91	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	221845	0	0
GntImpliesValid_A	413383842	221845	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	221845	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2828963	0	0
ReadyAndValidImplyGrant_A	413383842	221845	0	0
ReqAndReadyImplyGrant_A	413383842	221845	0	0
ReqImpliesValid_A	413383842	578137	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	221845	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221845	0	0
T1	22502	40	0	0
T2	6166	64	0	0
T3	79695	0	0	0
T7	197123	143	0	0
T8	266348	3062	0	0
T9	901070	82	0	0
T10	56682	99	0	0
T11	33439	92	0	0
T12	228767	11	0	0
T13	465194	10	0	0
T14	0	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221845	0	0
T1	22502	40	0	0
T2	6166	64	0	0
T3	79695	0	0	0
T7	197123	143	0	0
T8	266348	3062	0	0
T9	901070	82	0	0
T10	56682	99	0	0
T11	33439	92	0	0
T12	228767	11	0	0
T13	465194	10	0	0
T14	0	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221845	0	0
T1	22502	40	0	0
T2	6166	64	0	0
T3	79695	0	0	0
T7	197123	143	0	0
T8	266348	3062	0	0
T9	901070	82	0	0
T10	56682	99	0	0
T11	33439	92	0	0
T12	228767	11	0	0
T13	465194	10	0	0
T14	0	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2828963	0	0
T1	22502	354	0	0
T2	6166	64	0	0
T3	79695	1	0	0
T7	197123	47888	0	0
T8	266348	2509	0	0
T9	901070	316	0	0
T10	56682	678	0	0
T11	33439	666	0	0
T12	228767	46	0	0
T13	465194	3586	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221845	0	0
T1	22502	40	0	0
T2	6166	64	0	0
T3	79695	0	0	0
T7	197123	143	0	0
T8	266348	3062	0	0
T9	901070	82	0	0
T10	56682	99	0	0
T11	33439	92	0	0
T12	228767	11	0	0
T13	465194	10	0	0
T14	0	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221845	0	0
T1	22502	40	0	0
T2	6166	64	0	0
T3	79695	0	0	0
T7	197123	143	0	0
T8	266348	3062	0	0
T9	901070	82	0	0
T10	56682	99	0	0
T11	33439	92	0	0
T12	228767	11	0	0
T13	465194	10	0	0
T14	0	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	578137	0	0
T1	22502	40	0	0
T2	6166	65	0	0
T3	79695	0	0	0
T7	197123	3638	0	0
T8	266348	3629	0	0
T9	901070	100	0	0
T10	56682	124	0	0
T11	33439	132	0	0
T12	228767	23	0	0
T13	465194	10	0	0
T14	0	89	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	221845	0	0
T1	22502	40	0	0
T2	6166	64	0	0
T3	79695	0	0	0
T7	197123	143	0	0
T8	266348	3062	0	0
T9	901070	82	0	0
T10	56682	99	0	0
T11	33439	92	0	0
T12	228767	11	0	0
T13	465194	10	0	0
T14	0	84	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	227330	0	0
GntImpliesValid_A	413383842	227330	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	227330	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2875520	0	0
ReadyAndValidImplyGrant_A	413383842	227330	0	0
ReqAndReadyImplyGrant_A	413383842	227330	0	0
ReqImpliesValid_A	413383842	585805	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	227330	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	227330	0	0
T1	22502	40	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	125	0	0
T8	266348	4158	0	0
T9	901070	64	0	0
T10	56682	97	0	0
T11	33439	88	0	0
T12	228767	7	0	0
T13	465194	14	0	0
T14	0	101	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	227330	0	0
T1	22502	40	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	125	0	0
T8	266348	4158	0	0
T9	901070	64	0	0
T10	56682	97	0	0
T11	33439	88	0	0
T12	228767	7	0	0
T13	465194	14	0	0
T14	0	101	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	227330	0	0
T1	22502	40	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	125	0	0
T8	266348	4158	0	0
T9	901070	64	0	0
T10	56682	97	0	0
T11	33439	88	0	0
T12	228767	7	0	0
T13	465194	14	0	0
T14	0	101	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2875520	0	0
T1	22502	299	0	0
T2	6166	65	0	0
T3	79695	1	0	0
T7	197123	39892	0	0
T8	266348	3221	0	0
T9	901070	271	0	0
T10	56682	748	0	0
T11	33439	560	0	0
T12	228767	34	0	0
T13	465194	4984	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	227330	0	0
T1	22502	40	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	125	0	0
T8	266348	4158	0	0
T9	901070	64	0	0
T10	56682	97	0	0
T11	33439	88	0	0
T12	228767	7	0	0
T13	465194	14	0	0
T14	0	101	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	227330	0	0
T1	22502	40	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	125	0	0
T8	266348	4158	0	0
T9	901070	64	0	0
T10	56682	97	0	0
T11	33439	88	0	0
T12	228767	7	0	0
T13	465194	14	0	0
T14	0	101	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	585805	0	0
T1	22502	40	0	0
T2	6166	72	0	0
T3	79695	0	0	0
T7	197123	3987	0	0
T8	266348	5108	0	0
T9	901070	91	0	0
T10	56682	125	0	0
T11	33439	138	0	0
T12	228767	7	0	0
T13	465194	410	0	0
T14	0	107	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	227330	0	0
T1	22502	40	0	0
T2	6166	68	0	0
T3	79695	0	0	0
T7	197123	125	0	0
T8	266348	4158	0	0
T9	901070	64	0	0
T10	56682	97	0	0
T11	33439	88	0	0
T12	228767	7	0	0
T13	465194	14	0	0
T14	0	101	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	229271	0	0
GntImpliesValid_A	413383842	229271	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	229271	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2857294	0	0
ReadyAndValidImplyGrant_A	413383842	229271	0	0
ReqAndReadyImplyGrant_A	413383842	229271	0	0
ReqImpliesValid_A	413383842	627344	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	229271	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229271	0	0
T1	22502	21	0	0
T2	6166	58	0	0
T3	79695	432	0	0
T7	197123	120	0	0
T8	266348	3111	0	0
T9	901070	63	0	0
T10	56682	101	0	0
T11	33439	127	0	0
T12	228767	6	0	0
T13	465194	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229271	0	0
T1	22502	21	0	0
T2	6166	58	0	0
T3	79695	432	0	0
T7	197123	120	0	0
T8	266348	3111	0	0
T9	901070	63	0	0
T10	56682	101	0	0
T11	33439	127	0	0
T12	228767	6	0	0
T13	465194	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229271	0	0
T1	22502	21	0	0
T2	6166	58	0	0
T3	79695	432	0	0
T7	197123	120	0	0
T8	266348	3111	0	0
T9	901070	63	0	0
T10	56682	101	0	0
T11	33439	127	0	0
T12	228767	6	0	0
T13	465194	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2857294	0	0
T1	22502	148	0	0
T2	6166	58	0	0
T3	79695	957	0	0
T7	197123	37825	0	0
T8	266348	2542	0	0
T9	901070	218	0	0
T10	56682	730	0	0
T11	33439	956	0	0
T12	228767	30	0	0
T13	465194	2460	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229271	0	0
T1	22502	21	0	0
T2	6166	58	0	0
T3	79695	432	0	0
T7	197123	120	0	0
T8	266348	3111	0	0
T9	901070	63	0	0
T10	56682	101	0	0
T11	33439	127	0	0
T12	228767	6	0	0
T13	465194	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229271	0	0
T1	22502	21	0	0
T2	6166	58	0	0
T3	79695	432	0	0
T7	197123	120	0	0
T8	266348	3111	0	0
T9	901070	63	0	0
T10	56682	101	0	0
T11	33439	127	0	0
T12	228767	6	0	0
T13	465194	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	627344	0	0
T1	22502	23	0	0
T2	6166	59	0	0
T3	79695	3701	0	0
T7	197123	1433	0	0
T8	266348	3694	0	0
T9	901070	83	0	0
T10	56682	117	0	0
T11	33439	144	0	0
T12	228767	6	0	0
T13	465194	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229271	0	0
T1	22502	21	0	0
T2	6166	58	0	0
T3	79695	432	0	0
T7	197123	120	0	0
T8	266348	3111	0	0
T9	901070	63	0	0
T10	56682	101	0	0
T11	33439	127	0	0
T12	228767	6	0	0
T13	465194	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	223747	0	0
GntImpliesValid_A	413383842	223747	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	223747	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2803172	0	0
ReadyAndValidImplyGrant_A	413383842	223747	0	0
ReqAndReadyImplyGrant_A	413383842	223747	0	0
ReqImpliesValid_A	413383842	593572	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	223747	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223747	0	0
T1	22502	31	0	0
T2	6166	86	0	0
T3	79695	573	0	0
T7	197123	131	0	0
T8	266348	2605	0	0
T9	901070	75	0	0
T10	56682	68	0	0
T11	33439	96	0	0
T12	228767	10	0	0
T13	465194	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223747	0	0
T1	22502	31	0	0
T2	6166	86	0	0
T3	79695	573	0	0
T7	197123	131	0	0
T8	266348	2605	0	0
T9	901070	75	0	0
T10	56682	68	0	0
T11	33439	96	0	0
T12	228767	10	0	0
T13	465194	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223747	0	0
T1	22502	31	0	0
T2	6166	86	0	0
T3	79695	573	0	0
T7	197123	131	0	0
T8	266348	2605	0	0
T9	901070	75	0	0
T10	56682	68	0	0
T11	33439	96	0	0
T12	228767	10	0	0
T13	465194	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2803172	0	0
T1	22502	214	0	0
T2	6166	86	0	0
T3	79695	703	0	0
T7	197123	43031	0	0
T8	266348	2543	0	0
T9	901070	319	0	0
T10	56682	589	0	0
T11	33439	625	0	0
T12	228767	68	0	0
T13	465194	3076	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223747	0	0
T1	22502	31	0	0
T2	6166	86	0	0
T3	79695	573	0	0
T7	197123	131	0	0
T8	266348	2605	0	0
T9	901070	75	0	0
T10	56682	68	0	0
T11	33439	96	0	0
T12	228767	10	0	0
T13	465194	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223747	0	0
T1	22502	31	0	0
T2	6166	86	0	0
T3	79695	573	0	0
T7	197123	131	0	0
T8	266348	2605	0	0
T9	901070	75	0	0
T10	56682	68	0	0
T11	33439	96	0	0
T12	228767	10	0	0
T13	465194	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	593572	0	0
T1	22502	31	0	0
T2	6166	87	0	0
T3	79695	5798	0	0
T7	197123	399	0	0
T8	266348	2680	0	0
T9	901070	81	0	0
T10	56682	68	0	0
T11	33439	146	0	0
T12	228767	10	0	0
T13	465194	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	223747	0	0
T1	22502	31	0	0
T2	6166	86	0	0
T3	79695	573	0	0
T7	197123	131	0	0
T8	266348	2605	0	0
T9	901070	75	0	0
T10	56682	68	0	0
T11	33439	96	0	0
T12	228767	10	0	0
T13	465194	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	240326	0	0
GntImpliesValid_A	413383842	240326	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	240326	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2919213	0	0
ReadyAndValidImplyGrant_A	413383842	240326	0	0
ReqAndReadyImplyGrant_A	413383842	240326	0	0
ReqImpliesValid_A	413383842	615628	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	240326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	240326	0	0
T1	22502	38	0	0
T2	6166	106	0	0
T3	79695	0	0	0
T7	197123	109	0	0
T8	266348	3810	0	0
T9	901070	93	0	0
T10	56682	162	0	0
T11	33439	99	0	0
T12	228767	6	0	0
T13	465194	17	0	0
T14	0	85	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	240326	0	0
T1	22502	38	0	0
T2	6166	106	0	0
T3	79695	0	0	0
T7	197123	109	0	0
T8	266348	3810	0	0
T9	901070	93	0	0
T10	56682	162	0	0
T11	33439	99	0	0
T12	228767	6	0	0
T13	465194	17	0	0
T14	0	85	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	240326	0	0
T1	22502	38	0	0
T2	6166	106	0	0
T3	79695	0	0	0
T7	197123	109	0	0
T8	266348	3810	0	0
T9	901070	93	0	0
T10	56682	162	0	0
T11	33439	99	0	0
T12	228767	6	0	0
T13	465194	17	0	0
T14	0	85	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2919213	0	0
T1	22502	324	0	0
T2	6166	104	0	0
T3	79695	1	0	0
T7	197123	37079	0	0
T8	266348	3241	0	0
T9	901070	371	0	0
T10	56682	1248	0	0
T11	33439	756	0	0
T12	228767	23	0	0
T13	465194	3996	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	240326	0	0
T1	22502	38	0	0
T2	6166	106	0	0
T3	79695	0	0	0
T7	197123	109	0	0
T8	266348	3810	0	0
T9	901070	93	0	0
T10	56682	162	0	0
T11	33439	99	0	0
T12	228767	6	0	0
T13	465194	17	0	0
T14	0	85	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	240326	0	0
T1	22502	38	0	0
T2	6166	106	0	0
T3	79695	0	0	0
T7	197123	109	0	0
T8	266348	3810	0	0
T9	901070	93	0	0
T10	56682	162	0	0
T11	33439	99	0	0
T12	228767	6	0	0
T13	465194	17	0	0
T14	0	85	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	615628	0	0
T1	22502	38	0	0
T2	6166	109	0	0
T3	79695	0	0	0
T7	197123	1994	0	0
T8	266348	4393	0	0
T9	901070	111	0	0
T10	56682	220	0	0
T11	33439	121	0	0
T12	228767	7	0	0
T13	465194	60	0	0
T14	0	86	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	240326	0	0
T1	22502	38	0	0
T2	6166	106	0	0
T3	79695	0	0	0
T7	197123	109	0	0
T8	266348	3810	0	0
T9	901070	93	0	0
T10	56682	162	0	0
T11	33439	99	0	0
T12	228767	6	0	0
T13	465194	17	0	0
T14	0	85	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	216511	0	0
GntImpliesValid_A	413383842	216511	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	216511	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2805770	0	0
ReadyAndValidImplyGrant_A	413383842	216511	0	0
ReqAndReadyImplyGrant_A	413383842	216511	0	0
ReqImpliesValid_A	413383842	609218	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	216511	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	216511	0	0
T1	22502	48	0	0
T2	6166	71	0	0
T3	79695	994	0	0
T7	197123	127	0	0
T8	266348	2665	0	0
T9	901070	84	0	0
T10	56682	90	0	0
T11	33439	117	0	0
T12	228767	8	0	0
T13	465194	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	216511	0	0
T1	22502	48	0	0
T2	6166	71	0	0
T3	79695	994	0	0
T7	197123	127	0	0
T8	266348	2665	0	0
T9	901070	84	0	0
T10	56682	90	0	0
T11	33439	117	0	0
T12	228767	8	0	0
T13	465194	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	216511	0	0
T1	22502	48	0	0
T2	6166	71	0	0
T3	79695	994	0	0
T7	197123	127	0	0
T8	266348	2665	0	0
T9	901070	84	0	0
T10	56682	90	0	0
T11	33439	117	0	0
T12	228767	8	0	0
T13	465194	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2805770	0	0
T1	22502	383	0	0
T2	6166	68	0	0
T3	79695	1685	0	0
T7	197123	45654	0	0
T8	266348	2598	0	0
T9	901070	312	0	0
T10	56682	666	0	0
T11	33439	902	0	0
T12	228767	43	0	0
T13	465194	3493	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	216511	0	0
T1	22502	48	0	0
T2	6166	71	0	0
T3	79695	994	0	0
T7	197123	127	0	0
T8	266348	2665	0	0
T9	901070	84	0	0
T10	56682	90	0	0
T11	33439	117	0	0
T12	228767	8	0	0
T13	465194	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	216511	0	0
T1	22502	48	0	0
T2	6166	71	0	0
T3	79695	994	0	0
T7	197123	127	0	0
T8	266348	2665	0	0
T9	901070	84	0	0
T10	56682	90	0	0
T11	33439	117	0	0
T12	228767	8	0	0
T13	465194	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	609218	0	0
T1	22502	62	0	0
T2	6166	75	0	0
T3	79695	9530	0	0
T7	197123	1169	0	0
T8	266348	2746	0	0
T9	901070	94	0	0
T10	56682	118	0	0
T11	33439	155	0	0
T12	228767	8	0	0
T13	465194	814	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	216511	0	0
T1	22502	48	0	0
T2	6166	71	0	0
T3	79695	994	0	0
T7	197123	127	0	0
T8	266348	2665	0	0
T9	901070	84	0	0
T10	56682	90	0	0
T11	33439	117	0	0
T12	228767	8	0	0
T13	465194	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	229786	0	0
GntImpliesValid_A	413383842	229786	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	229786	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2762050	0	0
ReadyAndValidImplyGrant_A	413383842	229786	0	0
ReqAndReadyImplyGrant_A	413383842	229786	0	0
ReqImpliesValid_A	413383842	633455	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	229786	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229786	0	0
T1	22502	29	0	0
T2	6166	54	0	0
T3	79695	428	0	0
T7	197123	125	0	0
T8	266348	3041	0	0
T9	901070	82	0	0
T10	56682	76	0	0
T11	33439	93	0	0
T12	228767	7	0	0
T13	465194	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229786	0	0
T1	22502	29	0	0
T2	6166	54	0	0
T3	79695	428	0	0
T7	197123	125	0	0
T8	266348	3041	0	0
T9	901070	82	0	0
T10	56682	76	0	0
T11	33439	93	0	0
T12	228767	7	0	0
T13	465194	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229786	0	0
T1	22502	29	0	0
T2	6166	54	0	0
T3	79695	428	0	0
T7	197123	125	0	0
T8	266348	3041	0	0
T9	901070	82	0	0
T10	56682	76	0	0
T11	33439	93	0	0
T12	228767	7	0	0
T13	465194	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2762050	0	0
T1	22502	235	0	0
T2	6166	53	0	0
T3	79695	515	0	0
T7	197123	40154	0	0
T8	266348	2922	0	0
T9	901070	301	0	0
T10	56682	520	0	0
T11	33439	674	0	0
T12	228767	35	0	0
T13	465194	3853	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229786	0	0
T1	22502	29	0	0
T2	6166	54	0	0
T3	79695	428	0	0
T7	197123	125	0	0
T8	266348	3041	0	0
T9	901070	82	0	0
T10	56682	76	0	0
T11	33439	93	0	0
T12	228767	7	0	0
T13	465194	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229786	0	0
T1	22502	29	0	0
T2	6166	54	0	0
T3	79695	428	0	0
T7	197123	125	0	0
T8	266348	3041	0	0
T9	901070	82	0	0
T10	56682	76	0	0
T11	33439	93	0	0
T12	228767	7	0	0
T13	465194	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	633455	0	0
T1	22502	29	0	0
T2	6166	56	0	0
T3	79695	4315	0	0
T7	197123	2317	0	0
T8	266348	3173	0	0
T9	901070	105	0	0
T10	56682	94	0	0
T11	33439	107	0	0
T12	228767	7	0	0
T13	465194	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	229786	0	0
T1	22502	29	0	0
T2	6166	54	0	0
T3	79695	428	0	0
T7	197123	125	0	0
T8	266348	3041	0	0
T9	901070	82	0	0
T10	56682	76	0	0
T11	33439	93	0	0
T12	228767	7	0	0
T13	465194	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	220775	0	0
GntImpliesValid_A	413383842	220775	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	220775	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2768259	0	0
ReadyAndValidImplyGrant_A	413383842	220775	0	0
ReqAndReadyImplyGrant_A	413383842	220775	0	0
ReqImpliesValid_A	413383842	557566	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	220775	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	220775	0	0
T1	22502	35	0	0
T2	6166	60	0	0
T3	79695	534	0	0
T7	197123	119	0	0
T8	266348	4121	0	0
T9	901070	95	0	0
T10	56682	94	0	0
T11	33439	99	0	0
T12	228767	8	0	0
T13	465194	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	220775	0	0
T1	22502	35	0	0
T2	6166	60	0	0
T3	79695	534	0	0
T7	197123	119	0	0
T8	266348	4121	0	0
T9	901070	95	0	0
T10	56682	94	0	0
T11	33439	99	0	0
T12	228767	8	0	0
T13	465194	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	220775	0	0
T1	22502	35	0	0
T2	6166	60	0	0
T3	79695	534	0	0
T7	197123	119	0	0
T8	266348	4121	0	0
T9	901070	95	0	0
T10	56682	94	0	0
T11	33439	99	0	0
T12	228767	8	0	0
T13	465194	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2768259	0	0
T1	22502	292	0	0
T2	6166	57	0	0
T3	79695	580	0	0
T7	197123	42969	0	0
T8	266348	3402	0	0
T9	901070	437	0	0
T10	56682	720	0	0
T11	33439	793	0	0
T12	228767	41	0	0
T13	465194	4034	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	220775	0	0
T1	22502	35	0	0
T2	6166	60	0	0
T3	79695	534	0	0
T7	197123	119	0	0
T8	266348	4121	0	0
T9	901070	95	0	0
T10	56682	94	0	0
T11	33439	99	0	0
T12	228767	8	0	0
T13	465194	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	220775	0	0
T1	22502	35	0	0
T2	6166	60	0	0
T3	79695	534	0	0
T7	197123	119	0	0
T8	266348	4121	0	0
T9	901070	95	0	0
T10	56682	94	0	0
T11	33439	99	0	0
T12	228767	8	0	0
T13	465194	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	557566	0	0
T1	22502	37	0	0
T2	6166	64	0	0
T3	79695	5618	0	0
T7	197123	2294	0	0
T8	266348	4854	0	0
T9	901070	119	0	0
T10	56682	116	0	0
T11	33439	121	0	0
T12	228767	8	0	0
T13	465194	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	220775	0	0
T1	22502	35	0	0
T2	6166	60	0	0
T3	79695	534	0	0
T7	197123	119	0	0
T8	266348	4121	0	0
T9	901070	95	0	0
T10	56682	94	0	0
T11	33439	99	0	0
T12	228767	8	0	0
T13	465194	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	219046	0	0
GntImpliesValid_A	413383842	219046	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	219046	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2787489	0	0
ReadyAndValidImplyGrant_A	413383842	219046	0	0
ReqAndReadyImplyGrant_A	413383842	219046	0	0
ReqImpliesValid_A	413383842	572582	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	219046	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	219046	0	0
T1	22502	42	0	0
T2	6166	56	0	0
T3	79695	0	0	0
T7	197123	133	0	0
T8	266348	3249	0	0
T9	901070	82	0	0
T10	56682	90	0	0
T11	33439	98	0	0
T12	228767	5	0	0
T13	465194	13	0	0
T14	0	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	219046	0	0
T1	22502	42	0	0
T2	6166	56	0	0
T3	79695	0	0	0
T7	197123	133	0	0
T8	266348	3249	0	0
T9	901070	82	0	0
T10	56682	90	0	0
T11	33439	98	0	0
T12	228767	5	0	0
T13	465194	13	0	0
T14	0	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	219046	0	0
T1	22502	42	0	0
T2	6166	56	0	0
T3	79695	0	0	0
T7	197123	133	0	0
T8	266348	3249	0	0
T9	901070	82	0	0
T10	56682	90	0	0
T11	33439	98	0	0
T12	228767	5	0	0
T13	465194	13	0	0
T14	0	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2787489	0	0
T1	22502	300	0	0
T2	6166	54	0	0
T3	79695	1	0	0
T7	197123	43079	0	0
T8	266348	2962	0	0
T9	901070	349	0	0
T10	56682	669	0	0
T11	33439	685	0	0
T12	228767	28	0	0
T13	465194	4952	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	219046	0	0
T1	22502	42	0	0
T2	6166	56	0	0
T3	79695	0	0	0
T7	197123	133	0	0
T8	266348	3249	0	0
T9	901070	82	0	0
T10	56682	90	0	0
T11	33439	98	0	0
T12	228767	5	0	0
T13	465194	13	0	0
T14	0	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	219046	0	0
T1	22502	42	0	0
T2	6166	56	0	0
T3	79695	0	0	0
T7	197123	133	0	0
T8	266348	3249	0	0
T9	901070	82	0	0
T10	56682	90	0	0
T11	33439	98	0	0
T12	228767	5	0	0
T13	465194	13	0	0
T14	0	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	572582	0	0
T1	22502	42	0	0
T2	6166	59	0	0
T3	79695	0	0	0
T7	197123	3541	0	0
T8	266348	3550	0	0
T9	901070	91	0	0
T10	56682	125	0	0
T11	33439	154	0	0
T12	228767	5	0	0
T13	465194	659	0	0
T14	0	135	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	219046	0	0
T1	22502	42	0	0
T2	6166	56	0	0
T3	79695	0	0	0
T7	197123	133	0	0
T8	266348	3249	0	0
T9	901070	82	0	0
T10	56682	90	0	0
T11	33439	98	0	0
T12	228767	5	0	0
T13	465194	13	0	0
T14	0	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	231483	0	0
GntImpliesValid_A	413383842	231483	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	231483	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	2831460	0	0
ReadyAndValidImplyGrant_A	413383842	231483	0	0
ReqAndReadyImplyGrant_A	413383842	231483	0	0
ReqImpliesValid_A	413383842	630985	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	0	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	231483	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	231483	0	0
T1	22502	29	0	0
T2	6166	63	0	0
T3	79695	0	0	0
T7	197123	142	0	0
T8	266348	3547	0	0
T9	901070	63	0	0
T10	56682	83	0	0
T11	33439	110	0	0
T12	228767	9	0	0
T13	465194	19	0	0
T14	0	89	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	231483	0	0
T1	22502	29	0	0
T2	6166	63	0	0
T3	79695	0	0	0
T7	197123	142	0	0
T8	266348	3547	0	0
T9	901070	63	0	0
T10	56682	83	0	0
T11	33439	110	0	0
T12	228767	9	0	0
T13	465194	19	0	0
T14	0	89	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	231483	0	0
T1	22502	29	0	0
T2	6166	63	0	0
T3	79695	0	0	0
T7	197123	142	0	0
T8	266348	3547	0	0
T9	901070	63	0	0
T10	56682	83	0	0
T11	33439	110	0	0
T12	228767	9	0	0
T13	465194	19	0	0
T14	0	89	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2831460	0	0
T1	22502	219	0	0
T2	6166	62	0	0
T3	79695	1	0	0
T7	197123	48010	0	0
T8	266348	2979	0	0
T9	901070	294	0	0
T10	56682	709	0	0
T11	33439	772	0	0
T12	228767	28	0	0
T13	465194	6624	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	231483	0	0
T1	22502	29	0	0
T2	6166	63	0	0
T3	79695	0	0	0
T7	197123	142	0	0
T8	266348	3547	0	0
T9	901070	63	0	0
T10	56682	83	0	0
T11	33439	110	0	0
T12	228767	9	0	0
T13	465194	19	0	0
T14	0	89	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	231483	0	0
T1	22502	29	0	0
T2	6166	63	0	0
T3	79695	0	0	0
T7	197123	142	0	0
T8	266348	3547	0	0
T9	901070	63	0	0
T10	56682	83	0	0
T11	33439	110	0	0
T12	228767	9	0	0
T13	465194	19	0	0
T14	0	89	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	630985	0	0
T1	22502	29	0	0
T2	6166	65	0	0
T3	79695	0	0	0
T7	197123	2508	0	0
T8	266348	4129	0	0
T9	901070	65	0	0
T10	56682	92	0	0
T11	33439	140	0	0
T12	228767	9	0	0
T13	465194	247	0	0
T14	0	94	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	231483	0	0
T1	22502	29	0	0
T2	6166	63	0	0
T3	79695	0	0	0
T7	197123	142	0	0
T8	266348	3547	0	0
T9	901070	63	0	0
T10	56682	83	0	0
T11	33439	110	0	0
T12	228767	9	0	0
T13	465194	19	0	0
T14	0	89	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	910898	0	0
GntImpliesValid_A	413383842	910898	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	910898	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	10946299	0	0
ReadyAndValidImplyGrant_A	413383842	910898	0	0
ReqAndReadyImplyGrant_A	413383842	910898	0	0
ReqImpliesValid_A	413383842	2299801	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	20187	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	910898	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	910898	0	0
T1	22502	132	0	0
T2	6166	233	0	0
T3	79695	604	0	0
T7	197123	516	0	0
T8	266348	15255	0	0
T9	901070	317	0	0
T10	56682	447	0	0
T11	33439	367	0	0
T12	228767	47	0	0
T13	465194	56	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	910898	0	0
T1	22502	132	0	0
T2	6166	233	0	0
T3	79695	604	0	0
T7	197123	516	0	0
T8	266348	15255	0	0
T9	901070	317	0	0
T10	56682	447	0	0
T11	33439	367	0	0
T12	228767	47	0	0
T13	465194	56	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	910898	0	0
T1	22502	132	0	0
T2	6166	233	0	0
T3	79695	604	0	0
T7	197123	516	0	0
T8	266348	15255	0	0
T9	901070	317	0	0
T10	56682	447	0	0
T11	33439	367	0	0
T12	228767	47	0	0
T13	465194	56	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	10946299	0	0
T1	22502	858	0	0
T2	6166	1	0	0
T3	79695	3934	0	0
T7	197123	163812	0	0
T8	266348	14	0	0
T9	901070	1055	0	0
T10	56682	2785	0	0
T11	33439	2005	0	0
T12	228767	164	0	0
T13	465194	19316	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	910898	0	0
T1	22502	132	0	0
T2	6166	233	0	0
T3	79695	604	0	0
T7	197123	516	0	0
T8	266348	15255	0	0
T9	901070	317	0	0
T10	56682	447	0	0
T11	33439	367	0	0
T12	228767	47	0	0
T13	465194	56	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	910898	0	0
T1	22502	132	0	0
T2	6166	233	0	0
T3	79695	604	0	0
T7	197123	516	0	0
T8	266348	15255	0	0
T9	901070	317	0	0
T10	56682	447	0	0
T11	33439	367	0	0
T12	228767	47	0	0
T13	465194	56	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	2299801	0	0
T1	22502	151	0	0
T2	6166	233	0	0
T3	79695	947	0	0
T7	197123	14897	0	0
T8	266348	15255	0	0
T9	901070	385	0	0
T10	56682	646	0	0
T11	33439	626	0	0
T12	228767	61	0	0
T13	465194	2191	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	20187	0	900
T8	266348	599	0	1
T9	901070	0	0	1
T10	56682	0	0	1
T11	33439	1	0	1
T12	228767	0	0	1
T13	465194	0	0	1
T14	6449	5	0	1
T15	118959	0	0	1
T16	222082	1	0	1
T17	632703	1	0	1
T18	0	2	0	0
T20	0	2	0	0
T21	0	116	0	0
T22	0	14	0	0
T23	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	910898	0	0
T1	22502	132	0	0
T2	6166	233	0	0
T3	79695	604	0	0
T7	197123	516	0	0
T8	266348	15255	0	0
T9	901070	317	0	0
T10	56682	447	0	0
T11	33439	367	0	0
T12	228767	47	0	0
T13	465194	56	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413383842	413255738	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413383842	908780	0	0
GntImpliesValid_A	413383842	908780	0	0
GrantKnown_A	413383842	413255738	0	0
IdxKnown_A	413383842	413255738	0	0
IndexIsCorrect_A	413383842	908780	0	0
LockArbDecision_A	413383842	0	0	0
NoReadyValidNoGrant_A	413383842	346158408	0	0
ReadyAndValidImplyGrant_A	413383842	908780	0	0
ReqAndReadyImplyGrant_A	413383842	908780	0	0
ReqImpliesValid_A	413383842	12733420	0	0
ReqStaysHighUntilGranted0_M	413383842	0	0	0
RoundRobin_A	413383842	28694	0	900
ValidKnown_A	413383842	413255738	0	0
gen_data_port_assertion.DataFlow_A	413383842	908780	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	908780	0	0
T1	22502	154	0	0
T2	6166	236	0	0
T3	79695	624	0	0
T7	197123	568	0	0
T8	266348	13162	0	0
T9	901070	319	0	0
T10	56682	438	0	0
T11	33439	297	0	0
T12	228767	57	0	0
T13	465194	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	908780	0	0
T1	22502	154	0	0
T2	6166	236	0	0
T3	79695	624	0	0
T7	197123	568	0	0
T8	266348	13162	0	0
T9	901070	319	0	0
T10	56682	438	0	0
T11	33439	297	0	0
T12	228767	57	0	0
T13	465194	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	908780	0	0
T1	22502	154	0	0
T2	6166	236	0	0
T3	79695	624	0	0
T7	197123	568	0	0
T8	266348	13162	0	0
T9	901070	319	0	0
T10	56682	438	0	0
T11	33439	297	0	0
T12	228767	57	0	0
T13	465194	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	346158408	0	0
T1	22502	19314	0	0
T2	6166	1	0	0
T3	79695	68161	0	0
T7	197123	168887	0	0
T8	266348	1	0	0
T9	901070	749467	0	0
T10	56682	48500	0	0
T11	33439	28352	0	0
T12	228767	190123	0	0
T13	465194	441726	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	908780	0	0
T1	22502	154	0	0
T2	6166	236	0	0
T3	79695	624	0	0
T7	197123	568	0	0
T8	266348	13162	0	0
T9	901070	319	0	0
T10	56682	438	0	0
T11	33439	297	0	0
T12	228767	57	0	0
T13	465194	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	908780	0	0
T1	22502	154	0	0
T2	6166	236	0	0
T3	79695	624	0	0
T7	197123	568	0	0
T8	266348	13162	0	0
T9	901070	319	0	0
T10	56682	438	0	0
T11	33439	297	0	0
T12	228767	57	0	0
T13	465194	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	12733420	0	0
T1	22502	1244	0	0
T2	6166	236	0	0
T3	79695	4833	0	0
T7	197123	188654	0	0
T8	266348	13162	0	0
T9	901070	1564	0	0
T10	56682	3382	0	0
T11	33439	2398	0	0
T12	228767	256	0	0
T13	465194	11850	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	28694	0	900
T8	266348	327	0	1
T9	901070	1	0	1
T10	56682	3	0	1
T11	33439	1	0	1
T12	228767	0	0	1
T13	465194	0	0	1
T14	6449	4	0	1
T15	118959	1	0	1
T16	222082	1	0	1
T17	632703	5	0	1
T18	0	4	0	0
T19	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	413255738	0	0
T1	22502	22464	0	0
T2	6166	6124	0	0
T3	79695	79607	0	0
T7	197123	197121	0	0
T8	266348	265371	0	0
T9	901070	901043	0	0
T10	56682	56629	0	0
T11	33439	33412	0	0
T12	228767	228698	0	0
T13	465194	465122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413383842	908780	0	0
T1	22502	154	0	0
T2	6166	236	0	0
T3	79695	624	0	0
T7	197123	568	0	0
T8	266348	13162	0	0
T9	901070	319	0	0
T10	56682	438	0	0
T11	33439	297	0	0
T12	228767	57	0	0
T13	465194	43	0	0