Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1487672	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

236336

1

T1

29

T2

250

T3

205

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	586210	1			T1	60		T2	629		T3	506
values[0x0]	552868	1			T1	57		T2	608		T3	521
values[0x1]	584930	1			T1	56		T2	567		T3	472

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1150493	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

573515

1

T1

59

T2

590

T3

508

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27084	1			T1	5		T2	12		T3	19
valid_sources[0x01]	27544	1			T2	16		T3	19		T9	4
valid_sources[0x02]	26921	1			T1	2		T2	18		T3	26
valid_sources[0x03]	27770	1			T1	1		T2	54		T3	31
valid_sources[0x04]	26390	1			T1	1		T2	21		T3	24
valid_sources[0x05]	26279	1			T1	2		T2	24		T3	29
valid_sources[0x06]	27529	1			T1	4		T2	38		T3	22
valid_sources[0x07]	26080	1			T1	1		T2	11		T3	27
valid_sources[0x08]	26688	1			T1	2		T2	31		T3	21
valid_sources[0x09]	26294	1			T1	3		T2	24		T3	26
valid_sources[0x0a]	25903	1			T1	2		T2	35		T3	26
valid_sources[0x0b]	27205	1			T2	30		T3	25		T7	2
valid_sources[0x0c]	26375	1			T1	6		T2	9		T3	28
valid_sources[0x0d]	26043	1			T1	3		T2	37		T3	24
valid_sources[0x0e]	27129	1			T1	2		T2	23		T3	22
valid_sources[0x0f]	26944	1			T1	7		T2	34		T3	16
valid_sources[0x10]	27972	1			T1	1		T2	22		T3	20
valid_sources[0x11]	26790	1			T1	5		T2	24		T3	26
valid_sources[0x12]	25811	1			T1	2		T2	24		T3	17
valid_sources[0x13]	27651	1			T1	4		T2	25		T3	21
valid_sources[0x14]	26684	1			T1	3		T2	37		T3	24
valid_sources[0x15]	28178	1			T1	1		T2	52		T3	22
valid_sources[0x16]	25951	1			T1	4		T2	35		T3	24
valid_sources[0x17]	26821	1			T1	1		T2	29		T3	30
valid_sources[0x18]	25952	1			T1	3		T2	41		T3	19
valid_sources[0x19]	26881	1			T2	30		T3	20		T8	1
valid_sources[0x1a]	27132	1			T1	10		T2	19		T3	21
valid_sources[0x1b]	28258	1			T1	2		T2	48		T3	25
valid_sources[0x1c]	27125	1			T1	1		T2	48		T3	19
valid_sources[0x1d]	28360	1			T2	26		T3	22		T7	3
valid_sources[0x1e]	27217	1			T1	2		T2	29		T3	26
valid_sources[0x1f]	27149	1			T2	44		T3	33		T8	1
valid_sources[0x20]	27070	1			T1	4		T2	30		T3	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24889

1

T1

6

T2

36

T3

11

values[0x0]

all_enables

biggest_size

186367

1

T1

23

T2

194

T3

176

values[0x1]

all_enables

biggest_size

25080

1

T2

20

T3

18

T9

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1506145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244036

1

T1

22

T2

268

T3

224

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	600507	1			T1	64		T2	609		T3	472
values[0x0]	550915	1			T1	57		T2	583		T3	469
values[0x1]	598759	1			T1	71		T2	599		T3	533

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1155753	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

594428

1

T1

56

T2

643

T3

511

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27363	1			T2	27		T3	26		T7	4
valid_sources[0x01]	27397	1			T2	26		T3	28		T7	2
valid_sources[0x02]	26825	1			T2	31		T3	25		T9	30
valid_sources[0x03]	27196	1			T2	36		T3	7		T9	4
valid_sources[0x04]	27405	1			T1	5		T2	30		T3	34
valid_sources[0x05]	27442	1			T1	1		T2	42		T3	12
valid_sources[0x06]	26505	1			T1	5		T2	49		T3	23
valid_sources[0x07]	27183	1			T1	1		T2	18		T3	17
valid_sources[0x08]	27342	1			T1	4		T2	43		T3	20
valid_sources[0x09]	27186	1			T1	5		T2	26		T3	10
valid_sources[0x0a]	27473	1			T1	1		T2	34		T3	7
valid_sources[0x0b]	27733	1			T1	6		T2	23		T3	18
valid_sources[0x0c]	27239	1			T1	3		T2	28		T3	9
valid_sources[0x0d]	27101	1			T1	1		T2	28		T3	7
valid_sources[0x0e]	27687	1			T1	1		T2	32		T3	27
valid_sources[0x0f]	27791	1			T1	9		T2	21		T3	25
valid_sources[0x10]	26852	1			T2	14		T3	39		T7	2
valid_sources[0x11]	27688	1			T1	6		T2	34		T3	61
valid_sources[0x12]	26917	1			T1	4		T2	43		T3	9
valid_sources[0x13]	28255	1			T1	4		T2	31		T3	31
valid_sources[0x14]	27908	1			T1	4		T2	43		T3	9
valid_sources[0x15]	28326	1			T1	4		T2	37		T3	39
valid_sources[0x16]	27385	1			T1	5		T2	23		T3	14
valid_sources[0x17]	27240	1			T1	2		T2	39		T3	23
valid_sources[0x18]	27275	1			T1	1		T2	29		T3	20
valid_sources[0x19]	27246	1			T1	1		T2	34		T3	37
valid_sources[0x1a]	27166	1			T1	3		T2	24		T3	22
valid_sources[0x1b]	27811	1			T2	32		T3	19		T7	3
valid_sources[0x1c]	28250	1			T2	33		T3	36		T7	5
valid_sources[0x1d]	27216	1			T1	4		T2	18		T3	13
valid_sources[0x1e]	27688	1			T1	1		T2	21		T3	37
valid_sources[0x1f]	27610	1			T1	3		T2	30		T3	34
valid_sources[0x20]	27566	1			T1	1		T2	25		T3	42

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25705

1

T1

2

T2

22

T3

29

values[0x0]

all_enables

biggest_size

192804

1

T1

17

T2

219

T3

177

values[0x1]

all_enables

biggest_size

25527

1

T1

3

T2

27

T3

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1494999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238833

1

T1

33

T2

231

T3

173

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	588186	1			T1	60		T2	572		T3	479
values[0x0]	557722	1			T1	65		T2	511		T3	445
values[0x1]	587924	1			T1	66		T2	517		T3	451

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1155947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

577885

1

T1

69

T2

533

T3

424

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26854	1			T2	27		T3	13		T9	18
valid_sources[0x01]	27099	1			T2	33		T3	22		T9	16
valid_sources[0x02]	26841	1			T2	12		T3	16		T8	4
valid_sources[0x03]	27335	1			T1	12		T2	22		T3	20
valid_sources[0x04]	26788	1			T2	33		T3	24		T9	21
valid_sources[0x05]	26861	1			T1	10		T2	9		T3	16
valid_sources[0x06]	26643	1			T2	22		T3	18		T9	4
valid_sources[0x07]	26818	1			T1	2		T2	37		T3	20
valid_sources[0x08]	26781	1			T2	16		T3	28		T9	18
valid_sources[0x09]	27471	1			T2	25		T3	17		T9	5
valid_sources[0x0a]	27565	1			T2	25		T3	30		T9	11
valid_sources[0x0b]	27303	1			T2	15		T3	19		T9	6
valid_sources[0x0c]	27244	1			T1	2		T2	31		T3	21
valid_sources[0x0d]	27327	1			T2	18		T3	19		T8	1
valid_sources[0x0e]	27337	1			T2	24		T3	17		T9	16
valid_sources[0x0f]	27616	1			T2	19		T3	22		T8	1
valid_sources[0x10]	26510	1			T1	14		T2	29		T3	17
valid_sources[0x11]	27604	1			T2	28		T3	21		T7	3
valid_sources[0x12]	27230	1			T2	38		T3	24		T8	1
valid_sources[0x13]	27535	1			T2	42		T3	27		T7	2
valid_sources[0x14]	26769	1			T2	30		T3	25		T7	1
valid_sources[0x15]	27209	1			T1	9		T2	20		T3	19
valid_sources[0x16]	27062	1			T2	19		T3	21		T9	15
valid_sources[0x17]	26408	1			T2	26		T3	29		T9	33
valid_sources[0x18]	26281	1			T2	28		T3	21		T9	5
valid_sources[0x19]	27141	1			T2	22		T3	18		T8	2
valid_sources[0x1a]	27446	1			T1	13		T2	25		T3	25
valid_sources[0x1b]	27533	1			T1	28		T2	39		T3	17
valid_sources[0x1c]	28405	1			T1	42		T2	16		T3	18
valid_sources[0x1d]	27539	1			T2	44		T3	22		T9	25
valid_sources[0x1e]	27560	1			T2	26		T3	22		T9	21
valid_sources[0x1f]	26453	1			T2	26		T3	24		T9	18
valid_sources[0x20]	26958	1			T2	29		T3	22		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25036

1

T1

3

T2

28

T3

13

values[0x0]

all_enables

biggest_size

188648

1

T1

26

T2

181

T3

148

values[0x1]

all_enables

biggest_size

25149

1

T1

4

T2

22

T3

12