Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
142862 |
1 |
|
|
T1 |
6 |
|
T2 |
117 |
|
T7 |
6 |
auto[1] |
75153 |
1 |
|
|
T1 |
14 |
|
T2 |
20 |
|
T7 |
5 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
53241 |
1 |
|
|
T1 |
7 |
|
T2 |
46 |
|
T7 |
2 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
154203 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63812 |
1 |
|
|
T1 |
6 |
|
T2 |
45 |
|
T7 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16343 |
1 |
|
|
T1 |
3 |
|
T2 |
15 |
|
T7 |
1 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
130042 |
1 |
|
|
T1 |
13 |
|
T2 |
80 |
|
T8 |
7 |
auto[1] |
74172 |
1 |
|
|
T1 |
6 |
|
T2 |
59 |
|
T7 |
8 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
52223 |
1 |
|
|
T1 |
1 |
|
T2 |
52 |
|
T8 |
3 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
143417 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
60797 |
1 |
|
|
T1 |
5 |
|
T2 |
42 |
|
T7 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16291 |
1 |
|
|
T1 |
1 |
|
T2 |
18 |
|
T9 |
5 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
135506 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T7 |
3 |
auto[1] |
80567 |
1 |
|
|
T1 |
7 |
|
T2 |
55 |
|
T7 |
6 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
53418 |
1 |
|
|
T1 |
3 |
|
T2 |
47 |
|
T7 |
3 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
152746 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63327 |
1 |
|
|
T1 |
8 |
|
T2 |
47 |
|
T7 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16322 |
1 |
|
|
T1 |
2 |
|
T2 |
14 |
|
T7 |
1 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
138583 |
1 |
|
|
T1 |
9 |
|
T2 |
97 |
|
T3 |
172 |
auto[1] |
76771 |
1 |
|
|
T1 |
15 |
|
T2 |
63 |
|
T3 |
363 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
53746 |
1 |
|
|
T1 |
5 |
|
T2 |
61 |
|
T3 |
167 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
152364 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
62990 |
1 |
|
|
T1 |
9 |
|
T2 |
47 |
|
T3 |
170 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16498 |
1 |
|
|
T2 |
19 |
|
T3 |
53 |
|
T8 |
2 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
137110 |
1 |
|
|
T1 |
5 |
|
T2 |
129 |
|
T7 |
8 |
auto[1] |
79601 |
1 |
|
|
T1 |
11 |
|
T2 |
21 |
|
T7 |
4 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
54091 |
1 |
|
|
T1 |
4 |
|
T2 |
56 |
|
T7 |
5 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
152786 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63925 |
1 |
|
|
T1 |
7 |
|
T2 |
53 |
|
T7 |
6 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16739 |
1 |
|
|
T2 |
18 |
|
T7 |
2 |
|
T8 |
1 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
132422 |
1 |
|
|
T1 |
10 |
|
T2 |
105 |
|
T3 |
214 |
auto[1] |
80546 |
1 |
|
|
T2 |
36 |
|
T3 |
238 |
|
T7 |
3 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
52378 |
1 |
|
|
T1 |
5 |
|
T2 |
48 |
|
T3 |
159 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
150432 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
62536 |
1 |
|
|
T1 |
4 |
|
T2 |
45 |
|
T3 |
142 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16114 |
1 |
|
|
T1 |
3 |
|
T2 |
11 |
|
T3 |
47 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
552590 |
1 |
|
|
T1 |
47 |
|
T2 |
519 |
|
T3 |
258 |
auto[1] |
309949 |
1 |
|
|
T1 |
17 |
|
T2 |
58 |
|
T3 |
109 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
217534 |
1 |
|
|
T1 |
22 |
|
T2 |
194 |
|
T3 |
119 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
602221 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
260318 |
1 |
|
|
T1 |
19 |
|
T2 |
205 |
|
T3 |
115 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
68627 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
39 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
144727 |
1 |
|
|
T1 |
18 |
|
T2 |
80 |
|
T7 |
9 |
auto[1] |
71428 |
1 |
|
|
T1 |
2 |
|
T2 |
59 |
|
T7 |
5 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
54512 |
1 |
|
|
T1 |
5 |
|
T2 |
52 |
|
T7 |
10 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
152209 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63946 |
1 |
|
|
T1 |
8 |
|
T2 |
49 |
|
T7 |
4 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16932 |
1 |
|
|
T1 |
3 |
|
T2 |
18 |
|
T7 |
3 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
134729 |
1 |
|
|
T1 |
13 |
|
T2 |
118 |
|
T7 |
7 |
auto[1] |
75634 |
1 |
|
|
T1 |
2 |
|
T2 |
20 |
|
T7 |
6 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
52753 |
1 |
|
|
T1 |
4 |
|
T2 |
48 |
|
T7 |
5 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
146934 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63429 |
1 |
|
|
T1 |
5 |
|
T2 |
50 |
|
T7 |
6 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16520 |
1 |
|
|
T1 |
2 |
|
T2 |
22 |
|
T7 |
3 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
141492 |
1 |
|
|
T1 |
5 |
|
T2 |
72 |
|
T3 |
367 |
auto[1] |
74059 |
1 |
|
|
T1 |
6 |
|
T2 |
60 |
|
T3 |
74 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
55227 |
1 |
|
|
T1 |
4 |
|
T2 |
43 |
|
T3 |
158 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
151720 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63831 |
1 |
|
|
T1 |
4 |
|
T2 |
40 |
|
T3 |
156 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17070 |
1 |
|
|
T1 |
1 |
|
T2 |
18 |
|
T3 |
56 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
137406 |
1 |
|
|
T1 |
12 |
|
T2 |
121 |
|
T7 |
9 |
auto[1] |
70371 |
1 |
|
|
T2 |
14 |
|
T7 |
3 |
|
T8 |
17 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
51918 |
1 |
|
|
T1 |
4 |
|
T2 |
51 |
|
T7 |
5 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
144679 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63098 |
1 |
|
|
T1 |
2 |
|
T2 |
45 |
|
T7 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16344 |
1 |
|
|
T1 |
1 |
|
T2 |
11 |
|
T7 |
2 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
142547 |
1 |
|
|
T1 |
14 |
|
T2 |
79 |
|
T7 |
5 |
auto[1] |
77489 |
1 |
|
|
T1 |
14 |
|
T2 |
52 |
|
T7 |
4 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
55411 |
1 |
|
|
T1 |
6 |
|
T2 |
35 |
|
T7 |
5 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
153183 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
66853 |
1 |
|
|
T1 |
13 |
|
T2 |
38 |
|
T8 |
11 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17613 |
1 |
|
|
T1 |
2 |
|
T2 |
12 |
|
T8 |
1 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
142120 |
1 |
|
|
T1 |
6 |
|
T2 |
109 |
|
T7 |
7 |
auto[1] |
69428 |
1 |
|
|
T1 |
14 |
|
T2 |
48 |
|
T7 |
3 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
53533 |
1 |
|
|
T1 |
7 |
|
T2 |
58 |
|
T7 |
3 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
147360 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
64188 |
1 |
|
|
T1 |
6 |
|
T2 |
60 |
|
T7 |
5 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16944 |
1 |
|
|
T1 |
1 |
|
T2 |
25 |
|
T7 |
1 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
143357 |
1 |
|
|
T1 |
13 |
|
T2 |
145 |
|
T7 |
11 |
auto[1] |
76190 |
1 |
|
|
T1 |
5 |
|
T2 |
7 |
|
T7 |
5 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
54353 |
1 |
|
|
T1 |
9 |
|
T2 |
51 |
|
T7 |
5 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
154845 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
64702 |
1 |
|
|
T1 |
6 |
|
T2 |
59 |
|
T7 |
5 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16626 |
1 |
|
|
T1 |
3 |
|
T2 |
20 |
|
T7 |
2 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
548243 |
1 |
|
|
T1 |
22 |
|
T2 |
480 |
|
T3 |
187 |
auto[1] |
308979 |
1 |
|
|
T1 |
29 |
|
T2 |
118 |
|
T3 |
188 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
214933 |
1 |
|
|
T1 |
17 |
|
T2 |
209 |
|
T3 |
119 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
598138 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
259084 |
1 |
|
|
T1 |
16 |
|
T2 |
217 |
|
T3 |
132 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
67926 |
1 |
|
|
T1 |
6 |
|
T2 |
70 |
|
T3 |
43 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
132119 |
1 |
|
|
T1 |
6 |
|
T2 |
102 |
|
T7 |
11 |
auto[1] |
73497 |
1 |
|
|
T1 |
3 |
|
T2 |
32 |
|
T8 |
4 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
50252 |
1 |
|
|
T1 |
6 |
|
T2 |
47 |
|
T7 |
3 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
144885 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
60731 |
1 |
|
|
T1 |
2 |
|
T2 |
40 |
|
T7 |
4 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
15638 |
1 |
|
|
T1 |
1 |
|
T2 |
18 |
|
T8 |
1 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
554974 |
1 |
|
|
T1 |
58 |
|
T2 |
409 |
|
T3 |
234 |
auto[1] |
311890 |
1 |
|
|
T1 |
15 |
|
T2 |
197 |
|
T3 |
103 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
219856 |
1 |
|
|
T1 |
25 |
|
T2 |
207 |
|
T3 |
112 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
604120 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
262744 |
1 |
|
|
T1 |
22 |
|
T2 |
207 |
|
T3 |
123 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
69724 |
1 |
|
|
T1 |
9 |
|
T2 |
66 |
|
T3 |
38 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
146087 |
1 |
|
|
T1 |
10 |
|
T2 |
153 |
|
T7 |
3 |
auto[1] |
77997 |
1 |
|
|
T1 |
1 |
|
T2 |
16 |
|
T7 |
4 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
55714 |
1 |
|
|
T1 |
8 |
|
T2 |
59 |
|
T7 |
4 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
157938 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
66146 |
1 |
|
|
T1 |
4 |
|
T2 |
57 |
|
T7 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17366 |
1 |
|
|
T1 |
2 |
|
T2 |
23 |
|
T7 |
2 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
152825 |
1 |
|
|
T1 |
2 |
|
T2 |
81 |
|
T3 |
229 |
auto[1] |
83636 |
1 |
|
|
T1 |
8 |
|
T2 |
66 |
|
T3 |
206 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
57783 |
1 |
|
|
T1 |
4 |
|
T2 |
52 |
|
T3 |
150 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
165467 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
70994 |
1 |
|
|
T1 |
2 |
|
T2 |
43 |
|
T3 |
142 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
18325 |
1 |
|
|
T1 |
1 |
|
T2 |
16 |
|
T3 |
55 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
136641 |
1 |
|
|
T1 |
5 |
|
T2 |
112 |
|
T7 |
7 |
auto[1] |
73023 |
1 |
|
|
T1 |
1 |
|
T2 |
20 |
|
T7 |
6 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
51863 |
1 |
|
|
T1 |
1 |
|
T2 |
43 |
|
T7 |
5 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
147904 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
61760 |
1 |
|
|
T2 |
30 |
|
T7 |
2 |
|
T8 |
13 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16042 |
1 |
|
|
T2 |
8 |
|
T8 |
1 |
|
T9 |
4 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
149480 |
1 |
|
|
T1 |
8 |
|
T2 |
128 |
|
T7 |
3 |
auto[1] |
76670 |
1 |
|
|
T1 |
10 |
|
T2 |
7 |
|
T7 |
10 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
57473 |
1 |
|
|
T1 |
7 |
|
T2 |
51 |
|
T7 |
5 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
158875 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
67275 |
1 |
|
|
T1 |
7 |
|
T2 |
47 |
|
T7 |
5 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17905 |
1 |
|
|
T1 |
2 |
|
T2 |
24 |
|
T7 |
2 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
566063 |
1 |
|
|
T1 |
35 |
|
T2 |
563 |
|
T3 |
190 |
auto[1] |
290883 |
1 |
|
|
T1 |
26 |
|
T2 |
11 |
|
T3 |
205 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
217888 |
1 |
|
|
T1 |
22 |
|
T2 |
205 |
|
T3 |
122 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
597164 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
259782 |
1 |
|
|
T1 |
22 |
|
T2 |
211 |
|
T3 |
141 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
69007 |
1 |
|
|
T1 |
7 |
|
T2 |
73 |
|
T3 |
42 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
138589 |
1 |
|
|
T1 |
7 |
|
T2 |
47 |
|
T3 |
244 |
auto[1] |
72097 |
1 |
|
|
T1 |
3 |
|
T2 |
77 |
|
T3 |
250 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
52892 |
1 |
|
|
T1 |
5 |
|
T2 |
44 |
|
T3 |
171 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
148422 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
62264 |
1 |
|
|
T1 |
4 |
|
T2 |
40 |
|
T3 |
169 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16475 |
1 |
|
|
T1 |
2 |
|
T2 |
14 |
|
T3 |
68 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
137177 |
1 |
|
|
T1 |
11 |
|
T2 |
44 |
|
T3 |
387 |
auto[1] |
71027 |
1 |
|
|
T1 |
1 |
|
T2 |
103 |
|
T3 |
130 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
52980 |
1 |
|
|
T1 |
3 |
|
T2 |
51 |
|
T3 |
180 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
144847 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63357 |
1 |
|
|
T1 |
3 |
|
T2 |
49 |
|
T3 |
153 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16812 |
1 |
|
|
T1 |
1 |
|
T2 |
15 |
|
T3 |
45 |