Module Definition
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Module Instance : tb.dut.u_asf_35.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_asf_35


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
sync_rptr 100.00 100.00 100.00
sync_wptr 100.00 100.00 100.00



Module Instance : tb.dut.u_asf_37.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_asf_37


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
sync_rptr 100.00 100.00 100.00
sync_wptr 100.00 100.00 100.00



Module Instance : tb.dut.u_asf_39.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_asf_39


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
sync_rptr 100.00 100.00 100.00
sync_wptr 100.00 100.00 100.00



Module Instance : tb.dut.u_asf_41.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_asf_41


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
sync_rptr 100.00 100.00 100.00
sync_wptr 100.00 100.00 100.00



Module Instance : tb.dut.u_asf_35.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_asf_35


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
sync_rptr 100.00 100.00 100.00
sync_wptr 100.00 100.00 100.00



Module Instance : tb.dut.u_asf_37.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_asf_37


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
sync_rptr 100.00 100.00 100.00
sync_wptr 100.00 100.00 100.00



Module Instance : tb.dut.u_asf_39.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_asf_39


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
sync_rptr 100.00 100.00 100.00
sync_wptr 100.00 100.00 100.00



Module Instance : tb.dut.u_asf_41.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_asf_41


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
sync_rptr 100.00 100.00 100.00
sync_wptr 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_async
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5611100.00
ALWAYS5944100.00
ALWAYS6844100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
ALWAYS9244100.00
ALWAYS10144100.00
ALWAYS11733100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
ALWAYS19222100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28811100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
56 1 1
59 1 1
60 1 1
61 1 1
62 1 1
MISSING_ELSE
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
86 1 1
89 1 1
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
130 1 1
131 1 1
132 1 1
166 1 1
167 1 1
171 1 1
172 1 1
192 1 1
193 1 1
MISSING_ELSE
197 1 1
211 1 1
284 1 1
285 1 1
287 1 1
288 1 1


Cond Coverage for Module : prim_fifo_async ( parameter Width=107,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_asf_35.reqfifo

SCORECOND
100.00 100.00
tb.dut.u_asf_37.reqfifo

SCORECOND
100.00 100.00
tb.dut.u_asf_39.reqfifo

SCORECOND
100.00 100.00
tb.dut.u_asf_41.reqfifo

TotalCoveredPercent
Conditions1414100.00
Logical1414100.00
Non-Logical00
Event00

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_async ( parameter Width=64,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :
SCORECOND
98.21 92.86
tb.dut.u_asf_35.rspfifo

SCORECOND
98.21 92.86
tb.dut.u_asf_37.rspfifo

SCORECOND
98.21 92.86
tb.dut.u_asf_39.rspfifo

SCORECOND
98.21 92.86
tb.dut.u_asf_41.rspfifo

TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_async
Line No.TotalCoveredPercent
Branches 18 18 100.00
TERNARY 211 2 2 100.00
IF 59 3 3 100.00
IF 68 3 3 100.00
IF 92 3 3 100.00
IF 101 3 3 100.00
IF 117 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 211 (rvalid_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_wr_ni)) -2-: 61 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_wr_ni)) -2-: 70 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 92 if ((!rst_rd_ni)) -2-: 94 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_rd_ni)) -2-: 103 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_wr_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 192 if (fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_async
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
GrayRptr_A 2147483647 2147483647 0 0
GrayWptr_A 2147483647 2147483647 0 0
ParamCheckDepth_A 7200 7200 0 0


GrayRptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4219077 4218820 0 0
T2 1881834 1881744 0 0
T3 1705206 1705165 0 0
T7 2336986 2336303 0 0
T8 44135 43910 0 0
T9 368276 354817 0 0
T10 1375066 1374927 0 0
T11 239838 239380 0 0
T12 138645 138269 0 0
T13 3082500 3081398 0 0

GrayWptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4219077 4218820 0 0
T2 1881834 1881744 0 0
T3 1705206 1705165 0 0
T7 2336986 2336303 0 0
T8 44135 43910 0 0
T9 368276 354817 0 0
T10 1375066 1374927 0 0
T11 239838 239380 0 0
T12 138645 138269 0 0
T13 3082500 3081398 0 0

ParamCheckDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7200 7200 0 0
T1 8 8 0 0
T2 8 8 0 0
T3 8 8 0 0
T7 8 8 0 0
T8 8 8 0 0
T9 8 8 0 0
T10 8 8 0 0
T11 8 8 0 0
T12 8 8 0 0
T13 8 8 0 0

Line Coverage for Instance : tb.dut.u_asf_35.rspfifo
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5611100.00
ALWAYS5944100.00
ALWAYS6844100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
ALWAYS9244100.00
ALWAYS10144100.00
ALWAYS11733100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
ALWAYS19222100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28811100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
56 1 1
59 1 1
60 1 1
61 1 1
62 1 1
MISSING_ELSE
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
86 1 1
89 1 1
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
130 1 1
131 1 1
132 1 1
166 1 1
167 1 1
171 1 1
172 1 1
192 1 1
193 1 1
MISSING_ELSE
197 1 1
211 1 1
284 1 1
285 1 1
287 1 1
288 1 1


Cond Coverage for Instance : tb.dut.u_asf_35.rspfifo
TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

Branch Coverage for Instance : tb.dut.u_asf_35.rspfifo
Line No.TotalCoveredPercent
Branches 18 18 100.00
TERNARY 211 2 2 100.00
IF 59 3 3 100.00
IF 68 3 3 100.00
IF 92 3 3 100.00
IF 101 3 3 100.00
IF 117 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 211 (rvalid_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_wr_ni)) -2-: 61 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_wr_ni)) -2-: 70 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 92 if ((!rst_rd_ni)) -2-: 94 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_rd_ni)) -2-: 103 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_wr_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 192 if (fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_asf_35.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
GrayRptr_A 394829365 394693565 0 0
GrayWptr_A 501297676 501166509 0 0
ParamCheckDepth_A 900 900 0 0


GrayRptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394829365 394693565 0 0
T1 521851 521819 0 0
T2 156266 156258 0 0
T3 168551 168547 0 0
T7 331905 331808 0 0
T8 1991 1981 0 0
T9 25110 24182 0 0
T10 71504 71496 0 0
T11 39265 39190 0 0
T12 12136 12103 0 0
T13 462985 462820 0 0

GrayWptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501297676 501166509 0 0
T1 679980 679939 0 0
T2 140864 140858 0 0
T3 105072 105069 0 0
T7 205292 205232 0 0
T8 8296 8253 0 0
T9 78679 75822 0 0
T10 308017 307987 0 0
T11 29185 29129 0 0
T12 6619 6601 0 0
T13 225403 225322 0 0

ParamCheckDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_asf_37.rspfifo
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5611100.00
ALWAYS5944100.00
ALWAYS6844100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
ALWAYS9244100.00
ALWAYS10144100.00
ALWAYS11733100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
ALWAYS19222100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28811100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
56 1 1
59 1 1
60 1 1
61 1 1
62 1 1
MISSING_ELSE
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
86 1 1
89 1 1
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
130 1 1
131 1 1
132 1 1
166 1 1
167 1 1
171 1 1
172 1 1
192 1 1
193 1 1
MISSING_ELSE
197 1 1
211 1 1
284 1 1
285 1 1
287 1 1
288 1 1


Cond Coverage for Instance : tb.dut.u_asf_37.rspfifo
TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

Branch Coverage for Instance : tb.dut.u_asf_37.rspfifo
Line No.TotalCoveredPercent
Branches 18 18 100.00
TERNARY 211 2 2 100.00
IF 59 3 3 100.00
IF 68 3 3 100.00
IF 92 3 3 100.00
IF 101 3 3 100.00
IF 117 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 211 (rvalid_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_wr_ni)) -2-: 61 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_wr_ni)) -2-: 70 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 92 if ((!rst_rd_ni)) -2-: 94 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_rd_ni)) -2-: 103 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_wr_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 192 if (fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_asf_37.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
GrayRptr_A 394829365 394693565 0 0
GrayWptr_A 486540647 486421482 0 0
ParamCheckDepth_A 900 900 0 0


GrayRptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394829365 394693565 0 0
T1 521851 521819 0 0
T2 156266 156258 0 0
T3 168551 168547 0 0
T7 331905 331808 0 0
T8 1991 1981 0 0
T9 25110 24182 0 0
T10 71504 71496 0 0
T11 39265 39190 0 0
T12 12136 12103 0 0
T13 462985 462820 0 0

GrayWptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486540647 486421482 0 0
T1 885570 885516 0 0
T2 792357 792320 0 0
T3 170733 170729 0 0
T7 335321 335223 0 0
T8 12445 12381 0 0
T9 77837 75008 0 0
T10 313512 313481 0 0
T11 26001 25951 0 0
T12 10665 10636 0 0
T13 152299 152244 0 0

ParamCheckDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_asf_39.rspfifo
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5611100.00
ALWAYS5944100.00
ALWAYS6844100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
ALWAYS9244100.00
ALWAYS10144100.00
ALWAYS11733100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
ALWAYS19222100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28811100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
56 1 1
59 1 1
60 1 1
61 1 1
62 1 1
MISSING_ELSE
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
86 1 1
89 1 1
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
130 1 1
131 1 1
132 1 1
166 1 1
167 1 1
171 1 1
172 1 1
192 1 1
193 1 1
MISSING_ELSE
197 1 1
211 1 1
284 1 1
285 1 1
287 1 1
288 1 1


Cond Coverage for Instance : tb.dut.u_asf_39.rspfifo
TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

Branch Coverage for Instance : tb.dut.u_asf_39.rspfifo
Line No.TotalCoveredPercent
Branches 18 18 100.00
TERNARY 211 2 2 100.00
IF 59 3 3 100.00
IF 68 3 3 100.00
IF 92 3 3 100.00
IF 101 3 3 100.00
IF 117 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 211 (rvalid_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_wr_ni)) -2-: 61 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_wr_ni)) -2-: 70 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 92 if ((!rst_rd_ni)) -2-: 94 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_rd_ni)) -2-: 103 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_wr_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 192 if (fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_asf_39.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
GrayRptr_A 394829365 394693565 0 0
GrayWptr_A 508331063 508203752 0 0
ParamCheckDepth_A 900 900 0 0


GrayRptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394829365 394693565 0 0
T1 521851 521819 0 0
T2 156266 156258 0 0
T3 168551 168547 0 0
T7 331905 331808 0 0
T8 1991 1981 0 0
T9 25110 24182 0 0
T10 71504 71496 0 0
T11 39265 39190 0 0
T12 12136 12103 0 0
T13 462985 462820 0 0

GrayWptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508331063 508203752 0 0
T1 154974 154965 0 0
T2 191492 191483 0 0
T3 612918 612903 0 0
T7 318201 318108 0 0
T8 5309 5282 0 0
T9 46872 45160 0 0
T10 121004 120992 0 0
T11 15388 15359 0 0
T12 36776 36676 0 0
T13 426429 426276 0 0

ParamCheckDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_asf_41.rspfifo
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5611100.00
ALWAYS5944100.00
ALWAYS6844100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
ALWAYS9244100.00
ALWAYS10144100.00
ALWAYS11733100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
ALWAYS19222100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28811100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
56 1 1
59 1 1
60 1 1
61 1 1
62 1 1
MISSING_ELSE
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
86 1 1
89 1 1
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
130 1 1
131 1 1
132 1 1
166 1 1
167 1 1
171 1 1
172 1 1
192 1 1
193 1 1
MISSING_ELSE
197 1 1
211 1 1
284 1 1
285 1 1
287 1 1
288 1 1


Cond Coverage for Instance : tb.dut.u_asf_41.rspfifo
TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_asf_41.rspfifo
Line No.TotalCoveredPercent
Branches 18 18 100.00
TERNARY 211 2 2 100.00
IF 59 3 3 100.00
IF 68 3 3 100.00
IF 92 3 3 100.00
IF 101 3 3 100.00
IF 117 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 211 (rvalid_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_wr_ni)) -2-: 61 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_wr_ni)) -2-: 70 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 92 if ((!rst_rd_ni)) -2-: 94 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_rd_ni)) -2-: 103 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_wr_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 192 if (fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_asf_41.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
GrayRptr_A 394829365 394693565 0 0
GrayWptr_A 485908962 485774876 0 0
ParamCheckDepth_A 900 900 0 0


GrayRptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394829365 394693565 0 0
T1 521851 521819 0 0
T2 156266 156258 0 0
T3 168551 168547 0 0
T7 331905 331808 0 0
T8 1991 1981 0 0
T9 25110 24182 0 0
T10 71504 71496 0 0
T11 39265 39190 0 0
T12 12136 12103 0 0
T13 462985 462820 0 0

GrayWptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 485908962 485774876 0 0
T1 411149 411124 0 0
T2 132057 132051 0 0
T3 142279 142276 0 0
T7 150552 150508 0 0
T8 10121 10070 0 0
T9 64448 62099 0 0
T10 346517 346483 0 0
T11 12204 12181 0 0
T12 36041 35944 0 0
T13 426429 426276 0 0

ParamCheckDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_asf_35.reqfifo
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5611100.00
ALWAYS5944100.00
ALWAYS6844100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
ALWAYS9244100.00
ALWAYS10144100.00
ALWAYS11733100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
ALWAYS19222100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28811100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
56 1 1
59 1 1
60 1 1
61 1 1
62 1 1
MISSING_ELSE
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
86 1 1
89 1 1
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
130 1 1
131 1 1
132 1 1
166 1 1
167 1 1
171 1 1
172 1 1
192 1 1
193 1 1
MISSING_ELSE
197 1 1
211 1 1
284 1 1
285 1 1
287 1 1
288 1 1


Cond Coverage for Instance : tb.dut.u_asf_35.reqfifo
TotalCoveredPercent
Conditions1414100.00
Logical1414100.00
Non-Logical00
Event00

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

Branch Coverage for Instance : tb.dut.u_asf_35.reqfifo
Line No.TotalCoveredPercent
Branches 18 18 100.00
TERNARY 211 2 2 100.00
IF 59 3 3 100.00
IF 68 3 3 100.00
IF 92 3 3 100.00
IF 101 3 3 100.00
IF 117 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 211 (rvalid_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_wr_ni)) -2-: 61 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_wr_ni)) -2-: 70 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 92 if ((!rst_rd_ni)) -2-: 94 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_rd_ni)) -2-: 103 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_wr_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 192 if (fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_asf_35.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
GrayRptr_A 501297676 501166509 0 0
GrayWptr_A 394829365 394693565 0 0
ParamCheckDepth_A 900 900 0 0


GrayRptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501297676 501166509 0 0
T1 679980 679939 0 0
T2 140864 140858 0 0
T3 105072 105069 0 0
T7 205292 205232 0 0
T8 8296 8253 0 0
T9 78679 75822 0 0
T10 308017 307987 0 0
T11 29185 29129 0 0
T12 6619 6601 0 0
T13 225403 225322 0 0

GrayWptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394829365 394693565 0 0
T1 521851 521819 0 0
T2 156266 156258 0 0
T3 168551 168547 0 0
T7 331905 331808 0 0
T8 1991 1981 0 0
T9 25110 24182 0 0
T10 71504 71496 0 0
T11 39265 39190 0 0
T12 12136 12103 0 0
T13 462985 462820 0 0

ParamCheckDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_asf_37.reqfifo
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5611100.00
ALWAYS5944100.00
ALWAYS6844100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
ALWAYS9244100.00
ALWAYS10144100.00
ALWAYS11733100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
ALWAYS19222100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28811100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
56 1 1
59 1 1
60 1 1
61 1 1
62 1 1
MISSING_ELSE
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
86 1 1
89 1 1
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
130 1 1
131 1 1
132 1 1
166 1 1
167 1 1
171 1 1
172 1 1
192 1 1
193 1 1
MISSING_ELSE
197 1 1
211 1 1
284 1 1
285 1 1
287 1 1
288 1 1


Cond Coverage for Instance : tb.dut.u_asf_37.reqfifo
TotalCoveredPercent
Conditions1414100.00
Logical1414100.00
Non-Logical00
Event00

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

Branch Coverage for Instance : tb.dut.u_asf_37.reqfifo
Line No.TotalCoveredPercent
Branches 18 18 100.00
TERNARY 211 2 2 100.00
IF 59 3 3 100.00
IF 68 3 3 100.00
IF 92 3 3 100.00
IF 101 3 3 100.00
IF 117 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 211 (rvalid_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_wr_ni)) -2-: 61 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_wr_ni)) -2-: 70 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 92 if ((!rst_rd_ni)) -2-: 94 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_rd_ni)) -2-: 103 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_wr_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 192 if (fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_asf_37.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
GrayRptr_A 486540647 486421482 0 0
GrayWptr_A 394829365 394693565 0 0
ParamCheckDepth_A 900 900 0 0


GrayRptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486540647 486421482 0 0
T1 885570 885516 0 0
T2 792357 792320 0 0
T3 170733 170729 0 0
T7 335321 335223 0 0
T8 12445 12381 0 0
T9 77837 75008 0 0
T10 313512 313481 0 0
T11 26001 25951 0 0
T12 10665 10636 0 0
T13 152299 152244 0 0

GrayWptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394829365 394693565 0 0
T1 521851 521819 0 0
T2 156266 156258 0 0
T3 168551 168547 0 0
T7 331905 331808 0 0
T8 1991 1981 0 0
T9 25110 24182 0 0
T10 71504 71496 0 0
T11 39265 39190 0 0
T12 12136 12103 0 0
T13 462985 462820 0 0

ParamCheckDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_asf_39.reqfifo
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5611100.00
ALWAYS5944100.00
ALWAYS6844100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
ALWAYS9244100.00
ALWAYS10144100.00
ALWAYS11733100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
ALWAYS19222100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28811100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
56 1 1
59 1 1
60 1 1
61 1 1
62 1 1
MISSING_ELSE
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
86 1 1
89 1 1
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
130 1 1
131 1 1
132 1 1
166 1 1
167 1 1
171 1 1
172 1 1
192 1 1
193 1 1
MISSING_ELSE
197 1 1
211 1 1
284 1 1
285 1 1
287 1 1
288 1 1


Cond Coverage for Instance : tb.dut.u_asf_39.reqfifo
TotalCoveredPercent
Conditions1414100.00
Logical1414100.00
Non-Logical00
Event00

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

Branch Coverage for Instance : tb.dut.u_asf_39.reqfifo
Line No.TotalCoveredPercent
Branches 18 18 100.00
TERNARY 211 2 2 100.00
IF 59 3 3 100.00
IF 68 3 3 100.00
IF 92 3 3 100.00
IF 101 3 3 100.00
IF 117 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 211 (rvalid_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_wr_ni)) -2-: 61 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_wr_ni)) -2-: 70 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 92 if ((!rst_rd_ni)) -2-: 94 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_rd_ni)) -2-: 103 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_wr_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 192 if (fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_asf_39.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
GrayRptr_A 508331063 508203752 0 0
GrayWptr_A 394829365 394693565 0 0
ParamCheckDepth_A 900 900 0 0


GrayRptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 508331063 508203752 0 0
T1 154974 154965 0 0
T2 191492 191483 0 0
T3 612918 612903 0 0
T7 318201 318108 0 0
T8 5309 5282 0 0
T9 46872 45160 0 0
T10 121004 120992 0 0
T11 15388 15359 0 0
T12 36776 36676 0 0
T13 426429 426276 0 0

GrayWptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394829365 394693565 0 0
T1 521851 521819 0 0
T2 156266 156258 0 0
T3 168551 168547 0 0
T7 331905 331808 0 0
T8 1991 1981 0 0
T9 25110 24182 0 0
T10 71504 71496 0 0
T11 39265 39190 0 0
T12 12136 12103 0 0
T13 462985 462820 0 0

ParamCheckDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_asf_41.reqfifo
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5611100.00
ALWAYS5944100.00
ALWAYS6844100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
ALWAYS9244100.00
ALWAYS10144100.00
ALWAYS11733100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
ALWAYS19222100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28811100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
56 1 1
59 1 1
60 1 1
61 1 1
62 1 1
MISSING_ELSE
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
86 1 1
89 1 1
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
130 1 1
131 1 1
132 1 1
166 1 1
167 1 1
171 1 1
172 1 1
192 1 1
193 1 1
MISSING_ELSE
197 1 1
211 1 1
284 1 1
285 1 1
287 1 1
288 1 1


Cond Coverage for Instance : tb.dut.u_asf_41.reqfifo
TotalCoveredPercent
Conditions1414100.00
Logical1414100.00
Non-Logical00
Event00

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_asf_41.reqfifo
Line No.TotalCoveredPercent
Branches 18 18 100.00
TERNARY 211 2 2 100.00
IF 59 3 3 100.00
IF 68 3 3 100.00
IF 92 3 3 100.00
IF 101 3 3 100.00
IF 117 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 211 (rvalid_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_wr_ni)) -2-: 61 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_wr_ni)) -2-: 70 if (fifo_incr_wptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 92 if ((!rst_rd_ni)) -2-: 94 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_rd_ni)) -2-: 103 if (fifo_incr_rptr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_wr_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 192 if (fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_asf_41.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
GrayRptr_A 485908962 485774876 0 0
GrayWptr_A 394829365 394693565 0 0
ParamCheckDepth_A 900 900 0 0


GrayRptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 485908962 485774876 0 0
T1 411149 411124 0 0
T2 132057 132051 0 0
T3 142279 142276 0 0
T7 150552 150508 0 0
T8 10121 10070 0 0
T9 64448 62099 0 0
T10 346517 346483 0 0
T11 12204 12181 0 0
T12 36041 35944 0 0
T13 426429 426276 0 0

GrayWptr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394829365 394693565 0 0
T1 521851 521819 0 0
T2 156266 156258 0 0
T3 168551 168547 0 0
T7 331905 331808 0 0
T8 1991 1981 0 0
T9 25110 24182 0 0
T10 71504 71496 0 0
T11 39265 39190 0 0
T12 12136 12103 0 0
T13 462985 462820 0 0

ParamCheckDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%