Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7751118	0	0
GntImpliesValid_A	2147483647	7751118	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7751118	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	440965392	0	0
ReadyAndValidImplyGrant_A	2147483647	7751118	0	0
ReqAndReadyImplyGrant_A	2147483647	7751118	0	0
ReqImpliesValid_A	2147483647	35185918	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46079	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7751118	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12524424	12523680	0	0
T2	3750384	3750216	0	0
T3	4045224	4045128	0	0
T7	7965720	7963416	0	0
T8	47784	47568	0	0
T9	602640	580824	0	0
T10	1716096	1715928	0	0
T11	942360	940584	0	0
T12	291264	290496	0	0
T13	11111640	11107752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751118	0	0
T1	12524424	556	0	0
T2	3750384	5195	0	0
T3	4045224	4348	0	0
T7	7965720	414	0	0
T8	47784	1427	0	0
T9	602640	2455	0	0
T10	1716096	7773	0	0
T11	942360	2370	0	0
T12	291264	7392	0	0
T13	11111640	46762	0	0
T14	0	9418	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751118	0	0
T1	12524424	556	0	0
T2	3750384	5195	0	0
T3	4045224	4348	0	0
T7	7965720	414	0	0
T8	47784	1427	0	0
T9	602640	2455	0	0
T10	1716096	7773	0	0
T11	942360	2370	0	0
T12	291264	7392	0	0
T13	11111640	46762	0	0
T14	0	9418	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12524424	12523680	0	0
T2	3750384	3750216	0	0
T3	4045224	4045128	0	0
T7	7965720	7963416	0	0
T8	47784	47568	0	0
T9	602640	580824	0	0
T10	1716096	1715928	0	0
T11	942360	940584	0	0
T12	291264	290496	0	0
T13	11111640	11107752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12524424	12523680	0	0
T2	3750384	3750216	0	0
T3	4045224	4045128	0	0
T7	7965720	7963416	0	0
T8	47784	47568	0	0
T9	602640	580824	0	0
T10	1716096	1715928	0	0
T11	942360	940584	0	0
T12	291264	290496	0	0
T13	11111640	11107752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751118	0	0
T1	12524424	556	0	0
T2	3750384	5195	0	0
T3	4045224	4348	0	0
T7	7965720	414	0	0
T8	47784	1427	0	0
T9	602640	2455	0	0
T10	1716096	7773	0	0
T11	942360	2370	0	0
T12	291264	7392	0	0
T13	11111640	46762	0	0
T14	0	9418	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	440965392	0	0
T1	12524424	643615	0	0
T2	3750384	152132	0	0
T3	4045224	155956	0	0
T7	7965720	278088	0	0
T8	47784	1333	0	0
T9	602640	34752	0	0
T10	1716096	105136	0	0
T11	942360	53853	0	0
T12	291264	8402	0	0
T13	11111640	638864	0	0
T14	0	20833	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751118	0	0
T1	12524424	556	0	0
T2	3750384	5195	0	0
T3	4045224	4348	0	0
T7	7965720	414	0	0
T8	47784	1427	0	0
T9	602640	2455	0	0
T10	1716096	7773	0	0
T11	942360	2370	0	0
T12	291264	7392	0	0
T13	11111640	46762	0	0
T14	0	9418	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751118	0	0
T1	12524424	556	0	0
T2	3750384	5195	0	0
T3	4045224	4348	0	0
T7	7965720	414	0	0
T8	47784	1427	0	0
T9	602640	2455	0	0
T10	1716096	7773	0	0
T11	942360	2370	0	0
T12	291264	7392	0	0
T13	11111640	46762	0	0
T14	0	9418	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35185918	0	0
T1	12524424	30785	0	0
T2	3750384	8565	0	0
T3	4045224	10581	0	0
T7	7965720	670	0	0
T8	47784	1600	0	0
T9	602640	6834	0	0
T10	1716096	16839	0	0
T11	942360	4802	0	0
T12	291264	8573	0	0
T13	11111640	209267	0	0
T14	0	15974	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46079	0	21600
T8	3982	7	0	2
T9	50220	0	0	2
T10	143008	2	0	2
T11	78530	0	0	2
T12	24272	29	0	2
T13	925970	86	0	2
T14	122650	45	0	2
T15	29828	13	0	2
T16	0	1	0	0
T17	0	670	0	0
T18	0	8	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	0	12	0	0
T22	3758	0	0	2
T23	3366	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12524424	12523680	0	0
T2	3750384	3750216	0	0
T3	4045224	4045128	0	0
T7	7965720	7963416	0	0
T8	47784	47568	0	0
T9	602640	580824	0	0
T10	1716096	1715928	0	0
T11	942360	940584	0	0
T12	291264	290496	0	0
T13	11111640	11107752	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751118	0	0
T1	12524424	556	0	0
T2	3750384	5195	0	0
T3	4045224	4348	0	0
T7	7965720	414	0	0
T8	47784	1427	0	0
T9	602640	2455	0	0
T10	1716096	7773	0	0
T11	942360	2370	0	0
T12	291264	7392	0	0
T13	11111640	46762	0	0
T14	0	9418	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	867071	0	0
GntImpliesValid_A	394829365	867071	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	867071	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	12382004	0	0
ReadyAndValidImplyGrant_A	394829365	867071	0	0
ReqAndReadyImplyGrant_A	394829365	867071	0	0
ReqImpliesValid_A	394829365	2487995	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	867071	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	867071	0	0
T1	521851	73	0	0
T2	156266	606	0	0
T3	168551	337	0	0
T7	331905	51	0	0
T8	1991	146	0	0
T9	25110	476	0	0
T10	71504	860	0	0
T11	39265	247	0	0
T12	12136	825	0	0
T13	462985	6952	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	867071	0	0
T1	521851	73	0	0
T2	156266	606	0	0
T3	168551	337	0	0
T7	331905	51	0	0
T8	1991	146	0	0
T9	25110	476	0	0
T10	71504	860	0	0
T11	39265	247	0	0
T12	12136	825	0	0
T13	462985	6952	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	867071	0	0
T1	521851	73	0	0
T2	156266	606	0	0
T3	168551	337	0	0
T7	331905	51	0	0
T8	1991	146	0	0
T9	25110	476	0	0
T10	71504	860	0	0
T11	39265	247	0	0
T12	12136	825	0	0
T13	462985	6952	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	12382004	0	0
T1	521851	23746	0	0
T2	156266	2502	0	0
T3	168551	1459	0	0
T7	331905	213	0	0
T8	1991	120	0	0
T9	25110	2761	0	0
T10	71504	5636	0	0
T11	39265	1906	0	0
T12	12136	595	0	0
T13	462985	41469	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	867071	0	0
T1	521851	73	0	0
T2	156266	606	0	0
T3	168551	337	0	0
T7	331905	51	0	0
T8	1991	146	0	0
T9	25110	476	0	0
T10	71504	860	0	0
T11	39265	247	0	0
T12	12136	825	0	0
T13	462985	6952	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	867071	0	0
T1	521851	73	0	0
T2	156266	606	0	0
T3	168551	337	0	0
T7	331905	51	0	0
T8	1991	146	0	0
T9	25110	476	0	0
T10	71504	860	0	0
T11	39265	247	0	0
T12	12136	825	0	0
T13	462985	6952	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	2487995	0	0
T1	521851	2732	0	0
T2	156266	858	0	0
T3	168551	445	0	0
T7	331905	63	0	0
T8	1991	173	0	0
T9	25110	1948	0	0
T10	71504	1627	0	0
T11	39265	330	0	0
T12	12136	1056	0	0
T13	462985	25908	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	867071	0	0
T1	521851	73	0	0
T2	156266	606	0	0
T3	168551	337	0	0
T7	331905	51	0	0
T8	1991	146	0	0
T9	25110	476	0	0
T10	71504	860	0	0
T11	39265	247	0	0
T12	12136	825	0	0
T13	462985	6952	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	862736	0	0
GntImpliesValid_A	394829365	862736	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	862736	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	12481105	0	0
ReadyAndValidImplyGrant_A	394829365	862736	0	0
ReqAndReadyImplyGrant_A	394829365	862736	0	0
ReqImpliesValid_A	394829365	2498326	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	862736	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	862736	0	0
T1	521851	64	0	0
T2	156266	577	0	0
T3	168551	367	0	0
T7	331905	46	0	0
T8	1991	189	0	0
T9	25110	330	0	0
T10	71504	833	0	0
T11	39265	258	0	0
T12	12136	829	0	0
T13	462985	4096	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	862736	0	0
T1	521851	64	0	0
T2	156266	577	0	0
T3	168551	367	0	0
T7	331905	46	0	0
T8	1991	189	0	0
T9	25110	330	0	0
T10	71504	833	0	0
T11	39265	258	0	0
T12	12136	829	0	0
T13	462985	4096	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	862736	0	0
T1	521851	64	0	0
T2	156266	577	0	0
T3	168551	367	0	0
T7	331905	46	0	0
T8	1991	189	0	0
T9	25110	330	0	0
T10	71504	833	0	0
T11	39265	258	0	0
T12	12136	829	0	0
T13	462985	4096	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	12481105	0	0
T1	521851	19731	0	0
T2	156266	2412	0	0
T3	168551	1480	0	0
T7	331905	185	0	0
T8	1991	123	0	0
T9	25110	1985	0	0
T10	71504	6078	0	0
T11	39265	1940	0	0
T12	12136	613	0	0
T13	462985	30169	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	862736	0	0
T1	521851	64	0	0
T2	156266	577	0	0
T3	168551	367	0	0
T7	331905	46	0	0
T8	1991	189	0	0
T9	25110	330	0	0
T10	71504	833	0	0
T11	39265	258	0	0
T12	12136	829	0	0
T13	462985	4096	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	862736	0	0
T1	521851	64	0	0
T2	156266	577	0	0
T3	168551	367	0	0
T7	331905	46	0	0
T8	1991	189	0	0
T9	25110	330	0	0
T10	71504	833	0	0
T11	39265	258	0	0
T12	12136	829	0	0
T13	462985	4096	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	2498326	0	0
T1	521851	2310	0	0
T2	156266	800	0	0
T3	168551	528	0	0
T7	331905	61	0	0
T8	1991	256	0	0
T9	25110	736	0	0
T10	71504	1612	0	0
T11	39265	341	0	0
T12	12136	1046	0	0
T13	462985	6293	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	862736	0	0
T1	521851	64	0	0
T2	156266	577	0	0
T3	168551	367	0	0
T7	331905	46	0	0
T8	1991	189	0	0
T9	25110	330	0	0
T10	71504	833	0	0
T11	39265	258	0	0
T12	12136	829	0	0
T13	462985	4096	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	219576	0	0
GntImpliesValid_A	394829365	219576	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	219576	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3106404	0	0
ReadyAndValidImplyGrant_A	394829365	219576	0	0
ReqAndReadyImplyGrant_A	394829365	219576	0	0
ReqImpliesValid_A	394829365	557474	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	219576	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	219576	0	0
T1	521851	18	0	0
T2	156266	152	0	0
T3	168551	0	0	0
T7	331905	16	0	0
T8	1991	49	0	0
T9	25110	49	0	0
T10	71504	223	0	0
T11	39265	71	0	0
T12	12136	198	0	0
T13	462985	632	0	0
T14	0	945	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	219576	0	0
T1	521851	18	0	0
T2	156266	152	0	0
T3	168551	0	0	0
T7	331905	16	0	0
T8	1991	49	0	0
T9	25110	49	0	0
T10	71504	223	0	0
T11	39265	71	0	0
T12	12136	198	0	0
T13	462985	632	0	0
T14	0	945	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	219576	0	0
T1	521851	18	0	0
T2	156266	152	0	0
T3	168551	0	0	0
T7	331905	16	0	0
T8	1991	49	0	0
T9	25110	49	0	0
T10	71504	223	0	0
T11	39265	71	0	0
T12	12136	198	0	0
T13	462985	632	0	0
T14	0	945	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3106404	0	0
T1	521851	3816	0	0
T2	156266	641	0	0
T3	168551	1	0	0
T7	331905	70	0	0
T8	1991	46	0	0
T9	25110	339	0	0
T10	71504	1651	0	0
T11	39265	509	0	0
T12	12136	186	0	0
T13	462985	4923	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	219576	0	0
T1	521851	18	0	0
T2	156266	152	0	0
T3	168551	0	0	0
T7	331905	16	0	0
T8	1991	49	0	0
T9	25110	49	0	0
T10	71504	223	0	0
T11	39265	71	0	0
T12	12136	198	0	0
T13	462985	632	0	0
T14	0	945	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	219576	0	0
T1	521851	18	0	0
T2	156266	152	0	0
T3	168551	0	0	0
T7	331905	16	0	0
T8	1991	49	0	0
T9	25110	49	0	0
T10	71504	223	0	0
T11	39265	71	0	0
T12	12136	198	0	0
T13	462985	632	0	0
T14	0	945	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	557474	0	0
T1	521851	709	0	0
T2	156266	186	0	0
T3	168551	0	0	0
T7	331905	20	0	0
T8	1991	53	0	0
T9	25110	61	0	0
T10	71504	285	0	0
T11	39265	97	0	0
T12	12136	211	0	0
T13	462985	661	0	0
T14	0	1016	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	219576	0	0
T1	521851	18	0	0
T2	156266	152	0	0
T3	168551	0	0	0
T7	331905	16	0	0
T8	1991	49	0	0
T9	25110	49	0	0
T10	71504	223	0	0
T11	39265	71	0	0
T12	12136	198	0	0
T13	462985	632	0	0
T14	0	945	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	224136	0	0
GntImpliesValid_A	394829365	224136	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	224136	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3157369	0	0
ReadyAndValidImplyGrant_A	394829365	224136	0	0
ReqAndReadyImplyGrant_A	394829365	224136	0	0
ReqImpliesValid_A	394829365	645702	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	224136	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	224136	0	0
T1	521851	11	0	0
T2	156266	169	0	0
T3	168551	0	0	0
T7	331905	7	0	0
T8	1991	34	0	0
T9	25110	32	0	0
T10	71504	222	0	0
T11	39265	82	0	0
T12	12136	192	0	0
T13	462985	1151	0	0
T14	0	423	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	224136	0	0
T1	521851	11	0	0
T2	156266	169	0	0
T3	168551	0	0	0
T7	331905	7	0	0
T8	1991	34	0	0
T9	25110	32	0	0
T10	71504	222	0	0
T11	39265	82	0	0
T12	12136	192	0	0
T13	462985	1151	0	0
T14	0	423	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	224136	0	0
T1	521851	11	0	0
T2	156266	169	0	0
T3	168551	0	0	0
T7	331905	7	0	0
T8	1991	34	0	0
T9	25110	32	0	0
T10	71504	222	0	0
T11	39265	82	0	0
T12	12136	192	0	0
T13	462985	1151	0	0
T14	0	423	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3157369	0	0
T1	521851	2808	0	0
T2	156266	696	0	0
T3	168551	1	0	0
T7	331905	37	0	0
T8	1991	29	0	0
T9	25110	282	0	0
T10	71504	1634	0	0
T11	39265	564	0	0
T12	12136	183	0	0
T13	462985	5246	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	224136	0	0
T1	521851	11	0	0
T2	156266	169	0	0
T3	168551	0	0	0
T7	331905	7	0	0
T8	1991	34	0	0
T9	25110	32	0	0
T10	71504	222	0	0
T11	39265	82	0	0
T12	12136	192	0	0
T13	462985	1151	0	0
T14	0	423	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	224136	0	0
T1	521851	11	0	0
T2	156266	169	0	0
T3	168551	0	0	0
T7	331905	7	0	0
T8	1991	34	0	0
T9	25110	32	0	0
T10	71504	222	0	0
T11	39265	82	0	0
T12	12136	192	0	0
T13	462985	1151	0	0
T14	0	423	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	645702	0	0
T1	521851	686	0	0
T2	156266	220	0	0
T3	168551	0	0	0
T7	331905	7	0	0
T8	1991	40	0	0
T9	25110	32	0	0
T10	71504	319	0	0
T11	39265	95	0	0
T12	12136	202	0	0
T13	462985	6010	0	0
T14	0	430	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	224136	0	0
T1	521851	11	0	0
T2	156266	169	0	0
T3	168551	0	0	0
T7	331905	7	0	0
T8	1991	34	0	0
T9	25110	32	0	0
T10	71504	222	0	0
T11	39265	82	0	0
T12	12136	192	0	0
T13	462985	1151	0	0
T14	0	423	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	211643	0	0
GntImpliesValid_A	394829365	211643	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	211643	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	5219638	0	0
ReadyAndValidImplyGrant_A	394829365	211643	0	0
ReqAndReadyImplyGrant_A	394829365	211643	0	0
ReqImpliesValid_A	394829365	1138925	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	211643	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	211643	0	0
T1	521851	20	0	0
T2	156266	157	0	0
T3	168551	0	0	0
T7	331905	10	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	200	0	0
T11	39265	66	0	0
T12	12136	188	0	0
T13	462985	2203	0	0
T14	0	426	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	211643	0	0
T1	521851	20	0	0
T2	156266	157	0	0
T3	168551	0	0	0
T7	331905	10	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	200	0	0
T11	39265	66	0	0
T12	12136	188	0	0
T13	462985	2203	0	0
T14	0	426	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	211643	0	0
T1	521851	20	0	0
T2	156266	157	0	0
T3	168551	0	0	0
T7	331905	10	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	200	0	0
T11	39265	66	0	0
T12	12136	188	0	0
T13	462985	2203	0	0
T14	0	426	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	5219638	0	0
T1	521851	5144	0	0
T2	156266	1460	0	0
T3	168551	0	0	0
T7	331905	111	0	0
T8	1991	138	0	0
T9	25110	284	0	0
T10	71504	987	0	0
T11	39265	959	0	0
T12	12136	1409	0	0
T13	462985	23074	0	0
T14	0	10727	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	211643	0	0
T1	521851	20	0	0
T2	156266	157	0	0
T3	168551	0	0	0
T7	331905	10	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	200	0	0
T11	39265	66	0	0
T12	12136	188	0	0
T13	462985	2203	0	0
T14	0	426	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	211643	0	0
T1	521851	20	0	0
T2	156266	157	0	0
T3	168551	0	0	0
T7	331905	10	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	200	0	0
T11	39265	66	0	0
T12	12136	188	0	0
T13	462985	2203	0	0
T14	0	426	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	1138925	0	0
T1	521851	20	0	0
T2	156266	234	0	0
T3	168551	0	0	0
T7	331905	10	0	0
T8	1991	50	0	0
T9	25110	48	0	0
T10	71504	249	0	0
T11	39265	145	0	0
T12	12136	404	0	0
T13	462985	33263	0	0
T14	0	1917	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	211643	0	0
T1	521851	20	0	0
T2	156266	157	0	0
T3	168551	0	0	0
T7	331905	10	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	200	0	0
T11	39265	66	0	0
T12	12136	188	0	0
T13	462985	2203	0	0
T14	0	426	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	209757	0	0
GntImpliesValid_A	394829365	209757	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	209757	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	5657173	0	0
ReadyAndValidImplyGrant_A	394829365	209757	0	0
ReqAndReadyImplyGrant_A	394829365	209757	0	0
ReqImpliesValid_A	394829365	1228394	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	209757	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	209757	0	0
T1	521851	6	0	0
T2	156266	132	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	38	0	0
T9	25110	41	0	0
T10	71504	214	0	0
T11	39265	70	0	0
T12	12136	213	0	0
T13	462985	1079	0	0
T14	0	431	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	209757	0	0
T1	521851	6	0	0
T2	156266	132	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	38	0	0
T9	25110	41	0	0
T10	71504	214	0	0
T11	39265	70	0	0
T12	12136	213	0	0
T13	462985	1079	0	0
T14	0	431	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	209757	0	0
T1	521851	6	0	0
T2	156266	132	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	38	0	0
T9	25110	41	0	0
T10	71504	214	0	0
T11	39265	70	0	0
T12	12136	213	0	0
T13	462985	1079	0	0
T14	0	431	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	5657173	0	0
T1	521851	903	0	0
T2	156266	1862	0	0
T3	168551	0	0	0
T7	331905	104	0	0
T8	1991	124	0	0
T9	25110	255	0	0
T10	71504	1058	0	0
T11	39265	1153	0	0
T12	12136	1197	0	0
T13	462985	28589	0	0
T14	0	7157	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	209757	0	0
T1	521851	6	0	0
T2	156266	132	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	38	0	0
T9	25110	41	0	0
T10	71504	214	0	0
T11	39265	70	0	0
T12	12136	213	0	0
T13	462985	1079	0	0
T14	0	431	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	209757	0	0
T1	521851	6	0	0
T2	156266	132	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	38	0	0
T9	25110	41	0	0
T10	71504	214	0	0
T11	39265	70	0	0
T12	12136	213	0	0
T13	462985	1079	0	0
T14	0	431	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	1228394	0	0
T1	521851	6	0	0
T2	156266	301	0	0
T3	168551	0	0	0
T7	331905	14	0	0
T8	1991	47	0	0
T9	25110	51	0	0
T10	71504	268	0	0
T11	39265	125	0	0
T12	12136	391	0	0
T13	462985	9650	0	0
T14	0	1094	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	209757	0	0
T1	521851	6	0	0
T2	156266	132	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	38	0	0
T9	25110	41	0	0
T10	71504	214	0	0
T11	39265	70	0	0
T12	12136	213	0	0
T13	462985	1079	0	0
T14	0	431	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	226220	0	0
GntImpliesValid_A	394829365	226220	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	226220	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	5685476	0	0
ReadyAndValidImplyGrant_A	394829365	226220	0	0
ReqAndReadyImplyGrant_A	394829365	226220	0	0
ReqImpliesValid_A	394829365	1349826	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	226220	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	226220	0	0
T1	521851	18	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	36	0	0
T9	25110	49	0	0
T10	71504	175	0	0
T11	39265	55	0	0
T12	12136	226	0	0
T13	462985	622	0	0
T14	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	226220	0	0
T1	521851	18	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	36	0	0
T9	25110	49	0	0
T10	71504	175	0	0
T11	39265	55	0	0
T12	12136	226	0	0
T13	462985	622	0	0
T14	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	226220	0	0
T1	521851	18	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	36	0	0
T9	25110	49	0	0
T10	71504	175	0	0
T11	39265	55	0	0
T12	12136	226	0	0
T13	462985	622	0	0
T14	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	5685476	0	0
T1	521851	1518	0	0
T2	156266	1040	0	0
T3	168551	0	0	0
T7	331905	99	0	0
T8	1991	144	0	0
T9	25110	372	0	0
T10	71504	1402	0	0
T11	39265	1603	0	0
T12	12136	816	0	0
T13	462985	8046	0	0
T14	0	2949	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	226220	0	0
T1	521851	18	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	36	0	0
T9	25110	49	0	0
T10	71504	175	0	0
T11	39265	55	0	0
T12	12136	226	0	0
T13	462985	622	0	0
T14	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	226220	0	0
T1	521851	18	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	36	0	0
T9	25110	49	0	0
T10	71504	175	0	0
T11	39265	55	0	0
T12	12136	226	0	0
T13	462985	622	0	0
T14	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	1349826	0	0
T1	521851	18	0	0
T2	156266	179	0	0
T3	168551	0	0	0
T7	331905	35	0	0
T8	1991	41	0	0
T9	25110	59	0	0
T10	71504	215	0	0
T11	39265	172	0	0
T12	12136	314	0	0
T13	462985	849	0	0
T14	0	4025	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	226220	0	0
T1	521851	18	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	36	0	0
T9	25110	49	0	0
T10	71504	175	0	0
T11	39265	55	0	0
T12	12136	226	0	0
T13	462985	622	0	0
T14	0	832	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	208283	0	0
GntImpliesValid_A	394829365	208283	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	208283	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	5672323	0	0
ReadyAndValidImplyGrant_A	394829365	208283	0	0
ReqAndReadyImplyGrant_A	394829365	208283	0	0
ReqImpliesValid_A	394829365	1153669	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	208283	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	208283	0	0
T1	521851	12	0	0
T2	156266	147	0	0
T3	168551	517	0	0
T7	331905	12	0	0
T8	1991	34	0	0
T9	25110	204	0	0
T10	71504	212	0	0
T11	39265	57	0	0
T12	12136	188	0	0
T13	462985	1137	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	208283	0	0
T1	521851	12	0	0
T2	156266	147	0	0
T3	168551	517	0	0
T7	331905	12	0	0
T8	1991	34	0	0
T9	25110	204	0	0
T10	71504	212	0	0
T11	39265	57	0	0
T12	12136	188	0	0
T13	462985	1137	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	208283	0	0
T1	521851	12	0	0
T2	156266	147	0	0
T3	168551	517	0	0
T7	331905	12	0	0
T8	1991	34	0	0
T9	25110	204	0	0
T10	71504	212	0	0
T11	39265	57	0	0
T12	12136	188	0	0
T13	462985	1137	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	5672323	0	0
T1	521851	6466	0	0
T2	156266	1490	0	0
T3	168551	3860	0	0
T7	331905	194	0	0
T8	1991	107	0	0
T9	25110	755	0	0
T10	71504	1059	0	0
T11	39265	1793	0	0
T12	12136	692	0	0
T13	462985	9027	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	208283	0	0
T1	521851	12	0	0
T2	156266	147	0	0
T3	168551	517	0	0
T7	331905	12	0	0
T8	1991	34	0	0
T9	25110	204	0	0
T10	71504	212	0	0
T11	39265	57	0	0
T12	12136	188	0	0
T13	462985	1137	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	208283	0	0
T1	521851	12	0	0
T2	156266	147	0	0
T3	168551	517	0	0
T7	331905	12	0	0
T8	1991	34	0	0
T9	25110	204	0	0
T10	71504	212	0	0
T11	39265	57	0	0
T12	12136	188	0	0
T13	462985	1137	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	1153669	0	0
T1	521851	12	0	0
T2	156266	194	0	0
T3	168551	1854	0	0
T7	331905	29	0	0
T8	1991	46	0	0
T9	25110	824	0	0
T10	71504	235	0	0
T11	39265	90	0	0
T12	12136	262	0	0
T13	462985	7981	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	208283	0	0
T1	521851	12	0	0
T2	156266	147	0	0
T3	168551	517	0	0
T7	331905	12	0	0
T8	1991	34	0	0
T9	25110	204	0	0
T10	71504	212	0	0
T11	39265	57	0	0
T12	12136	188	0	0
T13	462985	1137	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	213009	0	0
GntImpliesValid_A	394829365	213009	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	213009	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3167768	0	0
ReadyAndValidImplyGrant_A	394829365	213009	0	0
ReqAndReadyImplyGrant_A	394829365	213009	0	0
ReqImpliesValid_A	394829365	604587	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	213009	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	213009	0	0
T1	521851	10	0	0
T2	156266	141	0	0
T3	168551	452	0	0
T7	331905	13	0	0
T8	1991	48	0	0
T9	25110	42	0	0
T10	71504	227	0	0
T11	39265	74	0	0
T12	12136	210	0	0
T13	462985	1190	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	213009	0	0
T1	521851	10	0	0
T2	156266	141	0	0
T3	168551	452	0	0
T7	331905	13	0	0
T8	1991	48	0	0
T9	25110	42	0	0
T10	71504	227	0	0
T11	39265	74	0	0
T12	12136	210	0	0
T13	462985	1190	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	213009	0	0
T1	521851	10	0	0
T2	156266	141	0	0
T3	168551	452	0	0
T7	331905	13	0	0
T8	1991	48	0	0
T9	25110	42	0	0
T10	71504	227	0	0
T11	39265	74	0	0
T12	12136	210	0	0
T13	462985	1190	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3167768	0	0
T1	521851	3125	0	0
T2	156266	565	0	0
T3	168551	1403	0	0
T7	331905	44	0	0
T8	1991	46	0	0
T9	25110	336	0	0
T10	71504	1722	0	0
T11	39265	539	0	0
T12	12136	197	0	0
T13	462985	8595	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	213009	0	0
T1	521851	10	0	0
T2	156266	141	0	0
T3	168551	452	0	0
T7	331905	13	0	0
T8	1991	48	0	0
T9	25110	42	0	0
T10	71504	227	0	0
T11	39265	74	0	0
T12	12136	210	0	0
T13	462985	1190	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	213009	0	0
T1	521851	10	0	0
T2	156266	141	0	0
T3	168551	452	0	0
T7	331905	13	0	0
T8	1991	48	0	0
T9	25110	42	0	0
T10	71504	227	0	0
T11	39265	74	0	0
T12	12136	210	0	0
T13	462985	1190	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	604587	0	0
T1	521851	10	0	0
T2	156266	163	0	0
T3	168551	1061	0	0
T7	331905	13	0	0
T8	1991	51	0	0
T9	25110	42	0	0
T10	71504	301	0	0
T11	39265	83	0	0
T12	12136	224	0	0
T13	462985	1790	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	213009	0	0
T1	521851	10	0	0
T2	156266	141	0	0
T3	168551	452	0	0
T7	331905	13	0	0
T8	1991	48	0	0
T9	25110	42	0	0
T10	71504	227	0	0
T11	39265	74	0	0
T12	12136	210	0	0
T13	462985	1190	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	216216	0	0
GntImpliesValid_A	394829365	216216	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	216216	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3080734	0	0
ReadyAndValidImplyGrant_A	394829365	216216	0	0
ReqAndReadyImplyGrant_A	394829365	216216	0	0
ReqImpliesValid_A	394829365	613536	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	216216	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216216	0	0
T1	521851	20	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	14	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	241	0	0
T11	39265	52	0	0
T12	12136	210	0	0
T13	462985	1609	0	0
T14	0	1383	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216216	0	0
T1	521851	20	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	14	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	241	0	0
T11	39265	52	0	0
T12	12136	210	0	0
T13	462985	1609	0	0
T14	0	1383	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216216	0	0
T1	521851	20	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	14	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	241	0	0
T11	39265	52	0	0
T12	12136	210	0	0
T13	462985	1609	0	0
T14	0	1383	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3080734	0	0
T1	521851	5508	0	0
T2	156266	549	0	0
T3	168551	1	0	0
T7	331905	76	0	0
T8	1991	39	0	0
T9	25110	348	0	0
T10	71504	1811	0	0
T11	39265	408	0	0
T12	12136	202	0	0
T13	462985	9952	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216216	0	0
T1	521851	20	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	14	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	241	0	0
T11	39265	52	0	0
T12	12136	210	0	0
T13	462985	1609	0	0
T14	0	1383	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216216	0	0
T1	521851	20	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	14	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	241	0	0
T11	39265	52	0	0
T12	12136	210	0	0
T13	462985	1609	0	0
T14	0	1383	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	613536	0	0
T1	521851	654	0	0
T2	156266	160	0	0
T3	168551	0	0	0
T7	331905	16	0	0
T8	1991	46	0	0
T9	25110	53	0	0
T10	71504	363	0	0
T11	39265	63	0	0
T12	12136	219	0	0
T13	462985	4885	0	0
T14	0	1740	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216216	0	0
T1	521851	20	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	14	0	0
T8	1991	42	0	0
T9	25110	44	0	0
T10	71504	241	0	0
T11	39265	52	0	0
T12	12136	210	0	0
T13	462985	1609	0	0
T14	0	1383	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	218101	0	0
GntImpliesValid_A	394829365	218101	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	218101	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3127816	0	0
ReadyAndValidImplyGrant_A	394829365	218101	0	0
ReqAndReadyImplyGrant_A	394829365	218101	0	0
ReqImpliesValid_A	394829365	583060	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	218101	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	218101	0	0
T1	521851	20	0	0
T2	156266	137	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	41	0	0
T9	25110	53	0	0
T10	71504	233	0	0
T11	39265	67	0	0
T12	12136	210	0	0
T13	462985	1581	0	0
T14	0	863	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	218101	0	0
T1	521851	20	0	0
T2	156266	137	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	41	0	0
T9	25110	53	0	0
T10	71504	233	0	0
T11	39265	67	0	0
T12	12136	210	0	0
T13	462985	1581	0	0
T14	0	863	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	218101	0	0
T1	521851	20	0	0
T2	156266	137	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	41	0	0
T9	25110	53	0	0
T10	71504	233	0	0
T11	39265	67	0	0
T12	12136	210	0	0
T13	462985	1581	0	0
T14	0	863	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3127816	0	0
T1	521851	5240	0	0
T2	156266	599	0	0
T3	168551	1	0	0
T7	331905	48	0	0
T8	1991	38	0	0
T9	25110	403	0	0
T10	71504	1847	0	0
T11	39265	492	0	0
T12	12136	199	0	0
T13	462985	7730	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	218101	0	0
T1	521851	20	0	0
T2	156266	137	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	41	0	0
T9	25110	53	0	0
T10	71504	233	0	0
T11	39265	67	0	0
T12	12136	210	0	0
T13	462985	1581	0	0
T14	0	863	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	218101	0	0
T1	521851	20	0	0
T2	156266	137	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	41	0	0
T9	25110	53	0	0
T10	71504	233	0	0
T11	39265	67	0	0
T12	12136	210	0	0
T13	462985	1581	0	0
T14	0	863	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	583060	0	0
T1	521851	576	0	0
T2	156266	168	0	0
T3	168551	0	0	0
T7	331905	17	0	0
T8	1991	45	0	0
T9	25110	56	0	0
T10	71504	313	0	0
T11	39265	91	0	0
T12	12136	222	0	0
T13	462985	3964	0	0
T14	0	1062	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	218101	0	0
T1	521851	20	0	0
T2	156266	137	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	41	0	0
T9	25110	53	0	0
T10	71504	233	0	0
T11	39265	67	0	0
T12	12136	210	0	0
T13	462985	1581	0	0
T14	0	863	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	216746	0	0
GntImpliesValid_A	394829365	216746	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	216746	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3146059	0	0
ReadyAndValidImplyGrant_A	394829365	216746	0	0
ReqAndReadyImplyGrant_A	394829365	216746	0	0
ReqImpliesValid_A	394829365	574841	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	216746	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216746	0	0
T1	521851	16	0	0
T2	156266	150	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	37	0	0
T9	25110	175	0	0
T10	71504	219	0	0
T11	39265	73	0	0
T12	12136	197	0	0
T13	462985	983	0	0
T14	0	448	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216746	0	0
T1	521851	16	0	0
T2	156266	150	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	37	0	0
T9	25110	175	0	0
T10	71504	219	0	0
T11	39265	73	0	0
T12	12136	197	0	0
T13	462985	983	0	0
T14	0	448	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216746	0	0
T1	521851	16	0	0
T2	156266	150	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	37	0	0
T9	25110	175	0	0
T10	71504	219	0	0
T11	39265	73	0	0
T12	12136	197	0	0
T13	462985	983	0	0
T14	0	448	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3146059	0	0
T1	521851	4018	0	0
T2	156266	659	0	0
T3	168551	1	0	0
T7	331905	42	0	0
T8	1991	37	0	0
T9	25110	1320	0	0
T10	71504	1520	0	0
T11	39265	559	0	0
T12	12136	188	0	0
T13	462985	6501	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216746	0	0
T1	521851	16	0	0
T2	156266	150	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	37	0	0
T9	25110	175	0	0
T10	71504	219	0	0
T11	39265	73	0	0
T12	12136	197	0	0
T13	462985	983	0	0
T14	0	448	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216746	0	0
T1	521851	16	0	0
T2	156266	150	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	37	0	0
T9	25110	175	0	0
T10	71504	219	0	0
T11	39265	73	0	0
T12	12136	197	0	0
T13	462985	983	0	0
T14	0	448	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	574841	0	0
T1	521851	440	0	0
T2	156266	179	0	0
T3	168551	0	0	0
T7	331905	14	0	0
T8	1991	38	0	0
T9	25110	420	0	0
T10	71504	278	0	0
T11	39265	79	0	0
T12	12136	207	0	0
T13	462985	2859	0	0
T14	0	457	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216746	0	0
T1	521851	16	0	0
T2	156266	150	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	37	0	0
T9	25110	175	0	0
T10	71504	219	0	0
T11	39265	73	0	0
T12	12136	197	0	0
T13	462985	983	0	0
T14	0	448	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	204251	0	0
GntImpliesValid_A	394829365	204251	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	204251	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3089429	0	0
ReadyAndValidImplyGrant_A	394829365	204251	0	0
ReqAndReadyImplyGrant_A	394829365	204251	0	0
ReqImpliesValid_A	394829365	530372	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	204251	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	204251	0	0
T1	521851	19	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	8	0	0
T8	1991	28	0	0
T9	25110	35	0	0
T10	71504	249	0	0
T11	39265	64	0	0
T12	12136	209	0	0
T13	462985	598	0	0
T14	0	980	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	204251	0	0
T1	521851	19	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	8	0	0
T8	1991	28	0	0
T9	25110	35	0	0
T10	71504	249	0	0
T11	39265	64	0	0
T12	12136	209	0	0
T13	462985	598	0	0
T14	0	980	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	204251	0	0
T1	521851	19	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	8	0	0
T8	1991	28	0	0
T9	25110	35	0	0
T10	71504	249	0	0
T11	39265	64	0	0
T12	12136	209	0	0
T13	462985	598	0	0
T14	0	980	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3089429	0	0
T1	521851	6866	0	0
T2	156266	586	0	0
T3	168551	1	0	0
T7	331905	19	0	0
T8	1991	28	0	0
T9	25110	282	0	0
T10	71504	1861	0	0
T11	39265	535	0	0
T12	12136	200	0	0
T13	462985	4352	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	204251	0	0
T1	521851	19	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	8	0	0
T8	1991	28	0	0
T9	25110	35	0	0
T10	71504	249	0	0
T11	39265	64	0	0
T12	12136	209	0	0
T13	462985	598	0	0
T14	0	980	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	204251	0	0
T1	521851	19	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	8	0	0
T8	1991	28	0	0
T9	25110	35	0	0
T10	71504	249	0	0
T11	39265	64	0	0
T12	12136	209	0	0
T13	462985	598	0	0
T14	0	980	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	530372	0	0
T1	521851	899	0	0
T2	156266	173	0	0
T3	168551	0	0	0
T7	331905	15	0	0
T8	1991	29	0	0
T9	25110	35	0	0
T10	71504	367	0	0
T11	39265	75	0	0
T12	12136	219	0	0
T13	462985	663	0	0
T14	0	1438	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	204251	0	0
T1	521851	19	0	0
T2	156266	139	0	0
T3	168551	0	0	0
T7	331905	8	0	0
T8	1991	28	0	0
T9	25110	35	0	0
T10	71504	249	0	0
T11	39265	64	0	0
T12	12136	209	0	0
T13	462985	598	0	0
T14	0	980	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	216103	0	0
GntImpliesValid_A	394829365	216103	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	216103	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3147678	0	0
ReadyAndValidImplyGrant_A	394829365	216103	0	0
ReqAndReadyImplyGrant_A	394829365	216103	0	0
ReqImpliesValid_A	394829365	608328	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	216103	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216103	0	0
T1	521851	18	0	0
T2	156266	141	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	35	0	0
T9	25110	36	0	0
T10	71504	219	0	0
T11	39265	64	0	0
T12	12136	202	0	0
T13	462985	1129	0	0
T14	0	460	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216103	0	0
T1	521851	18	0	0
T2	156266	141	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	35	0	0
T9	25110	36	0	0
T10	71504	219	0	0
T11	39265	64	0	0
T12	12136	202	0	0
T13	462985	1129	0	0
T14	0	460	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216103	0	0
T1	521851	18	0	0
T2	156266	141	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	35	0	0
T9	25110	36	0	0
T10	71504	219	0	0
T11	39265	64	0	0
T12	12136	202	0	0
T13	462985	1129	0	0
T14	0	460	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3147678	0	0
T1	521851	7603	0	0
T2	156266	600	0	0
T3	168551	1	0	0
T7	331905	42	0	0
T8	1991	31	0	0
T9	25110	288	0	0
T10	71504	1738	0	0
T11	39265	467	0	0
T12	12136	191	0	0
T13	462985	4696	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216103	0	0
T1	521851	18	0	0
T2	156266	141	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	35	0	0
T9	25110	36	0	0
T10	71504	219	0	0
T11	39265	64	0	0
T12	12136	202	0	0
T13	462985	1129	0	0
T14	0	460	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216103	0	0
T1	521851	18	0	0
T2	156266	141	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	35	0	0
T9	25110	36	0	0
T10	71504	219	0	0
T11	39265	64	0	0
T12	12136	202	0	0
T13	462985	1129	0	0
T14	0	460	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	608328	0	0
T1	521851	265	0	0
T2	156266	152	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	40	0	0
T9	25110	36	0	0
T10	71504	307	0	0
T11	39265	75	0	0
T12	12136	214	0	0
T13	462985	6278	0	0
T14	0	471	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	216103	0	0
T1	521851	18	0	0
T2	156266	141	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	35	0	0
T9	25110	36	0	0
T10	71504	219	0	0
T11	39265	64	0	0
T12	12136	202	0	0
T13	462985	1129	0	0
T14	0	460	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	215394	0	0
GntImpliesValid_A	394829365	215394	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	215394	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3146526	0	0
ReadyAndValidImplyGrant_A	394829365	215394	0	0
ReqAndReadyImplyGrant_A	394829365	215394	0	0
ReqImpliesValid_A	394829365	596916	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	215394	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215394	0	0
T1	521851	24	0	0
T2	156266	160	0	0
T3	168551	535	0	0
T7	331905	8	0	0
T8	1991	42	0	0
T9	25110	35	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	205	0	0
T13	462985	1691	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215394	0	0
T1	521851	24	0	0
T2	156266	160	0	0
T3	168551	535	0	0
T7	331905	8	0	0
T8	1991	42	0	0
T9	25110	35	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	205	0	0
T13	462985	1691	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215394	0	0
T1	521851	24	0	0
T2	156266	160	0	0
T3	168551	535	0	0
T7	331905	8	0	0
T8	1991	42	0	0
T9	25110	35	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	205	0	0
T13	462985	1691	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3146526	0	0
T1	521851	5493	0	0
T2	156266	639	0	0
T3	168551	1790	0	0
T7	331905	29	0	0
T8	1991	39	0	0
T9	25110	299	0	0
T10	71504	1578	0	0
T11	39265	562	0	0
T12	12136	200	0	0
T13	462985	9244	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215394	0	0
T1	521851	24	0	0
T2	156266	160	0	0
T3	168551	535	0	0
T7	331905	8	0	0
T8	1991	42	0	0
T9	25110	35	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	205	0	0
T13	462985	1691	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215394	0	0
T1	521851	24	0	0
T2	156266	160	0	0
T3	168551	535	0	0
T7	331905	8	0	0
T8	1991	42	0	0
T9	25110	35	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	205	0	0
T13	462985	1691	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	596916	0	0
T1	521851	57	0	0
T2	156266	201	0	0
T3	168551	1232	0	0
T7	331905	8	0	0
T8	1991	46	0	0
T9	25110	38	0	0
T10	71504	303	0	0
T11	39265	73	0	0
T12	12136	211	0	0
T13	462985	4226	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215394	0	0
T1	521851	24	0	0
T2	156266	160	0	0
T3	168551	535	0	0
T7	331905	8	0	0
T8	1991	42	0	0
T9	25110	35	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	205	0	0
T13	462985	1691	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	210404	0	0
GntImpliesValid_A	394829365	210404	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	210404	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3110286	0	0
ReadyAndValidImplyGrant_A	394829365	210404	0	0
ReqAndReadyImplyGrant_A	394829365	210404	0	0
ReqImpliesValid_A	394829365	570048	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	210404	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210404	0	0
T1	521851	15	0	0
T2	156266	138	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	44	0	0
T9	25110	35	0	0
T10	71504	234	0	0
T11	39265	73	0	0
T12	12136	206	0	0
T13	462985	1119	0	0
T14	0	893	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210404	0	0
T1	521851	15	0	0
T2	156266	138	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	44	0	0
T9	25110	35	0	0
T10	71504	234	0	0
T11	39265	73	0	0
T12	12136	206	0	0
T13	462985	1119	0	0
T14	0	893	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210404	0	0
T1	521851	15	0	0
T2	156266	138	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	44	0	0
T9	25110	35	0	0
T10	71504	234	0	0
T11	39265	73	0	0
T12	12136	206	0	0
T13	462985	1119	0	0
T14	0	893	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3110286	0	0
T1	521851	4096	0	0
T2	156266	558	0	0
T3	168551	1	0	0
T7	331905	57	0	0
T8	1991	41	0	0
T9	25110	261	0	0
T10	71504	1810	0	0
T11	39265	604	0	0
T12	12136	198	0	0
T13	462985	6109	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210404	0	0
T1	521851	15	0	0
T2	156266	138	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	44	0	0
T9	25110	35	0	0
T10	71504	234	0	0
T11	39265	73	0	0
T12	12136	206	0	0
T13	462985	1119	0	0
T14	0	893	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210404	0	0
T1	521851	15	0	0
T2	156266	138	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	44	0	0
T9	25110	35	0	0
T10	71504	234	0	0
T11	39265	73	0	0
T12	12136	206	0	0
T13	462985	1119	0	0
T14	0	893	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	570048	0	0
T1	521851	15	0	0
T2	156266	145	0	0
T3	168551	0	0	0
T7	331905	14	0	0
T8	1991	48	0	0
T9	25110	35	0	0
T10	71504	312	0	0
T11	39265	93	0	0
T12	12136	215	0	0
T13	462985	2290	0	0
T14	0	950	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210404	0	0
T1	521851	15	0	0
T2	156266	138	0	0
T3	168551	0	0	0
T7	331905	13	0	0
T8	1991	44	0	0
T9	25110	35	0	0
T10	71504	234	0	0
T11	39265	73	0	0
T12	12136	206	0	0
T13	462985	1119	0	0
T14	0	893	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	236549	0	0
GntImpliesValid_A	394829365	236549	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	236549	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3201157	0	0
ReadyAndValidImplyGrant_A	394829365	236549	0	0
ReqAndReadyImplyGrant_A	394829365	236549	0	0
ReqImpliesValid_A	394829365	580523	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	236549	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	236549	0	0
T1	521851	10	0	0
T2	156266	147	0	0
T3	168551	435	0	0
T7	331905	10	0	0
T8	1991	34	0	0
T9	25110	44	0	0
T10	71504	186	0	0
T11	39265	134	0	0
T12	12136	203	0	0
T13	462985	2130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	236549	0	0
T1	521851	10	0	0
T2	156266	147	0	0
T3	168551	435	0	0
T7	331905	10	0	0
T8	1991	34	0	0
T9	25110	44	0	0
T10	71504	186	0	0
T11	39265	134	0	0
T12	12136	203	0	0
T13	462985	2130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	236549	0	0
T1	521851	10	0	0
T2	156266	147	0	0
T3	168551	435	0	0
T7	331905	10	0	0
T8	1991	34	0	0
T9	25110	44	0	0
T10	71504	186	0	0
T11	39265	134	0	0
T12	12136	203	0	0
T13	462985	2130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3201157	0	0
T1	521851	4931	0	0
T2	156266	618	0	0
T3	168551	1350	0	0
T7	331905	42	0	0
T8	1991	34	0	0
T9	25110	383	0	0
T10	71504	1427	0	0
T11	39265	948	0	0
T12	12136	189	0	0
T13	462985	9208	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	236549	0	0
T1	521851	10	0	0
T2	156266	147	0	0
T3	168551	435	0	0
T7	331905	10	0	0
T8	1991	34	0	0
T9	25110	44	0	0
T10	71504	186	0	0
T11	39265	134	0	0
T12	12136	203	0	0
T13	462985	2130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	236549	0	0
T1	521851	10	0	0
T2	156266	147	0	0
T3	168551	435	0	0
T7	331905	10	0	0
T8	1991	34	0	0
T9	25110	44	0	0
T10	71504	186	0	0
T11	39265	134	0	0
T12	12136	203	0	0
T13	462985	2130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	580523	0	0
T1	521851	10	0	0
T2	156266	196	0	0
T3	168551	1081	0	0
T7	331905	10	0	0
T8	1991	35	0	0
T9	25110	46	0	0
T10	71504	245	0	0
T11	39265	198	0	0
T12	12136	218	0	0
T13	462985	6009	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	236549	0	0
T1	521851	10	0	0
T2	156266	147	0	0
T3	168551	435	0	0
T7	331905	10	0	0
T8	1991	34	0	0
T9	25110	44	0	0
T10	71504	186	0	0
T11	39265	134	0	0
T12	12136	203	0	0
T13	462985	2130	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	220085	0	0
GntImpliesValid_A	394829365	220085	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	220085	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3080006	0	0
ReadyAndValidImplyGrant_A	394829365	220085	0	0
ReqAndReadyImplyGrant_A	394829365	220085	0	0
ReqImpliesValid_A	394829365	582184	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	220085	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	220085	0	0
T1	521851	28	0	0
T2	156266	131	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	27	0	0
T9	25110	60	0	0
T10	71504	236	0	0
T11	39265	57	0	0
T12	12136	180	0	0
T13	462985	1119	0	0
T14	0	448	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	220085	0	0
T1	521851	28	0	0
T2	156266	131	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	27	0	0
T9	25110	60	0	0
T10	71504	236	0	0
T11	39265	57	0	0
T12	12136	180	0	0
T13	462985	1119	0	0
T14	0	448	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	220085	0	0
T1	521851	28	0	0
T2	156266	131	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	27	0	0
T9	25110	60	0	0
T10	71504	236	0	0
T11	39265	57	0	0
T12	12136	180	0	0
T13	462985	1119	0	0
T14	0	448	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3080006	0	0
T1	521851	9126	0	0
T2	156266	550	0	0
T3	168551	1	0	0
T7	331905	53	0	0
T8	1991	28	0	0
T9	25110	420	0	0
T10	71504	1669	0	0
T11	39265	428	0	0
T12	12136	169	0	0
T13	462985	5842	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	220085	0	0
T1	521851	28	0	0
T2	156266	131	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	27	0	0
T9	25110	60	0	0
T10	71504	236	0	0
T11	39265	57	0	0
T12	12136	180	0	0
T13	462985	1119	0	0
T14	0	448	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	220085	0	0
T1	521851	28	0	0
T2	156266	131	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	27	0	0
T9	25110	60	0	0
T10	71504	236	0	0
T11	39265	57	0	0
T12	12136	180	0	0
T13	462985	1119	0	0
T14	0	448	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	582184	0	0
T1	521851	28	0	0
T2	156266	146	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	27	0	0
T9	25110	84	0	0
T10	71504	347	0	0
T11	39265	88	0	0
T12	12136	192	0	0
T13	462985	2502	0	0
T14	0	459	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	220085	0	0
T1	521851	28	0	0
T2	156266	131	0	0
T3	168551	0	0	0
T7	331905	9	0	0
T8	1991	27	0	0
T9	25110	60	0	0
T10	71504	236	0	0
T11	39265	57	0	0
T12	12136	180	0	0
T13	462985	1119	0	0
T14	0	448	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	215690	0	0
GntImpliesValid_A	394829365	215690	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	215690	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3084987	0	0
ReadyAndValidImplyGrant_A	394829365	215690	0	0
ReqAndReadyImplyGrant_A	394829365	215690	0	0
ReqImpliesValid_A	394829365	577732	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	215690	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215690	0	0
T1	521851	11	0	0
T2	156266	132	0	0
T3	168551	441	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	69	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	226	0	0
T13	462985	622	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215690	0	0
T1	521851	11	0	0
T2	156266	132	0	0
T3	168551	441	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	69	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	226	0	0
T13	462985	622	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215690	0	0
T1	521851	11	0	0
T2	156266	132	0	0
T3	168551	441	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	69	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	226	0	0
T13	462985	622	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3084987	0	0
T1	521851	2871	0	0
T2	156266	557	0	0
T3	168551	1436	0	0
T7	331905	60	0	0
T8	1991	34	0	0
T9	25110	476	0	0
T10	71504	1757	0	0
T11	39265	580	0	0
T12	12136	213	0	0
T13	462985	4585	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215690	0	0
T1	521851	11	0	0
T2	156266	132	0	0
T3	168551	441	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	69	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	226	0	0
T13	462985	622	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215690	0	0
T1	521851	11	0	0
T2	156266	132	0	0
T3	168551	441	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	69	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	226	0	0
T13	462985	622	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	577732	0	0
T1	521851	11	0	0
T2	156266	178	0	0
T3	168551	1036	0	0
T7	331905	11	0	0
T8	1991	37	0	0
T9	25110	160	0	0
T10	71504	318	0	0
T11	39265	95	0	0
T12	12136	240	0	0
T13	462985	706	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	215690	0	0
T1	521851	11	0	0
T2	156266	132	0	0
T3	168551	441	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	69	0	0
T10	71504	222	0	0
T11	39265	72	0	0
T12	12136	226	0	0
T13	462985	622	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	207824	0	0
GntImpliesValid_A	394829365	207824	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	207824	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3174921	0	0
ReadyAndValidImplyGrant_A	394829365	207824	0	0
ReqAndReadyImplyGrant_A	394829365	207824	0	0
ReqImpliesValid_A	394829365	532345	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	207824	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	207824	0	0
T1	521851	12	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	35	0	0
T9	25110	82	0	0
T10	71504	209	0	0
T11	39265	60	0	0
T12	12136	198	0	0
T13	462985	1076	0	0
T14	0	428	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	207824	0	0
T1	521851	12	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	35	0	0
T9	25110	82	0	0
T10	71504	209	0	0
T11	39265	60	0	0
T12	12136	198	0	0
T13	462985	1076	0	0
T14	0	428	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	207824	0	0
T1	521851	12	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	35	0	0
T9	25110	82	0	0
T10	71504	209	0	0
T11	39265	60	0	0
T12	12136	198	0	0
T13	462985	1076	0	0
T14	0	428	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3174921	0	0
T1	521851	5411	0	0
T2	156266	542	0	0
T3	168551	1	0	0
T7	331905	49	0	0
T8	1991	34	0	0
T9	25110	640	0	0
T10	71504	1569	0	0
T11	39265	451	0	0
T12	12136	186	0	0
T13	462985	4880	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	207824	0	0
T1	521851	12	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	35	0	0
T9	25110	82	0	0
T10	71504	209	0	0
T11	39265	60	0	0
T12	12136	198	0	0
T13	462985	1076	0	0
T14	0	428	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	207824	0	0
T1	521851	12	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	35	0	0
T9	25110	82	0	0
T10	71504	209	0	0
T11	39265	60	0	0
T12	12136	198	0	0
T13	462985	1076	0	0
T14	0	428	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	532345	0	0
T1	521851	675	0	0
T2	156266	181	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	37	0	0
T9	25110	170	0	0
T10	71504	310	0	0
T11	39265	80	0	0
T12	12136	211	0	0
T13	462985	5621	0	0
T14	0	445	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	207824	0	0
T1	521851	12	0	0
T2	156266	135	0	0
T3	168551	0	0	0
T7	331905	12	0	0
T8	1991	35	0	0
T9	25110	82	0	0
T10	71504	209	0	0
T11	39265	60	0	0
T12	12136	198	0	0
T13	462985	1076	0	0
T14	0	428	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	210878	0	0
GntImpliesValid_A	394829365	210878	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	210878	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3112205	0	0
ReadyAndValidImplyGrant_A	394829365	210878	0	0
ReqAndReadyImplyGrant_A	394829365	210878	0	0
ReqImpliesValid_A	394829365	533416	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	210878	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210878	0	0
T1	521851	10	0	0
T2	156266	124	0	0
T3	168551	494	0	0
T7	331905	17	0	0
T8	1991	38	0	0
T9	25110	44	0	0
T10	71504	234	0	0
T11	39265	64	0	0
T12	12136	191	0	0
T13	462985	1959	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210878	0	0
T1	521851	10	0	0
T2	156266	124	0	0
T3	168551	494	0	0
T7	331905	17	0	0
T8	1991	38	0	0
T9	25110	44	0	0
T10	71504	234	0	0
T11	39265	64	0	0
T12	12136	191	0	0
T13	462985	1959	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210878	0	0
T1	521851	10	0	0
T2	156266	124	0	0
T3	168551	494	0	0
T7	331905	17	0	0
T8	1991	38	0	0
T9	25110	44	0	0
T10	71504	234	0	0
T11	39265	64	0	0
T12	12136	191	0	0
T13	462985	1959	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3112205	0	0
T1	521851	2747	0	0
T2	156266	490	0	0
T3	168551	1553	0	0
T7	331905	54	0	0
T8	1991	38	0	0
T9	25110	368	0	0
T10	71504	1731	0	0
T11	39265	529	0	0
T12	12136	184	0	0
T13	462985	6999	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210878	0	0
T1	521851	10	0	0
T2	156266	124	0	0
T3	168551	494	0	0
T7	331905	17	0	0
T8	1991	38	0	0
T9	25110	44	0	0
T10	71504	234	0	0
T11	39265	64	0	0
T12	12136	191	0	0
T13	462985	1959	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210878	0	0
T1	521851	10	0	0
T2	156266	124	0	0
T3	168551	494	0	0
T7	331905	17	0	0
T8	1991	38	0	0
T9	25110	44	0	0
T10	71504	234	0	0
T11	39265	64	0	0
T12	12136	191	0	0
T13	462985	1959	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	533416	0	0
T1	521851	10	0	0
T2	156266	150	0	0
T3	168551	1044	0	0
T7	331905	28	0	0
T8	1991	39	0	0
T9	25110	58	0	0
T10	71504	404	0	0
T11	39265	93	0	0
T12	12136	199	0	0
T13	462985	6633	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	210878	0	0
T1	521851	10	0	0
T2	156266	124	0	0
T3	168551	494	0	0
T7	331905	17	0	0
T8	1991	38	0	0
T9	25110	44	0	0
T10	71504	234	0	0
T11	39265	64	0	0
T12	12136	191	0	0
T13	462985	1959	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T10
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T8,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	205669	0	0
GntImpliesValid_A	394829365	205669	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	205669	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	3086541	0	0
ReadyAndValidImplyGrant_A	394829365	205669	0	0
ReqAndReadyImplyGrant_A	394829365	205669	0	0
ReqImpliesValid_A	394829365	545791	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	0	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	205669	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	205669	0	0
T1	521851	9	0	0
T2	156266	134	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	46	0	0
T10	71504	220	0	0
T11	39265	68	0	0
T12	12136	202	0	0
T13	462985	1081	0	0
T14	0	458	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	205669	0	0
T1	521851	9	0	0
T2	156266	134	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	46	0	0
T10	71504	220	0	0
T11	39265	68	0	0
T12	12136	202	0	0
T13	462985	1081	0	0
T14	0	458	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	205669	0	0
T1	521851	9	0	0
T2	156266	134	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	46	0	0
T10	71504	220	0	0
T11	39265	68	0	0
T12	12136	202	0	0
T13	462985	1081	0	0
T14	0	458	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	3086541	0	0
T1	521851	3001	0	0
T2	156266	561	0	0
T3	168551	1	0	0
T7	331905	34	0	0
T8	1991	33	0	0
T9	25110	407	0	0
T10	71504	1590	0	0
T11	39265	553	0	0
T12	12136	193	0	0
T13	462985	5460	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	205669	0	0
T1	521851	9	0	0
T2	156266	134	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	46	0	0
T10	71504	220	0	0
T11	39265	68	0	0
T12	12136	202	0	0
T13	462985	1081	0	0
T14	0	458	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	205669	0	0
T1	521851	9	0	0
T2	156266	134	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	46	0	0
T10	71504	220	0	0
T11	39265	68	0	0
T12	12136	202	0	0
T13	462985	1081	0	0
T14	0	458	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	545791	0	0
T1	521851	9	0	0
T2	156266	144	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	38	0	0
T9	25110	46	0	0
T10	71504	268	0	0
T11	39265	72	0	0
T12	12136	212	0	0
T13	462985	2826	0	0
T14	0	470	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	205669	0	0
T1	521851	9	0	0
T2	156266	134	0	0
T3	168551	0	0	0
T7	331905	11	0	0
T8	1991	35	0	0
T9	25110	46	0	0
T10	71504	220	0	0
T11	39265	68	0	0
T12	12136	202	0	0
T13	462985	1081	0	0
T14	0	458	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	857686	0	0
GntImpliesValid_A	394829365	857686	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	857686	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	11883913	0	0
ReadyAndValidImplyGrant_A	394829365	857686	0	0
ReqAndReadyImplyGrant_A	394829365	857686	0	0
ReqImpliesValid_A	394829365	2346303	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	19245	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	857686	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857686	0	0
T1	521851	51	0	0
T2	156266	598	0	0
T3	168551	375	0	0
T7	331905	41	0	0
T8	1991	185	0	0
T9	25110	222	0	0
T10	71504	851	0	0
T11	39265	243	0	0
T12	12136	871	0	0
T13	462985	4175	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857686	0	0
T1	521851	51	0	0
T2	156266	598	0	0
T3	168551	375	0	0
T7	331905	41	0	0
T8	1991	185	0	0
T9	25110	222	0	0
T10	71504	851	0	0
T11	39265	243	0	0
T12	12136	871	0	0
T13	462985	4175	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857686	0	0
T1	521851	51	0	0
T2	156266	598	0	0
T3	168551	375	0	0
T7	331905	41	0	0
T8	1991	185	0	0
T9	25110	222	0	0
T10	71504	851	0	0
T11	39265	243	0	0
T12	12136	871	0	0
T13	462985	4175	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	11883913	0	0
T1	521851	17073	0	0
T2	156266	1946	0	0
T3	168551	1273	0	0
T7	331905	158	0	0
T8	1991	1	0	0
T9	25110	1415	0	0
T10	71504	4552	0	0
T11	39265	1709	0	0
T12	12136	1	0	0
T13	462985	27233	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857686	0	0
T1	521851	51	0	0
T2	156266	598	0	0
T3	168551	375	0	0
T7	331905	41	0	0
T8	1991	185	0	0
T9	25110	222	0	0
T10	71504	851	0	0
T11	39265	243	0	0
T12	12136	871	0	0
T13	462985	4175	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857686	0	0
T1	521851	51	0	0
T2	156266	598	0	0
T3	168551	375	0	0
T7	331905	41	0	0
T8	1991	185	0	0
T9	25110	222	0	0
T10	71504	851	0	0
T11	39265	243	0	0
T12	12136	871	0	0
T13	462985	4175	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	2346303	0	0
T1	521851	51	0	0
T2	156266	763	0	0
T3	168551	504	0	0
T7	331905	47	0	0
T8	1991	185	0	0
T9	25110	265	0	0
T10	71504	1549	0	0
T11	39265	383	0	0
T12	12136	871	0	0
T13	462985	6578	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	19245	0	900
T8	1991	4	0	1
T9	25110	0	0	1
T10	71504	0	0	1
T11	39265	0	0	1
T12	12136	17	0	1
T13	462985	2	0	1
T14	61325	25	0	1
T15	14914	7	0	1
T16	0	1	0	0
T17	0	574	0	0
T18	0	5	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	1879	0	0	1
T23	1683	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857686	0	0
T1	521851	51	0	0
T2	156266	598	0	0
T3	168551	375	0	0
T7	331905	41	0	0
T8	1991	185	0	0
T9	25110	222	0	0
T10	71504	851	0	0
T11	39265	243	0	0
T12	12136	871	0	0
T13	462985	4175	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394829365	394695593	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	394829365	857091	0	0
GntImpliesValid_A	394829365	857091	0	0
GrantKnown_A	394829365	394695593	0	0
IdxKnown_A	394829365	394695593	0	0
IndexIsCorrect_A	394829365	857091	0	0
LockArbDecision_A	394829365	0	0	0
NoReadyValidNoGrant_A	394829365	331963874	0	0
ReadyAndValidImplyGrant_A	394829365	857091	0	0
ReqAndReadyImplyGrant_A	394829365	857091	0	0
ReqImpliesValid_A	394829365	13745625	0	0
ReqStaysHighUntilGranted0_M	394829365	0	0	0
RoundRobin_A	394829365	26834	0	900
ValidKnown_A	394829365	394695593	0	0
gen_data_port_assertion.DataFlow_A	394829365	857091	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857091	0	0
T1	521851	61	0	0
T2	156266	574	0	0
T3	168551	395	0	0
T7	331905	47	0	0
T8	1991	153	0	0
T9	25110	208	0	0
T10	71504	832	0	0
T11	39265	227	0	0
T12	12136	813	0	0
T13	462985	6828	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857091	0	0
T1	521851	61	0	0
T2	156266	574	0	0
T3	168551	395	0	0
T7	331905	47	0	0
T8	1991	153	0	0
T9	25110	208	0	0
T10	71504	832	0	0
T11	39265	227	0	0
T12	12136	813	0	0
T13	462985	6828	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857091	0	0
T1	521851	61	0	0
T2	156266	574	0	0
T3	168551	395	0	0
T7	331905	47	0	0
T8	1991	153	0	0
T9	25110	208	0	0
T10	71504	832	0	0
T11	39265	227	0	0
T12	12136	813	0	0
T13	462985	6828	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	331963874	0	0
T1	521851	492374	0	0
T2	156266	130010	0	0
T3	168551	140341	0	0
T7	331905	276268	0	0
T8	1991	1	0	0
T9	25110	20073	0	0
T10	71504	57449	0	0
T11	39265	34062	0	0
T12	12136	1	0	0
T13	462985	366935	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857091	0	0
T1	521851	61	0	0
T2	156266	574	0	0
T3	168551	395	0	0
T7	331905	47	0	0
T8	1991	153	0	0
T9	25110	208	0	0
T10	71504	832	0	0
T11	39265	227	0	0
T12	12136	813	0	0
T13	462985	6828	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857091	0	0
T1	521851	61	0	0
T2	156266	574	0	0
T3	168551	395	0	0
T7	331905	47	0	0
T8	1991	153	0	0
T9	25110	208	0	0
T10	71504	832	0	0
T11	39265	227	0	0
T12	12136	813	0	0
T13	462985	6828	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	13745625	0	0
T1	521851	20582	0	0
T2	156266	2494	0	0
T3	168551	1796	0	0
T7	331905	197	0	0
T8	1991	153	0	0
T9	25110	1531	0	0
T10	71504	6044	0	0
T11	39265	1766	0	0
T12	12136	813	0	0
T13	462985	60822	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	26834	0	900
T8	1991	3	0	1
T9	25110	0	0	1
T10	71504	2	0	1
T11	39265	0	0	1
T12	12136	12	0	1
T13	462985	84	0	1
T14	61325	20	0	1
T15	14914	6	0	1
T17	0	96	0	0
T18	0	3	0	0
T20	0	3	0	0
T21	0	12	0	0
T22	1879	0	0	1
T23	1683	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	394695593	0	0
T1	521851	521820	0	0
T2	156266	156259	0	0
T3	168551	168547	0	0
T7	331905	331809	0	0
T8	1991	1982	0	0
T9	25110	24201	0	0
T10	71504	71497	0	0
T11	39265	39191	0	0
T12	12136	12104	0	0
T13	462985	462823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394829365	857091	0	0
T1	521851	61	0	0
T2	156266	574	0	0
T3	168551	395	0	0
T7	331905	47	0	0
T8	1991	153	0	0
T9	25110	208	0	0
T10	71504	832	0	0
T11	39265	227	0	0
T12	12136	813	0	0
T13	462985	6828	0	0