Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1555713	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247179

1

T1

200

T2

167

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	612165	1			T1	475		T2	403		T3	64
values[0x0]	578654	1			T1	494		T2	409		T3	55
values[0x1]	612073	1			T1	528		T2	403		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1202268	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

600624

1

T1

481

T2

417

T3

57

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27316	1			T1	35		T2	21		T3	9
valid_sources[0x01]	28449	1			T1	27		T2	33		T8	7
valid_sources[0x02]	28091	1			T1	24		T2	19		T3	28
valid_sources[0x03]	27915	1			T1	23		T2	34		T8	6
valid_sources[0x04]	27573	1			T1	42		T2	20		T8	2
valid_sources[0x05]	28262	1			T1	22		T2	24		T3	8
valid_sources[0x06]	27444	1			T1	32		T2	17		T8	37
valid_sources[0x07]	28428	1			T1	28		T2	18		T3	7
valid_sources[0x08]	28974	1			T1	21		T2	20		T8	22
valid_sources[0x09]	28076	1			T1	38		T2	10		T8	35
valid_sources[0x0a]	27812	1			T1	31		T2	11		T3	8
valid_sources[0x0b]	28430	1			T1	19		T2	23		T3	5
valid_sources[0x0c]	27913	1			T1	27		T2	19		T3	9
valid_sources[0x0d]	28284	1			T1	18		T2	16		T8	21
valid_sources[0x0e]	27575	1			T1	18		T2	16		T8	5
valid_sources[0x0f]	27846	1			T1	17		T2	24		T8	3
valid_sources[0x10]	28109	1			T1	32		T2	21		T3	2
valid_sources[0x11]	27551	1			T1	15		T2	9		T8	12
valid_sources[0x12]	28196	1			T1	16		T2	24		T3	5
valid_sources[0x13]	29133	1			T1	24		T2	19		T3	5
valid_sources[0x14]	28679	1			T1	14		T2	17		T3	5
valid_sources[0x15]	28088	1			T1	22		T2	14		T8	3
valid_sources[0x16]	28901	1			T1	18		T2	20		T3	5
valid_sources[0x17]	29836	1			T1	45		T2	16		T3	1
valid_sources[0x18]	27547	1			T1	17		T2	14		T3	1
valid_sources[0x19]	27927	1			T1	25		T2	15		T8	11
valid_sources[0x1a]	28483	1			T1	31		T2	16		T8	13
valid_sources[0x1b]	27583	1			T1	25		T2	16		T8	9
valid_sources[0x1c]	28814	1			T1	14		T2	23		T8	17
valid_sources[0x1d]	28877	1			T1	27		T2	25		T8	5
valid_sources[0x1e]	28398	1			T1	17		T2	14		T8	11
valid_sources[0x1f]	28357	1			T1	12		T2	25		T3	1
valid_sources[0x20]	27641	1			T1	10		T2	13		T8	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25998

1

T1

19

T2

11

T3

5

values[0x0]

all_enables

biggest_size

195109

1

T1

159

T2

140

T3

16

values[0x1]

all_enables

biggest_size

26072

1

T1

22

T2

16

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1577568	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255709

1

T1

227

T2

169

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	627543	1			T1	494		T2	410		T3	50
values[0x0]	578081	1			T1	492		T2	397		T3	42
values[0x1]	627653	1			T1	470		T2	412		T3	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1211179	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

622098

1

T1

498

T2

392

T3

43

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28328	1			T1	24		T2	30		T8	8
valid_sources[0x01]	28546	1			T1	28		T2	11		T3	5
valid_sources[0x02]	28445	1			T1	11		T2	22		T3	5
valid_sources[0x03]	28833	1			T1	14		T2	12		T3	8
valid_sources[0x04]	28876	1			T1	34		T2	14		T8	11
valid_sources[0x05]	29420	1			T1	15		T2	25		T3	3
valid_sources[0x06]	28614	1			T1	21		T2	31		T8	6
valid_sources[0x07]	28726	1			T1	17		T2	28		T3	3
valid_sources[0x08]	29643	1			T1	19		T2	18		T3	8
valid_sources[0x09]	30102	1			T1	25		T2	12		T3	1
valid_sources[0x0a]	29090	1			T1	26		T2	16		T3	1
valid_sources[0x0b]	28903	1			T1	18		T2	14		T3	2
valid_sources[0x0c]	28346	1			T1	21		T2	11		T3	1
valid_sources[0x0d]	29442	1			T1	14		T2	17		T3	9
valid_sources[0x0e]	28865	1			T1	30		T2	14		T8	9
valid_sources[0x0f]	28493	1			T1	35		T2	11		T3	3
valid_sources[0x10]	28931	1			T1	12		T2	10		T8	11
valid_sources[0x11]	28430	1			T1	35		T2	23		T8	7
valid_sources[0x12]	29179	1			T1	25		T2	28		T3	1
valid_sources[0x13]	28442	1			T1	30		T2	30		T8	8
valid_sources[0x14]	28369	1			T1	16		T2	26		T3	2
valid_sources[0x15]	29094	1			T1	34		T2	19		T3	6
valid_sources[0x16]	28000	1			T1	18		T2	18		T3	1
valid_sources[0x17]	28392	1			T1	19		T2	26		T8	12
valid_sources[0x18]	28731	1			T1	17		T2	24		T8	5
valid_sources[0x19]	28857	1			T1	18		T2	20		T3	1
valid_sources[0x1a]	29036	1			T1	27		T2	45		T8	9
valid_sources[0x1b]	28673	1			T1	23		T2	18		T8	18
valid_sources[0x1c]	28804	1			T1	33		T2	8		T8	9
valid_sources[0x1d]	28489	1			T1	11		T2	13		T3	1
valid_sources[0x1e]	28402	1			T1	31		T2	20		T3	3
valid_sources[0x1f]	28277	1			T1	25		T2	12		T8	4
valid_sources[0x20]	28561	1			T1	21		T2	21		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26927

1

T1

25

T2

16

T3

3

values[0x0]

all_enables

biggest_size

202036

1

T1

185

T2

139

T3

16

values[0x1]

all_enables

biggest_size

26746

1

T1

17

T2

14

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1570931	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

250261

1

T1

201

T2

199

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	617838	1			T1	455		T2	435		T3	36
values[0x0]	585750	1			T1	481		T2	437		T3	39
values[0x1]	617604	1			T1	491		T2	441		T3	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1214346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

606846

1

T1

467

T2

454

T3

37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28335	1			T1	22		T2	27		T8	10
valid_sources[0x01]	29295	1			T1	21		T2	14		T8	14
valid_sources[0x02]	27187	1			T1	35		T2	27		T3	5
valid_sources[0x03]	28651	1			T1	22		T2	30		T8	9
valid_sources[0x04]	28496	1			T1	16		T2	20		T8	13
valid_sources[0x05]	28568	1			T1	18		T2	31		T8	10
valid_sources[0x06]	28821	1			T1	27		T2	20		T3	6
valid_sources[0x07]	28359	1			T1	27		T2	8		T3	1
valid_sources[0x08]	28629	1			T1	24		T2	14		T3	3
valid_sources[0x09]	29172	1			T1	26		T2	24		T3	3
valid_sources[0x0a]	28924	1			T1	23		T2	11		T8	9
valid_sources[0x0b]	29381	1			T1	25		T2	14		T8	13
valid_sources[0x0c]	27996	1			T1	20		T2	15		T3	4
valid_sources[0x0d]	28795	1			T1	20		T2	17		T8	6
valid_sources[0x0e]	28690	1			T1	30		T2	24		T3	20
valid_sources[0x0f]	28173	1			T1	20		T2	25		T8	9
valid_sources[0x10]	29034	1			T1	21		T2	24		T8	8
valid_sources[0x11]	27881	1			T1	18		T2	24		T3	6
valid_sources[0x12]	28655	1			T1	24		T2	14		T8	4
valid_sources[0x13]	27748	1			T1	26		T2	18		T8	7
valid_sources[0x14]	28676	1			T1	18		T2	18		T8	9
valid_sources[0x15]	28798	1			T1	25		T2	24		T8	4
valid_sources[0x16]	28261	1			T1	24		T2	25		T3	1
valid_sources[0x17]	28436	1			T1	8		T2	26		T8	18
valid_sources[0x18]	28765	1			T1	21		T2	27		T8	8
valid_sources[0x19]	28451	1			T1	25		T2	23		T3	1
valid_sources[0x1a]	28513	1			T1	18		T2	24		T8	12
valid_sources[0x1b]	28751	1			T1	28		T2	33		T3	5
valid_sources[0x1c]	27751	1			T1	25		T2	20		T3	5
valid_sources[0x1d]	28506	1			T1	20		T2	24		T8	14
valid_sources[0x1e]	28291	1			T1	24		T2	9		T8	10
valid_sources[0x1f]	28258	1			T1	19		T2	27		T8	6
valid_sources[0x20]	28329	1			T1	20		T2	16		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26160

1

T1

16

T2

29

T3

1

values[0x0]

all_enables

biggest_size

197839

1

T1

154

T2

158

T3

9

values[0x1]

all_enables

biggest_size

26262

1

T1

31

T2

12

T3

1