Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7941416	0	0
GntImpliesValid_A	2147483647	7941416	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7941416	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	458493525	0	0
ReadyAndValidImplyGrant_A	2147483647	7941416	0	0
ReqAndReadyImplyGrant_A	2147483647	7941416	0	0
ReqImpliesValid_A	2147483647	34360497	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50068	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7941416	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1203144	1202352	0	0
T2	131400	131256	0	0
T3	308088	306960	0	0
T4	253896	252432	0	0
T7	217224	216048	0	0
T8	1362648	1360992	0	0
T9	1493832	1430472	0	0
T10	106824	104784	0	0
T11	7163088	7129344	0	0
T12	435912	435264	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7941416	0	0
T1	350917	4380	0	0
T2	131400	3746	0	0
T3	308088	438	0	0
T4	253896	5889	0	0
T7	217224	337	0	0
T8	1362648	32458	0	0
T9	1493832	6234	0	0
T10	106824	3101	0	0
T11	7163088	27353	0	0
T12	435912	2122	0	0
T13	229245	261	0	0
T14	0	220	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7941416	0	0
T1	350917	4380	0	0
T2	131400	3746	0	0
T3	308088	438	0	0
T4	253896	5889	0	0
T7	217224	337	0	0
T8	1362648	32458	0	0
T9	1493832	6234	0	0
T10	106824	3101	0	0
T11	7163088	27353	0	0
T12	435912	2122	0	0
T13	229245	261	0	0
T14	0	220	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1203144	1202352	0	0
T2	131400	131256	0	0
T3	308088	306960	0	0
T4	253896	252432	0	0
T7	217224	216048	0	0
T8	1362648	1360992	0	0
T9	1493832	1430472	0	0
T10	106824	104784	0	0
T11	7163088	7129344	0	0
T12	435912	435264	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1203144	1202352	0	0
T2	131400	131256	0	0
T3	308088	306960	0	0
T4	253896	252432	0	0
T7	217224	216048	0	0
T8	1362648	1360992	0	0
T9	1493832	1430472	0	0
T10	106824	104784	0	0
T11	7163088	7129344	0	0
T12	435912	435264	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7941416	0	0
T1	350917	4380	0	0
T2	131400	3746	0	0
T3	308088	438	0	0
T4	253896	5889	0	0
T7	217224	337	0	0
T8	1362648	32458	0	0
T9	1493832	6234	0	0
T10	106824	3101	0	0
T11	7163088	27353	0	0
T12	435912	2122	0	0
T13	229245	261	0	0
T14	0	220	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	458493525	0	0
T1	1052751	46847	0	0
T2	131400	3483	0	0
T3	308088	15090	0	0
T4	253896	7382	0	0
T7	217224	10554	0	0
T8	1362648	27398	0	0
T9	1493832	79368	0	0
T10	106824	2878	0	0
T11	7163088	440803	0	0
T12	435912	21631	0	0
T13	40455	974	0	0
T14	0	726	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7941416	0	0
T1	350917	4380	0	0
T2	131400	3746	0	0
T3	308088	438	0	0
T4	253896	5889	0	0
T7	217224	337	0	0
T8	1362648	32458	0	0
T9	1493832	6234	0	0
T10	106824	3101	0	0
T11	7163088	27353	0	0
T12	435912	2122	0	0
T13	229245	261	0	0
T14	0	220	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7941416	0	0
T1	350917	4380	0	0
T2	131400	3746	0	0
T3	308088	438	0	0
T4	253896	5889	0	0
T7	217224	337	0	0
T8	1362648	32458	0	0
T9	1493832	6234	0	0
T10	106824	3101	0	0
T11	7163088	27353	0	0
T12	435912	2122	0	0
T13	229245	261	0	0
T14	0	220	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34360497	0	0
T1	350917	39106	0	0
T2	131400	4226	0	0
T3	308088	932	0	0
T4	253896	6983	0	0
T7	217224	664	0	0
T8	1362648	38861	0	0
T9	1493832	23675	0	0
T10	106824	3769	0	0
T11	7163088	58534	0	0
T12	435912	15382	0	0
T13	229245	443	0	0
T14	0	289	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50068	0	21600
T1	50131	17	0	1
T2	10950	21	0	2
T3	25674	0	0	2
T4	21158	26	0	2
T7	18102	0	0	2
T8	113554	369	0	2
T9	124486	33	0	2
T10	8902	5	0	2
T11	596924	7	0	2
T12	36326	0	0	2
T13	13485	0	0	1
T15	0	9	0	0
T16	0	322	0	0
T17	0	47	0	0
T18	0	21	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1203144	1202352	0	0
T2	131400	131256	0	0
T3	308088	306960	0	0
T4	253896	252432	0	0
T7	217224	216048	0	0
T8	1362648	1360992	0	0
T9	1493832	1430472	0	0
T10	106824	104784	0	0
T11	7163088	7129344	0	0
T12	435912	435264	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7941416	0	0
T1	350917	4380	0	0
T2	131400	3746	0	0
T3	308088	438	0	0
T4	253896	5889	0	0
T7	217224	337	0	0
T8	1362648	32458	0	0
T9	1493832	6234	0	0
T10	106824	3101	0	0
T11	7163088	27353	0	0
T12	435912	2122	0	0
T13	229245	261	0	0
T14	0	220	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	914815	0	0
GntImpliesValid_A	425848891	914815	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	914815	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	11656428	0	0
ReadyAndValidImplyGrant_A	425848891	914815	0	0
ReqAndReadyImplyGrant_A	425848891	914815	0	0
ReqImpliesValid_A	425848891	2591735	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	914815	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	914815	0	0
T1	50131	1582	0	0
T2	5475	412	0	0
T3	12837	54	0	0
T4	10579	600	0	0
T7	9051	37	0	0
T8	56777	3227	0	0
T9	62243	719	0	0
T10	4451	349	0	0
T11	298462	3670	0	0
T12	18163	204	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	914815	0	0
T1	50131	1582	0	0
T2	5475	412	0	0
T3	12837	54	0	0
T4	10579	600	0	0
T7	9051	37	0	0
T8	56777	3227	0	0
T9	62243	719	0	0
T10	4451	349	0	0
T11	298462	3670	0	0
T12	18163	204	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	914815	0	0
T1	50131	1582	0	0
T2	5475	412	0	0
T3	12837	54	0	0
T4	10579	600	0	0
T7	9051	37	0	0
T8	56777	3227	0	0
T9	62243	719	0	0
T10	4451	349	0	0
T11	298462	3670	0	0
T12	18163	204	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	11656428	0	0
T1	50131	3199	0	0
T2	5475	298	0	0
T3	12837	466	0	0
T4	10579	446	0	0
T7	9051	319	0	0
T8	56777	2691	0	0
T9	62243	3962	0	0
T10	4451	253	0	0
T11	298462	24052	0	0
T12	18163	1445	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	914815	0	0
T1	50131	1582	0	0
T2	5475	412	0	0
T3	12837	54	0	0
T4	10579	600	0	0
T7	9051	37	0	0
T8	56777	3227	0	0
T9	62243	719	0	0
T10	4451	349	0	0
T11	298462	3670	0	0
T12	18163	204	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	914815	0	0
T1	50131	1582	0	0
T2	5475	412	0	0
T3	12837	54	0	0
T4	10579	600	0	0
T7	9051	37	0	0
T8	56777	3227	0	0
T9	62243	719	0	0
T10	4451	349	0	0
T11	298462	3670	0	0
T12	18163	204	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2591735	0	0
T1	50131	14318	0	0
T2	5475	527	0	0
T3	12837	90	0	0
T4	10579	755	0	0
T7	9051	60	0	0
T8	56777	3766	0	0
T9	62243	1739	0	0
T10	4451	447	0	0
T11	298462	7018	0	0
T12	18163	359	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	914815	0	0
T1	50131	1582	0	0
T2	5475	412	0	0
T3	12837	54	0	0
T4	10579	600	0	0
T7	9051	37	0	0
T8	56777	3227	0	0
T9	62243	719	0	0
T10	4451	349	0	0
T11	298462	3670	0	0
T12	18163	204	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	866314	0	0
GntImpliesValid_A	425848891	866314	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	866314	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	11552004	0	0
ReadyAndValidImplyGrant_A	425848891	866314	0	0
ReqAndReadyImplyGrant_A	425848891	866314	0	0
ReqImpliesValid_A	425848891	2340852	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	866314	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	866314	0	0
T1	50131	231	0	0
T2	5475	406	0	0
T3	12837	58	0	0
T4	10579	661	0	0
T7	9051	37	0	0
T8	56777	4158	0	0
T9	62243	540	0	0
T10	4451	379	0	0
T11	298462	3086	0	0
T12	18163	184	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	866314	0	0
T1	50131	231	0	0
T2	5475	406	0	0
T3	12837	58	0	0
T4	10579	661	0	0
T7	9051	37	0	0
T8	56777	4158	0	0
T9	62243	540	0	0
T10	4451	379	0	0
T11	298462	3086	0	0
T12	18163	184	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	866314	0	0
T1	50131	231	0	0
T2	5475	406	0	0
T3	12837	58	0	0
T4	10579	661	0	0
T7	9051	37	0	0
T8	56777	4158	0	0
T9	62243	540	0	0
T10	4451	379	0	0
T11	298462	3086	0	0
T12	18163	184	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	11552004	0	0
T1	50131	1651	0	0
T2	5475	301	0	0
T3	12837	437	0	0
T4	10579	476	0	0
T7	9051	278	0	0
T8	56777	3109	0	0
T9	62243	4048	0	0
T10	4451	279	0	0
T11	298462	21566	0	0
T12	18163	1301	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	866314	0	0
T1	50131	231	0	0
T2	5475	406	0	0
T3	12837	58	0	0
T4	10579	661	0	0
T7	9051	37	0	0
T8	56777	4158	0	0
T9	62243	540	0	0
T10	4451	379	0	0
T11	298462	3086	0	0
T12	18163	184	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	866314	0	0
T1	50131	231	0	0
T2	5475	406	0	0
T3	12837	58	0	0
T4	10579	661	0	0
T7	9051	37	0	0
T8	56777	4158	0	0
T9	62243	540	0	0
T10	4451	379	0	0
T11	298462	3086	0	0
T12	18163	184	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2340852	0	0
T1	50131	400	0	0
T2	5475	512	0	0
T3	12837	99	0	0
T4	10579	847	0	0
T7	9051	79	0	0
T8	56777	5210	0	0
T9	62243	872	0	0
T10	4451	481	0	0
T11	298462	5876	0	0
T12	18163	278	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	866314	0	0
T1	50131	231	0	0
T2	5475	406	0	0
T3	12837	58	0	0
T4	10579	661	0	0
T7	9051	37	0	0
T8	56777	4158	0	0
T9	62243	540	0	0
T10	4451	379	0	0
T11	298462	3086	0	0
T12	18163	184	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	208349	0	0
GntImpliesValid_A	425848891	208349	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	208349	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2745521	0	0
ReadyAndValidImplyGrant_A	425848891	208349	0	0
ReqAndReadyImplyGrant_A	425848891	208349	0	0
ReqImpliesValid_A	425848891	522729	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	208349	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208349	0	0
T2	5475	121	0	0
T3	12837	21	0	0
T4	10579	150	0	0
T7	9051	12	0	0
T8	56777	627	0	0
T9	62243	74	0	0
T10	4451	45	0	0
T11	298462	751	0	0
T12	18163	1016	0	0
T13	13485	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208349	0	0
T2	5475	121	0	0
T3	12837	21	0	0
T4	10579	150	0	0
T7	9051	12	0	0
T8	56777	627	0	0
T9	62243	74	0	0
T10	4451	45	0	0
T11	298462	751	0	0
T12	18163	1016	0	0
T13	13485	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208349	0	0
T2	5475	121	0	0
T3	12837	21	0	0
T4	10579	150	0	0
T7	9051	12	0	0
T8	56777	627	0	0
T9	62243	74	0	0
T10	4451	45	0	0
T11	298462	751	0	0
T12	18163	1016	0	0
T13	13485	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2745521	0	0
T1	50131	1	0	0
T2	5475	113	0	0
T3	12837	123	0	0
T4	10579	148	0	0
T7	9051	98	0	0
T8	56777	601	0	0
T9	62243	596	0	0
T10	4451	47	0	0
T11	298462	5717	0	0
T12	18163	2011	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208349	0	0
T2	5475	121	0	0
T3	12837	21	0	0
T4	10579	150	0	0
T7	9051	12	0	0
T8	56777	627	0	0
T9	62243	74	0	0
T10	4451	45	0	0
T11	298462	751	0	0
T12	18163	1016	0	0
T13	13485	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208349	0	0
T2	5475	121	0	0
T3	12837	21	0	0
T4	10579	150	0	0
T7	9051	12	0	0
T8	56777	627	0	0
T9	62243	74	0	0
T10	4451	45	0	0
T11	298462	751	0	0
T12	18163	1016	0	0
T13	13485	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	522729	0	0
T2	5475	130	0	0
T3	12837	21	0	0
T4	10579	153	0	0
T7	9051	12	0	0
T8	56777	656	0	0
T9	62243	75	0	0
T10	4451	45	0	0
T11	298462	912	0	0
T12	18163	9302	0	0
T13	13485	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208349	0	0
T2	5475	121	0	0
T3	12837	21	0	0
T4	10579	150	0	0
T7	9051	12	0	0
T8	56777	627	0	0
T9	62243	74	0	0
T10	4451	45	0	0
T11	298462	751	0	0
T12	18163	1016	0	0
T13	13485	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T10
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	222214	0	0
GntImpliesValid_A	425848891	222214	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	222214	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2850761	0	0
ReadyAndValidImplyGrant_A	425848891	222214	0	0
ReqAndReadyImplyGrant_A	425848891	222214	0	0
ReqImpliesValid_A	425848891	597309	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	222214	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	222214	0	0
T2	5475	92	0	0
T3	12837	11	0	0
T4	10579	144	0	0
T7	9051	6	0	0
T8	56777	627	0	0
T9	62243	89	0	0
T10	4451	583	0	0
T11	298462	839	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	25	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	222214	0	0
T2	5475	92	0	0
T3	12837	11	0	0
T4	10579	144	0	0
T7	9051	6	0	0
T8	56777	627	0	0
T9	62243	89	0	0
T10	4451	583	0	0
T11	298462	839	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	25	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	222214	0	0
T2	5475	92	0	0
T3	12837	11	0	0
T4	10579	144	0	0
T7	9051	6	0	0
T8	56777	627	0	0
T9	62243	89	0	0
T10	4451	583	0	0
T11	298462	839	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	25	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2850761	0	0
T1	50131	1	0	0
T2	5475	87	0	0
T3	12837	109	0	0
T4	10579	136	0	0
T7	9051	54	0	0
T8	56777	608	0	0
T9	62243	675	0	0
T10	4451	502	0	0
T11	298462	5915	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	222214	0	0
T2	5475	92	0	0
T3	12837	11	0	0
T4	10579	144	0	0
T7	9051	6	0	0
T8	56777	627	0	0
T9	62243	89	0	0
T10	4451	583	0	0
T11	298462	839	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	25	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	222214	0	0
T2	5475	92	0	0
T3	12837	11	0	0
T4	10579	144	0	0
T7	9051	6	0	0
T8	56777	627	0	0
T9	62243	89	0	0
T10	4451	583	0	0
T11	298462	839	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	25	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	597309	0	0
T2	5475	98	0	0
T3	12837	11	0	0
T4	10579	153	0	0
T7	9051	6	0	0
T8	56777	649	0	0
T9	62243	89	0	0
T10	4451	666	0	0
T11	298462	1170	0	0
T12	18163	0	0	0
T13	13485	35	0	0
T14	0	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	222214	0	0
T2	5475	92	0	0
T3	12837	11	0	0
T4	10579	144	0	0
T7	9051	6	0	0
T8	56777	627	0	0
T9	62243	89	0	0
T10	4451	583	0	0
T11	298462	839	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	25	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	211350	0	0
GntImpliesValid_A	425848891	211350	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	211350	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	5423687	0	0
ReadyAndValidImplyGrant_A	425848891	211350	0	0
ReqAndReadyImplyGrant_A	425848891	211350	0	0
ReqImpliesValid_A	425848891	1216954	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	211350	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211350	0	0
T2	5475	95	0	0
T3	12837	7	0	0
T4	10579	150	0	0
T7	9051	9	0	0
T8	56777	652	0	0
T9	62243	468	0	0
T10	4451	39	0	0
T11	298462	678	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211350	0	0
T2	5475	95	0	0
T3	12837	7	0	0
T4	10579	150	0	0
T7	9051	9	0	0
T8	56777	652	0	0
T9	62243	468	0	0
T10	4451	39	0	0
T11	298462	678	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211350	0	0
T2	5475	95	0	0
T3	12837	7	0	0
T4	10579	150	0	0
T7	9051	9	0	0
T8	56777	652	0	0
T9	62243	468	0	0
T10	4451	39	0	0
T11	298462	678	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	5423687	0	0
T2	5475	313	0	0
T3	12837	109	0	0
T4	10579	1189	0	0
T7	9051	101	0	0
T8	56777	2735	0	0
T9	62243	4027	0	0
T10	4451	194	0	0
T11	298462	14425	0	0
T12	18163	0	0	0
T13	13485	190	0	0
T14	0	298	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211350	0	0
T2	5475	95	0	0
T3	12837	7	0	0
T4	10579	150	0	0
T7	9051	9	0	0
T8	56777	652	0	0
T9	62243	468	0	0
T10	4451	39	0	0
T11	298462	678	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211350	0	0
T2	5475	95	0	0
T3	12837	7	0	0
T4	10579	150	0	0
T7	9051	9	0	0
T8	56777	652	0	0
T9	62243	468	0	0
T10	4451	39	0	0
T11	298462	678	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	1216954	0	0
T2	5475	143	0	0
T3	12837	22	0	0
T4	10579	328	0	0
T7	9051	9	0	0
T8	56777	806	0	0
T9	62243	1758	0	0
T10	4451	45	0	0
T11	298462	1409	0	0
T12	18163	0	0	0
T13	13485	41	0	0
T14	0	34	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211350	0	0
T2	5475	95	0	0
T3	12837	7	0	0
T4	10579	150	0	0
T7	9051	9	0	0
T8	56777	652	0	0
T9	62243	468	0	0
T10	4451	39	0	0
T11	298462	678	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	214656	0	0
GntImpliesValid_A	425848891	214656	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	214656	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	5210938	0	0
ReadyAndValidImplyGrant_A	425848891	214656	0	0
ReqAndReadyImplyGrant_A	425848891	214656	0	0
ReqImpliesValid_A	425848891	1216292	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	214656	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	214656	0	0
T2	5475	107	0	0
T3	12837	13	0	0
T4	10579	173	0	0
T7	9051	10	0	0
T8	56777	604	0	0
T9	62243	88	0	0
T10	4451	37	0	0
T11	298462	699	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	214656	0	0
T2	5475	107	0	0
T3	12837	13	0	0
T4	10579	173	0	0
T7	9051	10	0	0
T8	56777	604	0	0
T9	62243	88	0	0
T10	4451	37	0	0
T11	298462	699	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	214656	0	0
T2	5475	107	0	0
T3	12837	13	0	0
T4	10579	173	0	0
T7	9051	10	0	0
T8	56777	604	0	0
T9	62243	88	0	0
T10	4451	37	0	0
T11	298462	699	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	5210938	0	0
T2	5475	322	0	0
T3	12837	205	0	0
T4	10579	934	0	0
T7	9051	219	0	0
T8	56777	2251	0	0
T9	62243	1069	0	0
T10	4451	164	0	0
T11	298462	10353	0	0
T12	18163	0	0	0
T13	13485	338	0	0
T14	0	150	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	214656	0	0
T2	5475	107	0	0
T3	12837	13	0	0
T4	10579	173	0	0
T7	9051	10	0	0
T8	56777	604	0	0
T9	62243	88	0	0
T10	4451	37	0	0
T11	298462	699	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	214656	0	0
T2	5475	107	0	0
T3	12837	13	0	0
T4	10579	173	0	0
T7	9051	10	0	0
T8	56777	604	0	0
T9	62243	88	0	0
T10	4451	37	0	0
T11	298462	699	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	1216292	0	0
T2	5475	150	0	0
T3	12837	22	0	0
T4	10579	296	0	0
T7	9051	10	0	0
T8	56777	715	0	0
T9	62243	102	0	0
T10	4451	41	0	0
T11	298462	1033	0	0
T12	18163	0	0	0
T13	13485	49	0	0
T14	0	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	214656	0	0
T2	5475	107	0	0
T3	12837	13	0	0
T4	10579	173	0	0
T7	9051	10	0	0
T8	56777	604	0	0
T9	62243	88	0	0
T10	4451	37	0	0
T11	298462	699	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	216182	0	0
GntImpliesValid_A	425848891	216182	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	216182	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	5280240	0	0
ReadyAndValidImplyGrant_A	425848891	216182	0	0
ReqAndReadyImplyGrant_A	425848891	216182	0	0
ReqImpliesValid_A	425848891	1250022	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	216182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	216182	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	165	0	0
T7	9051	7	0	0
T8	56777	665	0	0
T9	62243	92	0	0
T10	4451	162	0	0
T11	298462	693	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	216182	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	165	0	0
T7	9051	7	0	0
T8	56777	665	0	0
T9	62243	92	0	0
T10	4451	162	0	0
T11	298462	693	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	216182	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	165	0	0
T7	9051	7	0	0
T8	56777	665	0	0
T9	62243	92	0	0
T10	4451	162	0	0
T11	298462	693	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	5280240	0	0
T2	5475	285	0	0
T3	12837	146	0	0
T4	10579	832	0	0
T7	9051	178	0	0
T8	56777	2736	0	0
T9	62243	1955	0	0
T10	4451	368	0	0
T11	298462	11047	0	0
T12	18163	0	0	0
T13	13485	204	0	0
T14	0	278	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	216182	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	165	0	0
T7	9051	7	0	0
T8	56777	665	0	0
T9	62243	92	0	0
T10	4451	162	0	0
T11	298462	693	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	216182	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	165	0	0
T7	9051	7	0	0
T8	56777	665	0	0
T9	62243	92	0	0
T10	4451	162	0	0
T11	298462	693	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	1250022	0	0
T2	5475	118	0	0
T3	12837	25	0	0
T4	10579	287	0	0
T7	9051	7	0	0
T8	56777	821	0	0
T9	62243	135	0	0
T10	4451	521	0	0
T11	298462	926	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	216182	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	165	0	0
T7	9051	7	0	0
T8	56777	665	0	0
T9	62243	92	0	0
T10	4451	162	0	0
T11	298462	693	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	226342	0	0
GntImpliesValid_A	425848891	226342	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	226342	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	5242830	0	0
ReadyAndValidImplyGrant_A	425848891	226342	0	0
ReqAndReadyImplyGrant_A	425848891	226342	0	0
ReqImpliesValid_A	425848891	1097459	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	226342	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	226342	0	0
T1	50131	485	0	0
T2	5475	108	0	0
T3	12837	13	0	0
T4	10579	172	0	0
T7	9051	17	0	0
T8	56777	653	0	0
T9	62243	79	0	0
T10	4451	52	0	0
T11	298462	749	0	0
T12	18163	0	0	0
T13	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	226342	0	0
T1	50131	485	0	0
T2	5475	108	0	0
T3	12837	13	0	0
T4	10579	172	0	0
T7	9051	17	0	0
T8	56777	653	0	0
T9	62243	79	0	0
T10	4451	52	0	0
T11	298462	749	0	0
T12	18163	0	0	0
T13	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	226342	0	0
T1	50131	485	0	0
T2	5475	108	0	0
T3	12837	13	0	0
T4	10579	172	0	0
T7	9051	17	0	0
T8	56777	653	0	0
T9	62243	79	0	0
T10	4451	52	0	0
T11	298462	749	0	0
T12	18163	0	0	0
T13	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	5242830	0	0
T1	50131	1442	0	0
T2	5475	324	0	0
T3	12837	560	0	0
T4	10579	1005	0	0
T7	9051	318	0	0
T8	56777	2580	0	0
T9	62243	931	0	0
T10	4451	314	0	0
T11	298462	7320	0	0
T12	18163	0	0	0
T13	0	242	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	226342	0	0
T1	50131	485	0	0
T2	5475	108	0	0
T3	12837	13	0	0
T4	10579	172	0	0
T7	9051	17	0	0
T8	56777	653	0	0
T9	62243	79	0	0
T10	4451	52	0	0
T11	298462	749	0	0
T12	18163	0	0	0
T13	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	226342	0	0
T1	50131	485	0	0
T2	5475	108	0	0
T3	12837	13	0	0
T4	10579	172	0	0
T7	9051	17	0	0
T8	56777	653	0	0
T9	62243	79	0	0
T10	4451	52	0	0
T11	298462	749	0	0
T12	18163	0	0	0
T13	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	1097459	0	0
T1	50131	5822	0	0
T2	5475	152	0	0
T3	12837	93	0	0
T4	10579	338	0	0
T7	9051	25	0	0
T8	56777	815	0	0
T9	62243	95	0	0
T10	4451	67	0	0
T11	298462	1078	0	0
T12	18163	0	0	0
T13	0	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	226342	0	0
T1	50131	485	0	0
T2	5475	108	0	0
T3	12837	13	0	0
T4	10579	172	0	0
T7	9051	17	0	0
T8	56777	653	0	0
T9	62243	79	0	0
T10	4451	52	0	0
T11	298462	749	0	0
T12	18163	0	0	0
T13	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	218583	0	0
GntImpliesValid_A	425848891	218583	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	218583	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2862715	0	0
ReadyAndValidImplyGrant_A	425848891	218583	0	0
ReqAndReadyImplyGrant_A	425848891	218583	0	0
ReqImpliesValid_A	425848891	590268	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	218583	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218583	0	0
T1	50131	438	0	0
T2	5475	131	0	0
T3	12837	11	0	0
T4	10579	195	0	0
T7	9051	11	0	0
T8	56777	1148	0	0
T9	62243	455	0	0
T10	4451	50	0	0
T11	298462	673	0	0
T12	18163	0	0	0
T13	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218583	0	0
T1	50131	438	0	0
T2	5475	131	0	0
T3	12837	11	0	0
T4	10579	195	0	0
T7	9051	11	0	0
T8	56777	1148	0	0
T9	62243	455	0	0
T10	4451	50	0	0
T11	298462	673	0	0
T12	18163	0	0	0
T13	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218583	0	0
T1	50131	438	0	0
T2	5475	131	0	0
T3	12837	11	0	0
T4	10579	195	0	0
T7	9051	11	0	0
T8	56777	1148	0	0
T9	62243	455	0	0
T10	4451	50	0	0
T11	298462	673	0	0
T12	18163	0	0	0
T13	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2862715	0	0
T1	50131	859	0	0
T2	5475	123	0	0
T3	12837	76	0	0
T4	10579	182	0	0
T7	9051	66	0	0
T8	56777	848	0	0
T9	62243	807	0	0
T10	4451	51	0	0
T11	298462	5141	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218583	0	0
T1	50131	438	0	0
T2	5475	131	0	0
T3	12837	11	0	0
T4	10579	195	0	0
T7	9051	11	0	0
T8	56777	1148	0	0
T9	62243	455	0	0
T10	4451	50	0	0
T11	298462	673	0	0
T12	18163	0	0	0
T13	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218583	0	0
T1	50131	438	0	0
T2	5475	131	0	0
T3	12837	11	0	0
T4	10579	195	0	0
T7	9051	11	0	0
T8	56777	1148	0	0
T9	62243	455	0	0
T10	4451	50	0	0
T11	298462	673	0	0
T12	18163	0	0	0
T13	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	590268	0	0
T1	50131	4300	0	0
T2	5475	140	0	0
T3	12837	11	0	0
T4	10579	209	0	0
T7	9051	18	0	0
T8	56777	1451	0	0
T9	62243	3972	0	0
T10	4451	51	0	0
T11	298462	834	0	0
T12	18163	0	0	0
T13	0	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218583	0	0
T1	50131	438	0	0
T2	5475	131	0	0
T3	12837	11	0	0
T4	10579	195	0	0
T7	9051	11	0	0
T8	56777	1148	0	0
T9	62243	455	0	0
T10	4451	50	0	0
T11	298462	673	0	0
T12	18163	0	0	0
T13	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	223896	0	0
GntImpliesValid_A	425848891	223896	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	223896	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2854694	0	0
ReadyAndValidImplyGrant_A	425848891	223896	0	0
ReqAndReadyImplyGrant_A	425848891	223896	0	0
ReqImpliesValid_A	425848891	608733	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	223896	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223896	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	159	0	0
T7	9051	5	0	0
T8	56777	1141	0	0
T9	62243	87	0	0
T10	4451	51	0	0
T11	298462	842	0	0
T12	18163	0	0	0
T13	13485	18	0	0
T14	0	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223896	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	159	0	0
T7	9051	5	0	0
T8	56777	1141	0	0
T9	62243	87	0	0
T10	4451	51	0	0
T11	298462	842	0	0
T12	18163	0	0	0
T13	13485	18	0	0
T14	0	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223896	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	159	0	0
T7	9051	5	0	0
T8	56777	1141	0	0
T9	62243	87	0	0
T10	4451	51	0	0
T11	298462	842	0	0
T12	18163	0	0	0
T13	13485	18	0	0
T14	0	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2854694	0	0
T1	50131	1	0	0
T2	5475	86	0	0
T3	12837	111	0	0
T4	10579	151	0	0
T7	9051	45	0	0
T8	56777	640	0	0
T9	62243	726	0	0
T10	4451	53	0	0
T11	298462	6178	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223896	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	159	0	0
T7	9051	5	0	0
T8	56777	1141	0	0
T9	62243	87	0	0
T10	4451	51	0	0
T11	298462	842	0	0
T12	18163	0	0	0
T13	13485	18	0	0
T14	0	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223896	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	159	0	0
T7	9051	5	0	0
T8	56777	1141	0	0
T9	62243	87	0	0
T10	4451	51	0	0
T11	298462	842	0	0
T12	18163	0	0	0
T13	13485	18	0	0
T14	0	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	608733	0	0
T2	5475	99	0	0
T3	12837	13	0	0
T4	10579	168	0	0
T7	9051	5	0	0
T8	56777	1645	0	0
T9	62243	100	0	0
T10	4451	51	0	0
T11	298462	1109	0	0
T12	18163	0	0	0
T13	13485	31	0	0
T14	0	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223896	0	0
T2	5475	92	0	0
T3	12837	13	0	0
T4	10579	159	0	0
T7	9051	5	0	0
T8	56777	1141	0	0
T9	62243	87	0	0
T10	4451	51	0	0
T11	298462	842	0	0
T12	18163	0	0	0
T13	13485	18	0	0
T14	0	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	223449	0	0
GntImpliesValid_A	425848891	223449	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	223449	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2872938	0	0
ReadyAndValidImplyGrant_A	425848891	223449	0	0
ReqAndReadyImplyGrant_A	425848891	223449	0	0
ReqImpliesValid_A	425848891	551783	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	223449	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223449	0	0
T2	5475	127	0	0
T3	12837	6	0	0
T4	10579	167	0	0
T7	9051	15	0	0
T8	56777	645	0	0
T9	62243	174	0	0
T10	4451	58	0	0
T11	298462	730	0	0
T12	18163	0	0	0
T13	13485	9	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223449	0	0
T2	5475	127	0	0
T3	12837	6	0	0
T4	10579	167	0	0
T7	9051	15	0	0
T8	56777	645	0	0
T9	62243	174	0	0
T10	4451	58	0	0
T11	298462	730	0	0
T12	18163	0	0	0
T13	13485	9	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223449	0	0
T2	5475	127	0	0
T3	12837	6	0	0
T4	10579	167	0	0
T7	9051	15	0	0
T8	56777	645	0	0
T9	62243	174	0	0
T10	4451	58	0	0
T11	298462	730	0	0
T12	18163	0	0	0
T13	13485	9	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2872938	0	0
T1	50131	1	0	0
T2	5475	121	0	0
T3	12837	62	0	0
T4	10579	149	0	0
T7	9051	114	0	0
T8	56777	633	0	0
T9	62243	1150	0	0
T10	4451	60	0	0
T11	298462	5272	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223449	0	0
T2	5475	127	0	0
T3	12837	6	0	0
T4	10579	167	0	0
T7	9051	15	0	0
T8	56777	645	0	0
T9	62243	174	0	0
T10	4451	58	0	0
T11	298462	730	0	0
T12	18163	0	0	0
T13	13485	9	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223449	0	0
T2	5475	127	0	0
T3	12837	6	0	0
T4	10579	167	0	0
T7	9051	15	0	0
T8	56777	645	0	0
T9	62243	174	0	0
T10	4451	58	0	0
T11	298462	730	0	0
T12	18163	0	0	0
T13	13485	9	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	551783	0	0
T2	5475	134	0	0
T3	12837	6	0	0
T4	10579	186	0	0
T7	9051	18	0	0
T8	56777	660	0	0
T9	62243	265	0	0
T10	4451	58	0	0
T11	298462	896	0	0
T12	18163	0	0	0
T13	13485	9	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	223449	0	0
T2	5475	127	0	0
T3	12837	6	0	0
T4	10579	167	0	0
T7	9051	15	0	0
T8	56777	645	0	0
T9	62243	174	0	0
T10	4451	58	0	0
T11	298462	730	0	0
T12	18163	0	0	0
T13	13485	9	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	208996	0	0
GntImpliesValid_A	425848891	208996	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	208996	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2908058	0	0
ReadyAndValidImplyGrant_A	425848891	208996	0	0
ReqAndReadyImplyGrant_A	425848891	208996	0	0
ReqImpliesValid_A	425848891	553335	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	208996	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208996	0	0
T2	5475	107	0	0
T3	12837	19	0	0
T4	10579	175	0	0
T7	9051	7	0	0
T8	56777	661	0	0
T9	62243	87	0	0
T10	4451	49	0	0
T11	298462	674	0	0
T12	18163	355	0	0
T13	13485	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208996	0	0
T2	5475	107	0	0
T3	12837	19	0	0
T4	10579	175	0	0
T7	9051	7	0	0
T8	56777	661	0	0
T9	62243	87	0	0
T10	4451	49	0	0
T11	298462	674	0	0
T12	18163	355	0	0
T13	13485	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208996	0	0
T2	5475	107	0	0
T3	12837	19	0	0
T4	10579	175	0	0
T7	9051	7	0	0
T8	56777	661	0	0
T9	62243	87	0	0
T10	4451	49	0	0
T11	298462	674	0	0
T12	18163	355	0	0
T13	13485	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2908058	0	0
T1	50131	1	0	0
T2	5475	100	0	0
T3	12837	197	0	0
T4	10579	169	0	0
T7	9051	37	0	0
T8	56777	649	0	0
T9	62243	624	0	0
T10	4451	51	0	0
T11	298462	4984	0	0
T12	18163	762	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208996	0	0
T2	5475	107	0	0
T3	12837	19	0	0
T4	10579	175	0	0
T7	9051	7	0	0
T8	56777	661	0	0
T9	62243	87	0	0
T10	4451	49	0	0
T11	298462	674	0	0
T12	18163	355	0	0
T13	13485	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208996	0	0
T2	5475	107	0	0
T3	12837	19	0	0
T4	10579	175	0	0
T7	9051	7	0	0
T8	56777	661	0	0
T9	62243	87	0	0
T10	4451	49	0	0
T11	298462	674	0	0
T12	18163	355	0	0
T13	13485	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	553335	0	0
T2	5475	115	0	0
T3	12837	19	0	0
T4	10579	182	0	0
T7	9051	7	0	0
T8	56777	676	0	0
T9	62243	94	0	0
T10	4451	49	0	0
T11	298462	851	0	0
T12	18163	3484	0	0
T13	13485	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208996	0	0
T2	5475	107	0	0
T3	12837	19	0	0
T4	10579	175	0	0
T7	9051	7	0	0
T8	56777	661	0	0
T9	62243	87	0	0
T10	4451	49	0	0
T11	298462	674	0	0
T12	18163	355	0	0
T13	13485	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	218889	0	0
GntImpliesValid_A	425848891	218889	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	218889	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2833908	0	0
ReadyAndValidImplyGrant_A	425848891	218889	0	0
ReqAndReadyImplyGrant_A	425848891	218889	0	0
ReqImpliesValid_A	425848891	596348	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	218889	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218889	0	0
T2	5475	121	0	0
T3	12837	15	0	0
T4	10579	164	0	0
T7	9051	10	0	0
T8	56777	1130	0	0
T9	62243	434	0	0
T10	4451	42	0	0
T11	298462	1063	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218889	0	0
T2	5475	121	0	0
T3	12837	15	0	0
T4	10579	164	0	0
T7	9051	10	0	0
T8	56777	1130	0	0
T9	62243	434	0	0
T10	4451	42	0	0
T11	298462	1063	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218889	0	0
T2	5475	121	0	0
T3	12837	15	0	0
T4	10579	164	0	0
T7	9051	10	0	0
T8	56777	1130	0	0
T9	62243	434	0	0
T10	4451	42	0	0
T11	298462	1063	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2833908	0	0
T1	50131	1	0	0
T2	5475	116	0	0
T3	12837	105	0	0
T4	10579	152	0	0
T7	9051	78	0	0
T8	56777	712	0	0
T9	62243	2213	0	0
T10	4451	44	0	0
T11	298462	7775	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218889	0	0
T2	5475	121	0	0
T3	12837	15	0	0
T4	10579	164	0	0
T7	9051	10	0	0
T8	56777	1130	0	0
T9	62243	434	0	0
T10	4451	42	0	0
T11	298462	1063	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218889	0	0
T2	5475	121	0	0
T3	12837	15	0	0
T4	10579	164	0	0
T7	9051	10	0	0
T8	56777	1130	0	0
T9	62243	434	0	0
T10	4451	42	0	0
T11	298462	1063	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	596348	0	0
T2	5475	127	0	0
T3	12837	15	0	0
T4	10579	177	0	0
T7	9051	20	0	0
T8	56777	1551	0	0
T9	62243	2065	0	0
T10	4451	42	0	0
T11	298462	1918	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	218889	0	0
T2	5475	121	0	0
T3	12837	15	0	0
T4	10579	164	0	0
T7	9051	10	0	0
T8	56777	1130	0	0
T9	62243	434	0	0
T10	4451	42	0	0
T11	298462	1063	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	225001	0	0
GntImpliesValid_A	425848891	225001	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	225001	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2820371	0	0
ReadyAndValidImplyGrant_A	425848891	225001	0	0
ReqAndReadyImplyGrant_A	425848891	225001	0	0
ReqImpliesValid_A	425848891	634187	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	225001	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	225001	0	0
T2	5475	114	0	0
T3	12837	9	0	0
T4	10579	163	0	0
T7	9051	10	0	0
T8	56777	1175	0	0
T9	62243	72	0	0
T10	4451	35	0	0
T11	298462	713	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	225001	0	0
T2	5475	114	0	0
T3	12837	9	0	0
T4	10579	163	0	0
T7	9051	10	0	0
T8	56777	1175	0	0
T9	62243	72	0	0
T10	4451	35	0	0
T11	298462	713	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	225001	0	0
T2	5475	114	0	0
T3	12837	9	0	0
T4	10579	163	0	0
T7	9051	10	0	0
T8	56777	1175	0	0
T9	62243	72	0	0
T10	4451	35	0	0
T11	298462	713	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2820371	0	0
T1	50131	1	0	0
T2	5475	110	0	0
T3	12837	54	0	0
T4	10579	158	0	0
T7	9051	42	0	0
T8	56777	623	0	0
T9	62243	547	0	0
T10	4451	37	0	0
T11	298462	5479	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	225001	0	0
T2	5475	114	0	0
T3	12837	9	0	0
T4	10579	163	0	0
T7	9051	10	0	0
T8	56777	1175	0	0
T9	62243	72	0	0
T10	4451	35	0	0
T11	298462	713	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	225001	0	0
T2	5475	114	0	0
T3	12837	9	0	0
T4	10579	163	0	0
T7	9051	10	0	0
T8	56777	1175	0	0
T9	62243	72	0	0
T10	4451	35	0	0
T11	298462	713	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	634187	0	0
T2	5475	119	0	0
T3	12837	9	0	0
T4	10579	169	0	0
T7	9051	10	0	0
T8	56777	1730	0	0
T9	62243	78	0	0
T10	4451	35	0	0
T11	298462	864	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	225001	0	0
T2	5475	114	0	0
T3	12837	9	0	0
T4	10579	163	0	0
T7	9051	10	0	0
T8	56777	1175	0	0
T9	62243	72	0	0
T10	4451	35	0	0
T11	298462	713	0	0
T12	18163	0	0	0
T13	13485	7	0	0
T14	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	211165	0	0
GntImpliesValid_A	425848891	211165	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	211165	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2801551	0	0
ReadyAndValidImplyGrant_A	425848891	211165	0	0
ReqAndReadyImplyGrant_A	425848891	211165	0	0
ReqImpliesValid_A	425848891	563114	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	211165	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211165	0	0
T2	5475	105	0	0
T3	12837	13	0	0
T4	10579	151	0	0
T7	9051	13	0	0
T8	56777	652	0	0
T9	62243	90	0	0
T10	4451	41	0	0
T11	298462	658	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211165	0	0
T2	5475	105	0	0
T3	12837	13	0	0
T4	10579	151	0	0
T7	9051	13	0	0
T8	56777	652	0	0
T9	62243	90	0	0
T10	4451	41	0	0
T11	298462	658	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211165	0	0
T2	5475	105	0	0
T3	12837	13	0	0
T4	10579	151	0	0
T7	9051	13	0	0
T8	56777	652	0	0
T9	62243	90	0	0
T10	4451	41	0	0
T11	298462	658	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2801551	0	0
T1	50131	1	0	0
T2	5475	101	0	0
T3	12837	101	0	0
T4	10579	145	0	0
T7	9051	104	0	0
T8	56777	635	0	0
T9	62243	637	0	0
T10	4451	43	0	0
T11	298462	5123	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211165	0	0
T2	5475	105	0	0
T3	12837	13	0	0
T4	10579	151	0	0
T7	9051	13	0	0
T8	56777	652	0	0
T9	62243	90	0	0
T10	4451	41	0	0
T11	298462	658	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211165	0	0
T2	5475	105	0	0
T3	12837	13	0	0
T4	10579	151	0	0
T7	9051	13	0	0
T8	56777	652	0	0
T9	62243	90	0	0
T10	4451	41	0	0
T11	298462	658	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	563114	0	0
T2	5475	110	0	0
T3	12837	28	0	0
T4	10579	158	0	0
T7	9051	13	0	0
T8	56777	672	0	0
T9	62243	98	0	0
T10	4451	41	0	0
T11	298462	719	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	211165	0	0
T2	5475	105	0	0
T3	12837	13	0	0
T4	10579	151	0	0
T7	9051	13	0	0
T8	56777	652	0	0
T9	62243	90	0	0
T10	4451	41	0	0
T11	298462	658	0	0
T12	18163	0	0	0
T13	13485	15	0	0
T14	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	220048	0	0
GntImpliesValid_A	425848891	220048	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	220048	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2862541	0	0
ReadyAndValidImplyGrant_A	425848891	220048	0	0
ReqAndReadyImplyGrant_A	425848891	220048	0	0
ReqImpliesValid_A	425848891	606325	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	220048	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220048	0	0
T2	5475	100	0	0
T3	12837	11	0	0
T4	10579	148	0	0
T7	9051	11	0	0
T8	56777	1147	0	0
T9	62243	99	0	0
T10	4451	41	0	0
T11	298462	671	0	0
T12	18163	0	0	0
T13	13485	10	0	0
T14	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220048	0	0
T2	5475	100	0	0
T3	12837	11	0	0
T4	10579	148	0	0
T7	9051	11	0	0
T8	56777	1147	0	0
T9	62243	99	0	0
T10	4451	41	0	0
T11	298462	671	0	0
T12	18163	0	0	0
T13	13485	10	0	0
T14	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220048	0	0
T2	5475	100	0	0
T3	12837	11	0	0
T4	10579	148	0	0
T7	9051	11	0	0
T8	56777	1147	0	0
T9	62243	99	0	0
T10	4451	41	0	0
T11	298462	671	0	0
T12	18163	0	0	0
T13	13485	10	0	0
T14	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2862541	0	0
T1	50131	1	0	0
T2	5475	98	0	0
T3	12837	98	0	0
T4	10579	142	0	0
T7	9051	88	0	0
T8	56777	684	0	0
T9	62243	824	0	0
T10	4451	43	0	0
T11	298462	5255	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220048	0	0
T2	5475	100	0	0
T3	12837	11	0	0
T4	10579	148	0	0
T7	9051	11	0	0
T8	56777	1147	0	0
T9	62243	99	0	0
T10	4451	41	0	0
T11	298462	671	0	0
T12	18163	0	0	0
T13	13485	10	0	0
T14	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220048	0	0
T2	5475	100	0	0
T3	12837	11	0	0
T4	10579	148	0	0
T7	9051	11	0	0
T8	56777	1147	0	0
T9	62243	99	0	0
T10	4451	41	0	0
T11	298462	671	0	0
T12	18163	0	0	0
T13	13485	10	0	0
T14	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	606325	0	0
T2	5475	103	0	0
T3	12837	11	0	0
T4	10579	155	0	0
T7	9051	11	0	0
T8	56777	1613	0	0
T9	62243	123	0	0
T10	4451	41	0	0
T11	298462	834	0	0
T12	18163	0	0	0
T13	13485	19	0	0
T14	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220048	0	0
T2	5475	100	0	0
T3	12837	11	0	0
T4	10579	148	0	0
T7	9051	11	0	0
T8	56777	1147	0	0
T9	62243	99	0	0
T10	4451	41	0	0
T11	298462	671	0	0
T12	18163	0	0	0
T13	13485	10	0	0
T14	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	239666	0	0
GntImpliesValid_A	425848891	239666	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	239666	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2974707	0	0
ReadyAndValidImplyGrant_A	425848891	239666	0	0
ReqAndReadyImplyGrant_A	425848891	239666	0	0
ReqImpliesValid_A	425848891	644496	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	239666	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	239666	0	0
T1	50131	548	0	0
T2	5475	109	0	0
T3	12837	15	0	0
T4	10579	175	0	0
T7	9051	11	0	0
T8	56777	1300	0	0
T9	62243	101	0	0
T10	4451	70	0	0
T11	298462	915	0	0
T12	18163	0	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	239666	0	0
T1	50131	548	0	0
T2	5475	109	0	0
T3	12837	15	0	0
T4	10579	175	0	0
T7	9051	11	0	0
T8	56777	1300	0	0
T9	62243	101	0	0
T10	4451	70	0	0
T11	298462	915	0	0
T12	18163	0	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	239666	0	0
T1	50131	548	0	0
T2	5475	109	0	0
T3	12837	15	0	0
T4	10579	175	0	0
T7	9051	11	0	0
T8	56777	1300	0	0
T9	62243	101	0	0
T10	4451	70	0	0
T11	298462	915	0	0
T12	18163	0	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2974707	0	0
T1	50131	1281	0	0
T2	5475	104	0	0
T3	12837	108	0	0
T4	10579	164	0	0
T7	9051	70	0	0
T8	56777	1133	0	0
T9	62243	769	0	0
T10	4451	72	0	0
T11	298462	6982	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	239666	0	0
T1	50131	548	0	0
T2	5475	109	0	0
T3	12837	15	0	0
T4	10579	175	0	0
T7	9051	11	0	0
T8	56777	1300	0	0
T9	62243	101	0	0
T10	4451	70	0	0
T11	298462	915	0	0
T12	18163	0	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	239666	0	0
T1	50131	548	0	0
T2	5475	109	0	0
T3	12837	15	0	0
T4	10579	175	0	0
T7	9051	11	0	0
T8	56777	1300	0	0
T9	62243	101	0	0
T10	4451	70	0	0
T11	298462	915	0	0
T12	18163	0	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	644496	0	0
T1	50131	4866	0	0
T2	5475	115	0	0
T3	12837	15	0	0
T4	10579	187	0	0
T7	9051	11	0	0
T8	56777	1470	0	0
T9	62243	126	0	0
T10	4451	70	0	0
T11	298462	1272	0	0
T12	18163	0	0	0
T13	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	239666	0	0
T1	50131	548	0	0
T2	5475	109	0	0
T3	12837	15	0	0
T4	10579	175	0	0
T7	9051	11	0	0
T8	56777	1300	0	0
T9	62243	101	0	0
T10	4451	70	0	0
T11	298462	915	0	0
T12	18163	0	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	221034	0	0
GntImpliesValid_A	425848891	221034	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	221034	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2895096	0	0
ReadyAndValidImplyGrant_A	425848891	221034	0	0
ReqAndReadyImplyGrant_A	425848891	221034	0	0
ReqImpliesValid_A	425848891	598591	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	221034	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	221034	0	0
T2	5475	91	0	0
T3	12837	13	0	0
T4	10579	174	0	0
T7	9051	2	0	0
T8	56777	662	0	0
T9	62243	78	0	0
T10	4451	55	0	0
T11	298462	672	0	0
T12	18163	0	0	0
T13	13485	20	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	221034	0	0
T2	5475	91	0	0
T3	12837	13	0	0
T4	10579	174	0	0
T7	9051	2	0	0
T8	56777	662	0	0
T9	62243	78	0	0
T10	4451	55	0	0
T11	298462	672	0	0
T12	18163	0	0	0
T13	13485	20	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	221034	0	0
T2	5475	91	0	0
T3	12837	13	0	0
T4	10579	174	0	0
T7	9051	2	0	0
T8	56777	662	0	0
T9	62243	78	0	0
T10	4451	55	0	0
T11	298462	672	0	0
T12	18163	0	0	0
T13	13485	20	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2895096	0	0
T1	50131	1	0	0
T2	5475	90	0	0
T3	12837	105	0	0
T4	10579	167	0	0
T7	9051	10	0	0
T8	56777	644	0	0
T9	62243	669	0	0
T10	4451	57	0	0
T11	298462	4982	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	221034	0	0
T2	5475	91	0	0
T3	12837	13	0	0
T4	10579	174	0	0
T7	9051	2	0	0
T8	56777	662	0	0
T9	62243	78	0	0
T10	4451	55	0	0
T11	298462	672	0	0
T12	18163	0	0	0
T13	13485	20	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	221034	0	0
T2	5475	91	0	0
T3	12837	13	0	0
T4	10579	174	0	0
T7	9051	2	0	0
T8	56777	662	0	0
T9	62243	78	0	0
T10	4451	55	0	0
T11	298462	672	0	0
T12	18163	0	0	0
T13	13485	20	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	598591	0	0
T2	5475	93	0	0
T3	12837	13	0	0
T4	10579	182	0	0
T7	9051	2	0	0
T8	56777	683	0	0
T9	62243	89	0	0
T10	4451	55	0	0
T11	298462	786	0	0
T12	18163	0	0	0
T13	13485	20	0	0
T14	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	221034	0	0
T2	5475	91	0	0
T3	12837	13	0	0
T4	10579	174	0	0
T7	9051	2	0	0
T8	56777	662	0	0
T9	62243	78	0	0
T10	4451	55	0	0
T11	298462	672	0	0
T12	18163	0	0	0
T13	13485	20	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	220905	0	0
GntImpliesValid_A	425848891	220905	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	220905	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2812114	0	0
ReadyAndValidImplyGrant_A	425848891	220905	0	0
ReqAndReadyImplyGrant_A	425848891	220905	0	0
ReqImpliesValid_A	425848891	597993	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	220905	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220905	0	0
T2	5475	105	0	0
T3	12837	15	0	0
T4	10579	186	0	0
T7	9051	9	0	0
T8	56777	683	0	0
T9	62243	62	0	0
T10	4451	54	0	0
T11	298462	692	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220905	0	0
T2	5475	105	0	0
T3	12837	15	0	0
T4	10579	186	0	0
T7	9051	9	0	0
T8	56777	683	0	0
T9	62243	62	0	0
T10	4451	54	0	0
T11	298462	692	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220905	0	0
T2	5475	105	0	0
T3	12837	15	0	0
T4	10579	186	0	0
T7	9051	9	0	0
T8	56777	683	0	0
T9	62243	62	0	0
T10	4451	54	0	0
T11	298462	692	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2812114	0	0
T1	50131	1	0	0
T2	5475	98	0	0
T3	12837	136	0	0
T4	10579	170	0	0
T7	9051	87	0	0
T8	56777	670	0	0
T9	62243	485	0	0
T10	4451	56	0	0
T11	298462	5217	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220905	0	0
T2	5475	105	0	0
T3	12837	15	0	0
T4	10579	186	0	0
T7	9051	9	0	0
T8	56777	683	0	0
T9	62243	62	0	0
T10	4451	54	0	0
T11	298462	692	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220905	0	0
T2	5475	105	0	0
T3	12837	15	0	0
T4	10579	186	0	0
T7	9051	9	0	0
T8	56777	683	0	0
T9	62243	62	0	0
T10	4451	54	0	0
T11	298462	692	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	597993	0	0
T2	5475	113	0	0
T3	12837	25	0	0
T4	10579	203	0	0
T7	9051	9	0	0
T8	56777	699	0	0
T9	62243	74	0	0
T10	4451	54	0	0
T11	298462	790	0	0
T12	18163	0	0	0
T13	13485	20	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	220905	0	0
T2	5475	105	0	0
T3	12837	15	0	0
T4	10579	186	0	0
T7	9051	9	0	0
T8	56777	683	0	0
T9	62243	62	0	0
T10	4451	54	0	0
T11	298462	692	0	0
T12	18163	0	0	0
T13	13485	14	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	212329	0	0
GntImpliesValid_A	425848891	212329	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	212329	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2881740	0	0
ReadyAndValidImplyGrant_A	425848891	212329	0	0
ReqAndReadyImplyGrant_A	425848891	212329	0	0
ReqImpliesValid_A	425848891	579032	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	212329	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	212329	0	0
T2	5475	96	0	0
T3	12837	11	0	0
T4	10579	179	0	0
T7	9051	10	0	0
T8	56777	1098	0	0
T9	62243	68	0	0
T10	4451	62	0	0
T11	298462	641	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	212329	0	0
T2	5475	96	0	0
T3	12837	11	0	0
T4	10579	179	0	0
T7	9051	10	0	0
T8	56777	1098	0	0
T9	62243	68	0	0
T10	4451	62	0	0
T11	298462	641	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	212329	0	0
T2	5475	96	0	0
T3	12837	11	0	0
T4	10579	179	0	0
T7	9051	10	0	0
T8	56777	1098	0	0
T9	62243	68	0	0
T10	4451	62	0	0
T11	298462	641	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2881740	0	0
T1	50131	1	0	0
T2	5475	90	0	0
T3	12837	78	0	0
T4	10579	168	0	0
T7	9051	76	0	0
T8	56777	639	0	0
T9	62243	496	0	0
T10	4451	64	0	0
T11	298462	4685	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	212329	0	0
T2	5475	96	0	0
T3	12837	11	0	0
T4	10579	179	0	0
T7	9051	10	0	0
T8	56777	1098	0	0
T9	62243	68	0	0
T10	4451	62	0	0
T11	298462	641	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	212329	0	0
T2	5475	96	0	0
T3	12837	11	0	0
T4	10579	179	0	0
T7	9051	10	0	0
T8	56777	1098	0	0
T9	62243	68	0	0
T10	4451	62	0	0
T11	298462	641	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	579032	0	0
T2	5475	103	0	0
T3	12837	11	0	0
T4	10579	191	0	0
T7	9051	21	0	0
T8	56777	1560	0	0
T9	62243	68	0	0
T10	4451	62	0	0
T11	298462	745	0	0
T12	18163	0	0	0
T13	13485	18	0	0
T14	0	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	212329	0	0
T2	5475	96	0	0
T3	12837	11	0	0
T4	10579	179	0	0
T7	9051	10	0	0
T8	56777	1098	0	0
T9	62243	68	0	0
T10	4451	62	0	0
T11	298462	641	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	208219	0	0
GntImpliesValid_A	425848891	208219	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	208219	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2836020	0	0
ReadyAndValidImplyGrant_A	425848891	208219	0	0
ReqAndReadyImplyGrant_A	425848891	208219	0	0
ReqImpliesValid_A	425848891	581040	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	208219	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208219	0	0
T2	5475	84	0	0
T3	12837	12	0	0
T4	10579	156	0	0
T7	9051	5	0	0
T8	56777	659	0	0
T9	62243	88	0	0
T10	4451	55	0	0
T11	298462	682	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208219	0	0
T2	5475	84	0	0
T3	12837	12	0	0
T4	10579	156	0	0
T7	9051	5	0	0
T8	56777	659	0	0
T9	62243	88	0	0
T10	4451	55	0	0
T11	298462	682	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208219	0	0
T2	5475	84	0	0
T3	12837	12	0	0
T4	10579	156	0	0
T7	9051	5	0	0
T8	56777	659	0	0
T9	62243	88	0	0
T10	4451	55	0	0
T11	298462	682	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2836020	0	0
T1	50131	1	0	0
T2	5475	82	0	0
T3	12837	105	0	0
T4	10579	148	0	0
T7	9051	46	0	0
T8	56777	643	0	0
T9	62243	641	0	0
T10	4451	57	0	0
T11	298462	5261	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208219	0	0
T2	5475	84	0	0
T3	12837	12	0	0
T4	10579	156	0	0
T7	9051	5	0	0
T8	56777	659	0	0
T9	62243	88	0	0
T10	4451	55	0	0
T11	298462	682	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208219	0	0
T2	5475	84	0	0
T3	12837	12	0	0
T4	10579	156	0	0
T7	9051	5	0	0
T8	56777	659	0	0
T9	62243	88	0	0
T10	4451	55	0	0
T11	298462	682	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	581040	0	0
T2	5475	87	0	0
T3	12837	12	0	0
T4	10579	165	0	0
T7	9051	5	0	0
T8	56777	678	0	0
T9	62243	110	0	0
T10	4451	55	0	0
T11	298462	814	0	0
T12	18163	0	0	0
T13	13485	18	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	208219	0	0
T2	5475	84	0	0
T3	12837	12	0	0
T4	10579	156	0	0
T7	9051	5	0	0
T8	56777	659	0	0
T9	62243	88	0	0
T10	4451	55	0	0
T11	298462	682	0	0
T12	18163	0	0	0
T13	13485	11	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	240330	0	0
GntImpliesValid_A	425848891	240330	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	240330	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	2913976	0	0
ReadyAndValidImplyGrant_A	425848891	240330	0	0
ReqAndReadyImplyGrant_A	425848891	240330	0	0
ReqImpliesValid_A	425848891	669982	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	0	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	240330	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	240330	0	0
T2	5475	125	0	0
T3	12837	12	0	0
T4	10579	160	0	0
T7	9051	14	0	0
T8	56777	2118	0	0
T9	62243	123	0	0
T10	4451	64	0	0
T11	298462	681	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	240330	0	0
T2	5475	125	0	0
T3	12837	12	0	0
T4	10579	160	0	0
T7	9051	14	0	0
T8	56777	2118	0	0
T9	62243	123	0	0
T10	4451	64	0	0
T11	298462	681	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	240330	0	0
T2	5475	125	0	0
T3	12837	12	0	0
T4	10579	160	0	0
T7	9051	14	0	0
T8	56777	2118	0	0
T9	62243	123	0	0
T10	4451	64	0	0
T11	298462	681	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2913976	0	0
T1	50131	1	0	0
T2	5475	119	0	0
T3	12837	113	0	0
T4	10579	149	0	0
T7	9051	130	0	0
T8	56777	930	0	0
T9	62243	806	0	0
T10	4451	66	0	0
T11	298462	5108	0	0
T12	18163	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	240330	0	0
T2	5475	125	0	0
T3	12837	12	0	0
T4	10579	160	0	0
T7	9051	14	0	0
T8	56777	2118	0	0
T9	62243	123	0	0
T10	4451	64	0	0
T11	298462	681	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	240330	0	0
T2	5475	125	0	0
T3	12837	12	0	0
T4	10579	160	0	0
T7	9051	14	0	0
T8	56777	2118	0	0
T9	62243	123	0	0
T10	4451	64	0	0
T11	298462	681	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	669982	0	0
T2	5475	132	0	0
T3	12837	12	0	0
T4	10579	172	0	0
T7	9051	14	0	0
T8	56777	3309	0	0
T9	62243	271	0	0
T10	4451	64	0	0
T11	298462	762	0	0
T12	18163	0	0	0
T13	13485	29	0	0
T14	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	240330	0	0
T2	5475	125	0	0
T3	12837	12	0	0
T4	10579	160	0	0
T7	9051	14	0	0
T8	56777	2118	0	0
T9	62243	123	0	0
T10	4451	64	0	0
T11	298462	681	0	0
T12	18163	0	0	0
T13	13485	17	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	878021	0	0
GntImpliesValid_A	425848891	878021	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	878021	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	11093747	0	0
ReadyAndValidImplyGrant_A	425848891	878021	0	0
ReqAndReadyImplyGrant_A	425848891	878021	0	0
ReqImpliesValid_A	425848891	2266495	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	17345	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	878021	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	878021	0	0
T1	50131	159	0	0
T2	5475	381	0	0
T3	12837	34	0	0
T4	10579	653	0	0
T7	9051	32	0	0
T8	56777	3917	0	0
T9	62243	1077	0	0
T10	4451	340	0	0
T11	298462	2989	0	0
T12	18163	166	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	878021	0	0
T1	50131	159	0	0
T2	5475	381	0	0
T3	12837	34	0	0
T4	10579	653	0	0
T7	9051	32	0	0
T8	56777	3917	0	0
T9	62243	1077	0	0
T10	4451	340	0	0
T11	298462	2989	0	0
T12	18163	166	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	878021	0	0
T1	50131	159	0	0
T2	5475	381	0	0
T3	12837	34	0	0
T4	10579	653	0	0
T7	9051	32	0	0
T8	56777	3917	0	0
T9	62243	1077	0	0
T10	4451	340	0	0
T11	298462	2989	0	0
T12	18163	166	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	11093747	0	0
T1	50131	1078	0	0
T2	5475	1	0	0
T3	12837	157	0	0
T4	10579	1	0	0
T7	9051	194	0	0
T8	56777	3	0	0
T9	62243	4308	0	0
T10	4451	2	0	0
T11	298462	19936	0	0
T12	18163	1157	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	878021	0	0
T1	50131	159	0	0
T2	5475	381	0	0
T3	12837	34	0	0
T4	10579	653	0	0
T7	9051	32	0	0
T8	56777	3917	0	0
T9	62243	1077	0	0
T10	4451	340	0	0
T11	298462	2989	0	0
T12	18163	166	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	878021	0	0
T1	50131	159	0	0
T2	5475	381	0	0
T3	12837	34	0	0
T4	10579	653	0	0
T7	9051	32	0	0
T8	56777	3917	0	0
T9	62243	1077	0	0
T10	4451	340	0	0
T11	298462	2989	0	0
T12	18163	166	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	2266495	0	0
T1	50131	229	0	0
T2	5475	381	0	0
T3	12837	57	0	0
T4	10579	653	0	0
T7	9051	39	0	0
T8	56777	3917	0	0
T9	62243	2552	0	0
T10	4451	340	0	0
T11	298462	4278	0	0
T12	18163	248	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	17345	0	900
T2	5475	8	0	1
T3	12837	0	0	1
T4	10579	10	0	1
T7	9051	0	0	1
T8	56777	327	0	1
T9	62243	27	0	1
T10	4451	2	0	1
T11	298462	2	0	1
T12	18163	0	0	1
T13	13485	0	0	1
T15	0	3	0	0
T16	0	299	0	0
T17	0	18	0	0
T18	0	21	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	878021	0	0
T1	50131	159	0	0
T2	5475	381	0	0
T3	12837	34	0	0
T4	10579	653	0	0
T7	9051	32	0	0
T8	56777	3917	0	0
T9	62243	1077	0	0
T10	4451	340	0	0
T11	298462	2989	0	0
T12	18163	166	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425848891	425722808	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425848891	890663	0	0
GntImpliesValid_A	425848891	890663	0	0
GrantKnown_A	425848891	425722808	0	0
IdxKnown_A	425848891	425722808	0	0
IndexIsCorrect_A	425848891	890663	0	0
LockArbDecision_A	425848891	0	0	0
NoReadyValidNoGrant_A	425848891	357306940	0	0
ReadyAndValidImplyGrant_A	425848891	890663	0	0
ReqAndReadyImplyGrant_A	425848891	890663	0	0
ReqImpliesValid_A	425848891	12885423	0	0
ReqStaysHighUntilGranted0_M	425848891	0	0	0
RoundRobin_A	425848891	32723	0	900
ValidKnown_A	425848891	425722808	0	0
gen_data_port_assertion.DataFlow_A	425848891	890663	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	890663	0	0
T1	50131	937	0	0
T2	5475	425	0	0
T3	12837	39	0	0
T4	10579	669	0	0
T7	9051	37	0	0
T8	56777	3109	0	0
T9	62243	990	0	0
T10	4451	388	0	0
T11	298462	2892	0	0
T12	18163	197	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	890663	0	0
T1	50131	937	0	0
T2	5475	425	0	0
T3	12837	39	0	0
T4	10579	669	0	0
T7	9051	37	0	0
T8	56777	3109	0	0
T9	62243	990	0	0
T10	4451	388	0	0
T11	298462	2892	0	0
T12	18163	197	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	890663	0	0
T1	50131	937	0	0
T2	5475	425	0	0
T3	12837	39	0	0
T4	10579	669	0	0
T7	9051	37	0	0
T8	56777	3109	0	0
T9	62243	990	0	0
T10	4451	388	0	0
T11	298462	2892	0	0
T12	18163	197	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	357306940	0	0
T1	50131	37323	0	0
T2	5475	1	0	0
T3	12837	11329	0	0
T4	10579	1	0	0
T7	9051	7802	0	0
T8	56777	1	0	0
T9	62243	46403	0	0
T10	4451	1	0	0
T11	298462	243030	0	0
T12	18163	14941	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	890663	0	0
T1	50131	937	0	0
T2	5475	425	0	0
T3	12837	39	0	0
T4	10579	669	0	0
T7	9051	37	0	0
T8	56777	3109	0	0
T9	62243	990	0	0
T10	4451	388	0	0
T11	298462	2892	0	0
T12	18163	197	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	890663	0	0
T1	50131	937	0	0
T2	5475	425	0	0
T3	12837	39	0	0
T4	10579	669	0	0
T7	9051	37	0	0
T8	56777	3109	0	0
T9	62243	990	0	0
T10	4451	388	0	0
T11	298462	2892	0	0
T12	18163	197	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	12885423	0	0
T1	50131	9171	0	0
T2	5475	425	0	0
T3	12837	292	0	0
T4	10579	669	0	0
T7	9051	253	0	0
T8	56777	3109	0	0
T9	62243	8725	0	0
T10	4451	388	0	0
T11	298462	21640	0	0
T12	18163	1711	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	32723	0	900
T1	50131	17	0	1
T2	5475	13	0	1
T3	12837	0	0	1
T4	10579	16	0	1
T7	9051	0	0	1
T8	56777	42	0	1
T9	62243	6	0	1
T10	4451	3	0	1
T11	298462	5	0	1
T12	18163	0	0	1
T15	0	6	0	0
T16	0	23	0	0
T17	0	29	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	425722808	0	0
T1	50131	50098	0	0
T2	5475	5469	0	0
T3	12837	12790	0	0
T4	10579	10518	0	0
T7	9051	9002	0	0
T8	56777	56708	0	0
T9	62243	59603	0	0
T10	4451	4366	0	0
T11	298462	297056	0	0
T12	18163	18136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425848891	890663	0	0
T1	50131	937	0	0
T2	5475	425	0	0
T3	12837	39	0	0
T4	10579	669	0	0
T7	9051	37	0	0
T8	56777	3109	0	0
T9	62243	990	0	0
T10	4451	388	0	0
T11	298462	2892	0	0
T12	18163	197	0	0