Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1668871 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 266102 1 T1 132 T2 12 T3 16


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 656904 1 T1 368 T2 41 T3 35
values[0x0] 621309 1 T1 341 T2 41 T3 37
values[0x1] 656760 1 T1 333 T2 34 T3 42


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1290009 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 644964 1 T1 338 T2 32 T3 46


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 31214 1 T1 17 T3 3 T4 2
valid_sources[0x01] 30203 1 T1 5 T4 1 T7 2
valid_sources[0x02] 30154 1 T1 17 T2 6 T3 5
valid_sources[0x03] 29990 1 T1 10 T4 2 T7 2
valid_sources[0x04] 31591 1 T1 18 T3 13 T7 5
valid_sources[0x05] 29703 1 T1 21 T4 3 T9 1
valid_sources[0x06] 30961 1 T4 1 T7 3 T10 20
valid_sources[0x07] 28983 1 T4 1 T9 1 T10 56
valid_sources[0x08] 29225 1 T1 15 T4 1 T7 3
valid_sources[0x09] 30206 1 T7 4 T10 72 T12 85
valid_sources[0x0a] 30893 1 T1 11 T4 2 T7 1
valid_sources[0x0b] 31623 1 T4 4 T7 5 T9 1
valid_sources[0x0c] 30387 1 T1 12 T2 4 T4 2
valid_sources[0x0d] 29976 1 T1 24 T3 10 T4 1
valid_sources[0x0e] 29696 1 T1 17 T3 4 T4 1
valid_sources[0x0f] 30497 1 T1 21 T3 2 T8 12
valid_sources[0x10] 30655 1 T1 61 T3 4 T7 1
valid_sources[0x11] 31399 1 T4 1 T7 1 T8 41
valid_sources[0x12] 30330 1 T1 26 T3 6 T4 4
valid_sources[0x13] 30188 1 T4 3 T7 1 T10 26
valid_sources[0x14] 30827 1 T4 3 T7 1 T9 2
valid_sources[0x15] 29726 1 T1 30 T7 1 T8 1
valid_sources[0x16] 30239 1 T4 2 T9 1 T10 48
valid_sources[0x17] 29985 1 T1 16 T3 7 T4 4
valid_sources[0x18] 29076 1 T1 32 T7 1 T9 1
valid_sources[0x19] 30188 1 T1 20 T4 4 T7 3
valid_sources[0x1a] 29315 1 T1 22 T2 19 T3 14
valid_sources[0x1b] 29899 1 T1 13 T4 1 T7 7
valid_sources[0x1c] 29887 1 T1 35 T2 1 T4 2
valid_sources[0x1d] 30045 1 T1 27 T3 9 T7 3
valid_sources[0x1e] 30312 1 T1 27 T4 1 T7 3
valid_sources[0x1f] 30502 1 T1 14 T4 3 T8 8
valid_sources[0x20] 30300 1 T1 41 T3 10 T4 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27809 1 T1 12 T2 1 T3 1
values[0x0] all_enables biggest_size 210362 1 T1 106 T2 11 T3 14
values[0x1] all_enables biggest_size 27931 1 T1 14 T3 1 T4 6


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1683358 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 273648 1 T1 157 T2 25 T3 20


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 669096 1 T1 387 T2 53 T3 60
values[0x0] 618352 1 T1 369 T2 61 T3 58
values[0x1] 669558 1 T1 349 T2 64 T3 55


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1291944 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 665062 1 T1 383 T2 59 T3 63


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29816 1 T1 10 T2 3 T3 1
valid_sources[0x01] 30789 1 T1 19 T2 2 T4 1
valid_sources[0x02] 30577 1 T1 15 T2 6 T4 1
valid_sources[0x03] 30423 1 T1 15 T2 6 T3 3
valid_sources[0x04] 31529 1 T1 19 T2 2 T3 2
valid_sources[0x05] 29876 1 T1 45 T2 4 T3 3
valid_sources[0x06] 30379 1 T2 4 T3 2 T4 1
valid_sources[0x07] 31644 1 T2 5 T3 1 T4 2
valid_sources[0x08] 30864 1 T1 9 T2 3 T3 2
valid_sources[0x09] 30123 1 T2 4 T3 1 T10 19
valid_sources[0x0a] 30480 1 T1 19 T2 1 T3 6
valid_sources[0x0b] 30002 1 T2 3 T3 1 T4 2
valid_sources[0x0c] 30147 1 T1 8 T2 5 T3 7
valid_sources[0x0d] 30829 1 T1 32 T2 5 T3 2
valid_sources[0x0e] 31342 1 T1 17 T2 2 T3 1
valid_sources[0x0f] 30277 1 T1 15 T2 3 T3 1
valid_sources[0x10] 30417 1 T1 55 T2 4 T3 2
valid_sources[0x11] 30741 1 T2 2 T3 3 T4 3
valid_sources[0x12] 30294 1 T1 24 T2 5 T3 3
valid_sources[0x13] 30423 1 T2 4 T3 2 T7 3
valid_sources[0x14] 31050 1 T2 1 T3 4 T4 5
valid_sources[0x15] 30951 1 T1 22 T2 1 T3 5
valid_sources[0x16] 31371 1 T2 3 T3 2 T4 3
valid_sources[0x17] 30719 1 T1 27 T2 6 T3 2
valid_sources[0x18] 30424 1 T1 18 T2 2 T3 3
valid_sources[0x19] 30062 1 T1 17 T2 4 T3 2
valid_sources[0x1a] 30507 1 T1 32 T2 3 T3 2
valid_sources[0x1b] 30318 1 T1 15 T2 1 T3 3
valid_sources[0x1c] 30413 1 T1 36 T2 4 T3 5
valid_sources[0x1d] 30242 1 T1 20 T2 3 T3 5
valid_sources[0x1e] 30556 1 T1 23 T2 3 T3 6
valid_sources[0x1f] 30554 1 T1 14 T4 3 T7 2
valid_sources[0x20] 31279 1 T1 44 T2 1 T4 2


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 28589 1 T1 15 T2 3 T4 2
values[0x0] all_enables biggest_size 216232 1 T1 129 T2 21 T3 19
values[0x1] all_enables biggest_size 28827 1 T1 13 T2 1 T3 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1673277 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 266908 1 T1 146 T2 22 T3 31


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 659012 1 T1 356 T2 39 T3 56
values[0x0] 623303 1 T1 362 T2 45 T3 67
values[0x1] 657870 1 T1 403 T2 43 T3 54


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1293128 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 647057 1 T1 355 T2 45 T3 63


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 31315 1 T1 11 T2 5 T4 6
valid_sources[0x01] 30503 1 T1 5 T2 2 T4 2
valid_sources[0x02] 29805 1 T1 11 T2 1 T7 3
valid_sources[0x03] 30658 1 T1 18 T2 3 T3 1
valid_sources[0x04] 30294 1 T1 22 T7 5 T10 42
valid_sources[0x05] 30978 1 T1 44 T2 3 T7 6
valid_sources[0x06] 30067 1 T2 2 T4 12 T10 10
valid_sources[0x07] 30460 1 T2 4 T7 2 T9 4
valid_sources[0x08] 30538 1 T1 12 T2 1 T7 3
valid_sources[0x09] 29718 1 T7 2 T10 4 T11 4
valid_sources[0x0a] 30483 1 T1 6 T2 3 T4 10
valid_sources[0x0b] 30541 1 T2 2 T4 9 T7 3
valid_sources[0x0c] 30810 1 T1 10 T2 3 T3 11
valid_sources[0x0d] 30335 1 T1 27 T2 2 T7 3
valid_sources[0x0e] 30628 1 T1 18 T2 2 T7 4
valid_sources[0x0f] 30805 1 T1 19 T2 1 T3 32
valid_sources[0x10] 30369 1 T1 71 T2 2 T4 2
valid_sources[0x11] 30470 1 T2 1 T7 2 T9 2
valid_sources[0x12] 30054 1 T1 21 T2 3 T4 7
valid_sources[0x13] 30562 1 T2 6 T3 16 T7 1
valid_sources[0x14] 30291 1 T2 3 T7 2 T10 24
valid_sources[0x15] 30714 1 T1 29 T2 3 T7 2
valid_sources[0x16] 30203 1 T2 2 T7 4 T9 2
valid_sources[0x17] 29760 1 T1 38 T3 12 T7 2
valid_sources[0x18] 30768 1 T1 34 T2 2 T7 3
valid_sources[0x19] 30850 1 T1 7 T2 2 T7 2
valid_sources[0x1a] 30439 1 T1 35 T2 2 T7 4
valid_sources[0x1b] 30055 1 T1 17 T2 2 T7 3
valid_sources[0x1c] 30112 1 T1 41 T2 2 T4 2
valid_sources[0x1d] 29230 1 T1 42 T2 2 T3 4
valid_sources[0x1e] 30182 1 T1 26 T7 4 T9 1
valid_sources[0x1f] 29325 1 T1 6 T4 6 T7 3
valid_sources[0x20] 30578 1 T1 20 T3 23 T7 4


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27903 1 T1 15 T2 2 T7 1
values[0x0] all_enables biggest_size 210970 1 T1 114 T2 17 T3 27
values[0x1] all_enables biggest_size 28035 1 T1 17 T2 3 T3 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%