Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8374910	0	0
GntImpliesValid_A	2147483647	8374910	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8374910	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	474426164	0	0
ReadyAndValidImplyGrant_A	2147483647	8374910	0	0
ReqAndReadyImplyGrant_A	2147483647	8374910	0	0
ReqImpliesValid_A	2147483647	34659233	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46135	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8374910	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1598160	1596576	0	0
T2	52368	51120	0	0
T3	22872	22320	0	0
T4	6967392	6966312	0	0
T7	6414624	6414360	0	0
T8	272688	272472	0	0
T9	139920	139080	0	0
T10	424776	423840	0	0
T11	46200	44904	0	0
T12	13949664	13949616	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8374910	0	0
T1	1598160	3250	0	0
T2	52368	421	0	0
T3	22872	464	0	0
T4	6967392	336	0	0
T7	6414624	499	0	0
T8	272688	501	0	0
T9	139920	2291	0	0
T10	424776	8834	0	0
T11	46200	402	0	0
T12	13949664	14532	0	0
T13	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8374910	0	0
T1	1598160	3250	0	0
T2	52368	421	0	0
T3	22872	464	0	0
T4	6967392	336	0	0
T7	6414624	499	0	0
T8	272688	501	0	0
T9	139920	2291	0	0
T10	424776	8834	0	0
T11	46200	402	0	0
T12	13949664	14532	0	0
T13	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1598160	1596576	0	0
T2	52368	51120	0	0
T3	22872	22320	0	0
T4	6967392	6966312	0	0
T7	6414624	6414360	0	0
T8	272688	272472	0	0
T9	139920	139080	0	0
T10	424776	423840	0	0
T11	46200	44904	0	0
T12	13949664	13949616	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1598160	1596576	0	0
T2	52368	51120	0	0
T3	22872	22320	0	0
T4	6967392	6966312	0	0
T7	6414624	6414360	0	0
T8	272688	272472	0	0
T9	139920	139080	0	0
T10	424776	423840	0	0
T11	46200	44904	0	0
T12	13949664	13949616	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8374910	0	0
T1	1598160	3250	0	0
T2	52368	421	0	0
T3	22872	464	0	0
T4	6967392	336	0	0
T7	6414624	499	0	0
T8	272688	501	0	0
T9	139920	2291	0	0
T10	424776	8834	0	0
T11	46200	402	0	0
T12	13949664	14532	0	0
T13	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	474426164	0	0
T1	1598160	88984	0	0
T2	52368	620	0	0
T3	22872	514	0	0
T4	6967392	243763	0	0
T7	6414624	224612	0	0
T8	272688	13132	0	0
T9	139920	2948	0	0
T10	424776	13485	0	0
T11	46200	498	0	0
T12	13949664	530558	0	0
T13	0	331	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8374910	0	0
T1	1598160	3250	0	0
T2	52368	421	0	0
T3	22872	464	0	0
T4	6967392	336	0	0
T7	6414624	499	0	0
T8	272688	501	0	0
T9	139920	2291	0	0
T10	424776	8834	0	0
T11	46200	402	0	0
T12	13949664	14532	0	0
T13	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8374910	0	0
T1	1598160	3250	0	0
T2	52368	421	0	0
T3	22872	464	0	0
T4	6967392	336	0	0
T7	6414624	499	0	0
T8	272688	501	0	0
T9	139920	2291	0	0
T10	424776	8834	0	0
T11	46200	402	0	0
T12	13949664	14532	0	0
T13	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34659233	0	0
T1	1598160	6110	0	0
T2	52368	532	0	0
T3	22872	524	0	0
T4	6967392	695	0	0
T7	6414624	814	0	0
T8	272688	963	0	0
T9	139920	2618	0	0
T10	424776	10764	0	0
T11	46200	448	0	0
T12	13949664	33931	0	0
T13	0	135	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46135	0	21600
T3	953	4	0	1
T4	290308	0	0	1
T7	267276	0	0	1
T8	11362	0	0	1
T9	5830	5	0	1
T10	35398	29	0	2
T11	3850	0	0	2
T12	1162472	0	0	2
T13	20500	0	0	2
T14	242773	42	0	1
T15	387928	7	0	1
T16	668955	21	0	1
T17	4694	7	0	1
T18	0	13	0	0
T19	0	2	0	0
T20	0	12	0	0
T21	0	9	0	0
T22	0	13	0	0
T23	537230	0	0	2
T24	131139	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1598160	1596576	0	0
T2	52368	51120	0	0
T3	22872	22320	0	0
T4	6967392	6966312	0	0
T7	6414624	6414360	0	0
T8	272688	272472	0	0
T9	139920	139080	0	0
T10	424776	423840	0	0
T11	46200	44904	0	0
T12	13949664	13949616	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8374910	0	0
T1	1598160	3250	0	0
T2	52368	421	0	0
T3	22872	464	0	0
T4	6967392	336	0	0
T7	6414624	499	0	0
T8	272688	501	0	0
T9	139920	2291	0	0
T10	424776	8834	0	0
T11	46200	402	0	0
T12	13949664	14532	0	0
T13	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	927742	0	0
GntImpliesValid_A	441843153	927742	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	927742	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	12105524	0	0
ReadyAndValidImplyGrant_A	441843153	927742	0	0
ReqAndReadyImplyGrant_A	441843153	927742	0	0
ReqImpliesValid_A	441843153	2520348	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	927742	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	927742	0	0
T1	66590	348	0	0
T2	2182	57	0	0
T3	953	55	0	0
T4	290308	36	0	0
T7	267276	62	0	0
T8	11362	48	0	0
T9	5830	249	0	0
T10	17699	1008	0	0
T11	1925	50	0	0
T12	581236	1754	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	927742	0	0
T1	66590	348	0	0
T2	2182	57	0	0
T3	953	55	0	0
T4	290308	36	0	0
T7	267276	62	0	0
T8	11362	48	0	0
T9	5830	249	0	0
T10	17699	1008	0	0
T11	1925	50	0	0
T12	581236	1754	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	927742	0	0
T1	66590	348	0	0
T2	2182	57	0	0
T3	953	55	0	0
T4	290308	36	0	0
T7	267276	62	0	0
T8	11362	48	0	0
T9	5830	249	0	0
T10	17699	1008	0	0
T11	1925	50	0	0
T12	581236	1754	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	12105524	0	0
T1	66590	2714	0	0
T2	2182	40	0	0
T3	953	45	0	0
T4	290308	141	0	0
T7	267276	254	0	0
T8	11362	359	0	0
T9	5830	213	0	0
T10	17699	755	0	0
T11	1925	42	0	0
T12	581236	6505	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	927742	0	0
T1	66590	348	0	0
T2	2182	57	0	0
T3	953	55	0	0
T4	290308	36	0	0
T7	267276	62	0	0
T8	11362	48	0	0
T9	5830	249	0	0
T10	17699	1008	0	0
T11	1925	50	0	0
T12	581236	1754	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	927742	0	0
T1	66590	348	0	0
T2	2182	57	0	0
T3	953	55	0	0
T4	290308	36	0	0
T7	267276	62	0	0
T8	11362	48	0	0
T9	5830	249	0	0
T10	17699	1008	0	0
T11	1925	50	0	0
T12	581236	1754	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	2520348	0	0
T1	66590	352	0	0
T2	2182	75	0	0
T3	953	66	0	0
T4	290308	40	0	0
T7	267276	96	0	0
T8	11362	90	0	0
T9	5830	286	0	0
T10	17699	1262	0	0
T11	1925	59	0	0
T12	581236	3350	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	927742	0	0
T1	66590	348	0	0
T2	2182	57	0	0
T3	953	55	0	0
T4	290308	36	0	0
T7	267276	62	0	0
T8	11362	48	0	0
T9	5830	249	0	0
T10	17699	1008	0	0
T11	1925	50	0	0
T12	581236	1754	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	939832	0	0
GntImpliesValid_A	441843153	939832	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	939832	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	12304492	0	0
ReadyAndValidImplyGrant_A	441843153	939832	0	0
ReqAndReadyImplyGrant_A	441843153	939832	0	0
ReqImpliesValid_A	441843153	2595506	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	939832	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	939832	0	0
T1	66590	364	0	0
T2	2182	54	0	0
T3	953	55	0	0
T4	290308	48	0	0
T7	267276	59	0	0
T8	11362	62	0	0
T9	5830	248	0	0
T10	17699	1028	0	0
T11	1925	49	0	0
T12	581236	2539	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	939832	0	0
T1	66590	364	0	0
T2	2182	54	0	0
T3	953	55	0	0
T4	290308	48	0	0
T7	267276	59	0	0
T8	11362	62	0	0
T9	5830	248	0	0
T10	17699	1028	0	0
T11	1925	49	0	0
T12	581236	2539	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	939832	0	0
T1	66590	364	0	0
T2	2182	54	0	0
T3	953	55	0	0
T4	290308	48	0	0
T7	267276	59	0	0
T8	11362	62	0	0
T9	5830	248	0	0
T10	17699	1028	0	0
T11	1925	49	0	0
T12	581236	2539	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	12304492	0	0
T1	66590	2787	0	0
T2	2182	38	0	0
T3	953	42	0	0
T4	290308	204	0	0
T7	267276	239	0	0
T8	11362	434	0	0
T9	5830	203	0	0
T10	17699	765	0	0
T11	1925	36	0	0
T12	581236	9220	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	939832	0	0
T1	66590	364	0	0
T2	2182	54	0	0
T3	953	55	0	0
T4	290308	48	0	0
T7	267276	59	0	0
T8	11362	62	0	0
T9	5830	248	0	0
T10	17699	1028	0	0
T11	1925	49	0	0
T12	581236	2539	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	939832	0	0
T1	66590	364	0	0
T2	2182	54	0	0
T3	953	55	0	0
T4	290308	48	0	0
T7	267276	59	0	0
T8	11362	62	0	0
T9	5830	248	0	0
T10	17699	1028	0	0
T11	1925	49	0	0
T12	581236	2539	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	2595506	0	0
T1	66590	397	0	0
T2	2182	71	0	0
T3	953	69	0	0
T4	290308	55	0	0
T7	267276	79	0	0
T8	11362	97	0	0
T9	5830	294	0	0
T10	17699	1292	0	0
T11	1925	63	0	0
T12	581236	5113	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	939832	0	0
T1	66590	364	0	0
T2	2182	54	0	0
T3	953	55	0	0
T4	290308	48	0	0
T7	267276	59	0	0
T8	11362	62	0	0
T9	5830	248	0	0
T10	17699	1028	0	0
T11	1925	49	0	0
T12	581236	2539	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	228193	0	0
GntImpliesValid_A	441843153	228193	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	228193	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3064538	0	0
ReadyAndValidImplyGrant_A	441843153	228193	0	0
ReqAndReadyImplyGrant_A	441843153	228193	0	0
ReqImpliesValid_A	441843153	635370	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	228193	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228193	0	0
T1	66590	92	0	0
T2	2182	12	0	0
T3	953	10	0	0
T4	290308	13	0	0
T7	267276	19	0	0
T8	11362	24	0	0
T9	5830	59	0	0
T10	17699	226	0	0
T11	1925	10	0	0
T12	581236	0	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228193	0	0
T1	66590	92	0	0
T2	2182	12	0	0
T3	953	10	0	0
T4	290308	13	0	0
T7	267276	19	0	0
T8	11362	24	0	0
T9	5830	59	0	0
T10	17699	226	0	0
T11	1925	10	0	0
T12	581236	0	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228193	0	0
T1	66590	92	0	0
T2	2182	12	0	0
T3	953	10	0	0
T4	290308	13	0	0
T7	267276	19	0	0
T8	11362	24	0	0
T9	5830	59	0	0
T10	17699	226	0	0
T11	1925	10	0	0
T12	581236	0	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3064538	0	0
T1	66590	722	0	0
T2	2182	13	0	0
T3	953	10	0	0
T4	290308	53	0	0
T7	267276	87	0	0
T8	11362	208	0	0
T9	5830	60	0	0
T10	17699	215	0	0
T11	1925	11	0	0
T12	581236	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228193	0	0
T1	66590	92	0	0
T2	2182	12	0	0
T3	953	10	0	0
T4	290308	13	0	0
T7	267276	19	0	0
T8	11362	24	0	0
T9	5830	59	0	0
T10	17699	226	0	0
T11	1925	10	0	0
T12	581236	0	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228193	0	0
T1	66590	92	0	0
T2	2182	12	0	0
T3	953	10	0	0
T4	290308	13	0	0
T7	267276	19	0	0
T8	11362	24	0	0
T9	5830	59	0	0
T10	17699	226	0	0
T11	1925	10	0	0
T12	581236	0	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	635370	0	0
T1	66590	92	0	0
T2	2182	12	0	0
T3	953	11	0	0
T4	290308	13	0	0
T7	267276	23	0	0
T8	11362	24	0	0
T9	5830	59	0	0
T10	17699	238	0	0
T11	1925	10	0	0
T12	581236	0	0	0
T13	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228193	0	0
T1	66590	92	0	0
T2	2182	12	0	0
T3	953	10	0	0
T4	290308	13	0	0
T7	267276	19	0	0
T8	11362	24	0	0
T9	5830	59	0	0
T10	17699	226	0	0
T11	1925	10	0	0
T12	581236	0	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	239627	0	0
GntImpliesValid_A	441843153	239627	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	239627	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3069880	0	0
ReadyAndValidImplyGrant_A	441843153	239627	0	0
ReqAndReadyImplyGrant_A	441843153	239627	0	0
ReqImpliesValid_A	441843153	585106	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	239627	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	239627	0	0
T1	66590	80	0	0
T2	2182	10	0	0
T3	953	11	0	0
T4	290308	8	0	0
T7	267276	14	0	0
T8	11362	12	0	0
T9	5830	69	0	0
T10	17699	222	0	0
T11	1925	9	0	0
T12	581236	1548	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	239627	0	0
T1	66590	80	0	0
T2	2182	10	0	0
T3	953	11	0	0
T4	290308	8	0	0
T7	267276	14	0	0
T8	11362	12	0	0
T9	5830	69	0	0
T10	17699	222	0	0
T11	1925	9	0	0
T12	581236	1548	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	239627	0	0
T1	66590	80	0	0
T2	2182	10	0	0
T3	953	11	0	0
T4	290308	8	0	0
T7	267276	14	0	0
T8	11362	12	0	0
T9	5830	69	0	0
T10	17699	222	0	0
T11	1925	9	0	0
T12	581236	1548	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3069880	0	0
T1	66590	602	0	0
T2	2182	10	0	0
T3	953	12	0	0
T4	290308	31	0	0
T7	267276	60	0	0
T8	11362	58	0	0
T9	5830	65	0	0
T10	17699	212	0	0
T11	1925	9	0	0
T12	581236	5225	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	239627	0	0
T1	66590	80	0	0
T2	2182	10	0	0
T3	953	11	0	0
T4	290308	8	0	0
T7	267276	14	0	0
T8	11362	12	0	0
T9	5830	69	0	0
T10	17699	222	0	0
T11	1925	9	0	0
T12	581236	1548	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	239627	0	0
T1	66590	80	0	0
T2	2182	10	0	0
T3	953	11	0	0
T4	290308	8	0	0
T7	267276	14	0	0
T8	11362	12	0	0
T9	5830	69	0	0
T10	17699	222	0	0
T11	1925	9	0	0
T12	581236	1548	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	585106	0	0
T1	66590	80	0	0
T2	2182	11	0	0
T3	953	11	0	0
T4	290308	8	0	0
T7	267276	14	0	0
T8	11362	12	0	0
T9	5830	74	0	0
T10	17699	233	0	0
T11	1925	10	0	0
T12	581236	3606	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	239627	0	0
T1	66590	80	0	0
T2	2182	10	0	0
T3	953	11	0	0
T4	290308	8	0	0
T7	267276	14	0	0
T8	11362	12	0	0
T9	5830	69	0	0
T10	17699	222	0	0
T11	1925	9	0	0
T12	581236	1548	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	226401	0	0
GntImpliesValid_A	441843153	226401	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	226401	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	4974233	0	0
ReadyAndValidImplyGrant_A	441843153	226401	0	0
ReqAndReadyImplyGrant_A	441843153	226401	0	0
ReqImpliesValid_A	441843153	1027407	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	226401	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	226401	0	0
T1	66590	89	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	6	0	0
T7	267276	10	0	0
T8	11362	9	0	0
T9	5830	63	0	0
T10	17699	226	0	0
T11	1925	18	0	0
T12	581236	425	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	226401	0	0
T1	66590	89	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	6	0	0
T7	267276	10	0	0
T8	11362	9	0	0
T9	5830	63	0	0
T10	17699	226	0	0
T11	1925	18	0	0
T12	581236	425	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	226401	0	0
T1	66590	89	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	6	0	0
T7	267276	10	0	0
T8	11362	9	0	0
T9	5830	63	0	0
T10	17699	226	0	0
T11	1925	18	0	0
T12	581236	425	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	4974233	0	0
T1	66590	2712	0	0
T2	2182	69	0	0
T3	953	62	0	0
T4	290308	157	0	0
T7	267276	36	0	0
T8	11362	38	0	0
T9	5830	291	0	0
T10	17699	2751	0	0
T11	1925	72	0	0
T12	581236	1506	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	226401	0	0
T1	66590	89	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	6	0	0
T7	267276	10	0	0
T8	11362	9	0	0
T9	5830	63	0	0
T10	17699	226	0	0
T11	1925	18	0	0
T12	581236	425	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	226401	0	0
T1	66590	89	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	6	0	0
T7	267276	10	0	0
T8	11362	9	0	0
T9	5830	63	0	0
T10	17699	226	0	0
T11	1925	18	0	0
T12	581236	425	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	1027407	0	0
T1	66590	170	0	0
T2	2182	13	0	0
T3	953	18	0	0
T4	290308	55	0	0
T7	267276	18	0	0
T8	11362	9	0	0
T9	5830	104	0	0
T10	17699	544	0	0
T11	1925	35	0	0
T12	581236	1093	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	226401	0	0
T1	66590	89	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	6	0	0
T7	267276	10	0	0
T8	11362	9	0	0
T9	5830	63	0	0
T10	17699	226	0	0
T11	1925	18	0	0
T12	581236	425	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	232436	0	0
GntImpliesValid_A	441843153	232436	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	232436	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	4599916	0	0
ReadyAndValidImplyGrant_A	441843153	232436	0	0
ReqAndReadyImplyGrant_A	441843153	232436	0	0
ReqImpliesValid_A	441843153	1077721	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	232436	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	232436	0	0
T1	66590	91	0	0
T2	2182	8	0	0
T3	953	9	0	0
T4	290308	5	0	0
T7	267276	16	0	0
T8	11362	16	0	0
T9	5830	64	0	0
T10	17699	238	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	232436	0	0
T1	66590	91	0	0
T2	2182	8	0	0
T3	953	9	0	0
T4	290308	5	0	0
T7	267276	16	0	0
T8	11362	16	0	0
T9	5830	64	0	0
T10	17699	238	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	232436	0	0
T1	66590	91	0	0
T2	2182	8	0	0
T3	953	9	0	0
T4	290308	5	0	0
T7	267276	16	0	0
T8	11362	16	0	0
T9	5830	64	0	0
T10	17699	238	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	4599916	0	0
T1	66590	6428	0	0
T2	2182	77	0	0
T3	953	41	0	0
T4	290308	273	0	0
T7	267276	63	0	0
T8	11362	101	0	0
T9	5830	368	0	0
T10	17699	3454	0	0
T11	1925	35	0	0
T12	581236	0	0	0
T13	0	118	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	232436	0	0
T1	66590	91	0	0
T2	2182	8	0	0
T3	953	9	0	0
T4	290308	5	0	0
T7	267276	16	0	0
T8	11362	16	0	0
T9	5830	64	0	0
T10	17699	238	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	232436	0	0
T1	66590	91	0	0
T2	2182	8	0	0
T3	953	9	0	0
T4	290308	5	0	0
T7	267276	16	0	0
T8	11362	16	0	0
T9	5830	64	0	0
T10	17699	238	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	1077721	0	0
T1	66590	171	0	0
T2	2182	29	0	0
T3	953	12	0	0
T4	290308	5	0	0
T7	267276	20	0	0
T8	11362	21	0	0
T9	5830	89	0	0
T10	17699	859	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	232436	0	0
T1	66590	91	0	0
T2	2182	8	0	0
T3	953	9	0	0
T4	290308	5	0	0
T7	267276	16	0	0
T8	11362	16	0	0
T9	5830	64	0	0
T10	17699	238	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	230134	0	0
GntImpliesValid_A	441843153	230134	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	230134	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	5145287	0	0
ReadyAndValidImplyGrant_A	441843153	230134	0	0
ReqAndReadyImplyGrant_A	441843153	230134	0	0
ReqImpliesValid_A	441843153	1139482	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	230134	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	230134	0	0
T1	66590	80	0	0
T2	2182	9	0	0
T3	953	10	0	0
T4	290308	17	0	0
T7	267276	14	0	0
T8	11362	14	0	0
T9	5830	64	0	0
T10	17699	246	0	0
T11	1925	4	0	0
T12	581236	0	0	0
T13	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	230134	0	0
T1	66590	80	0	0
T2	2182	9	0	0
T3	953	10	0	0
T4	290308	17	0	0
T7	267276	14	0	0
T8	11362	14	0	0
T9	5830	64	0	0
T10	17699	246	0	0
T11	1925	4	0	0
T12	581236	0	0	0
T13	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	230134	0	0
T1	66590	80	0	0
T2	2182	9	0	0
T3	953	10	0	0
T4	290308	17	0	0
T7	267276	14	0	0
T8	11362	14	0	0
T9	5830	64	0	0
T10	17699	246	0	0
T11	1925	4	0	0
T12	581236	0	0	0
T13	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	5145287	0	0
T1	66590	824	0	0
T2	2182	40	0	0
T3	953	39	0	0
T4	290308	319	0	0
T7	267276	82	0	0
T8	11362	152	0	0
T9	5830	590	0	0
T10	17699	1036	0	0
T11	1925	76	0	0
T12	581236	0	0	0
T13	0	97	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	230134	0	0
T1	66590	80	0	0
T2	2182	9	0	0
T3	953	10	0	0
T4	290308	17	0	0
T7	267276	14	0	0
T8	11362	14	0	0
T9	5830	64	0	0
T10	17699	246	0	0
T11	1925	4	0	0
T12	581236	0	0	0
T13	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	230134	0	0
T1	66590	80	0	0
T2	2182	9	0	0
T3	953	10	0	0
T4	290308	17	0	0
T7	267276	14	0	0
T8	11362	14	0	0
T9	5830	64	0	0
T10	17699	246	0	0
T11	1925	4	0	0
T12	581236	0	0	0
T13	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	1139482	0	0
T1	66590	97	0	0
T2	2182	13	0	0
T3	953	14	0	0
T4	290308	77	0	0
T7	267276	14	0	0
T8	11362	15	0	0
T9	5830	124	0	0
T10	17699	375	0	0
T11	1925	4	0	0
T12	581236	0	0	0
T13	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	230134	0	0
T1	66590	80	0	0
T2	2182	9	0	0
T3	953	10	0	0
T4	290308	17	0	0
T7	267276	14	0	0
T8	11362	14	0	0
T9	5830	64	0	0
T10	17699	246	0	0
T11	1925	4	0	0
T12	581236	0	0	0
T13	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	237190	0	0
GntImpliesValid_A	441843153	237190	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	237190	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	5157079	0	0
ReadyAndValidImplyGrant_A	441843153	237190	0	0
ReqAndReadyImplyGrant_A	441843153	237190	0	0
ReqImpliesValid_A	441843153	1249088	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	237190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237190	0	0
T1	66590	84	0	0
T2	2182	10	0	0
T3	953	18	0	0
T4	290308	9	0	0
T7	267276	11	0	0
T8	11362	14	0	0
T9	5830	68	0	0
T10	17699	274	0	0
T11	1925	11	0	0
T12	581236	0	0	0
T13	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237190	0	0
T1	66590	84	0	0
T2	2182	10	0	0
T3	953	18	0	0
T4	290308	9	0	0
T7	267276	11	0	0
T8	11362	14	0	0
T9	5830	68	0	0
T10	17699	274	0	0
T11	1925	11	0	0
T12	581236	0	0	0
T13	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237190	0	0
T1	66590	84	0	0
T2	2182	10	0	0
T3	953	18	0	0
T4	290308	9	0	0
T7	267276	11	0	0
T8	11362	14	0	0
T9	5830	68	0	0
T10	17699	274	0	0
T11	1925	11	0	0
T12	581236	0	0	0
T13	0	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	5157079	0	0
T1	66590	1888	0	0
T2	2182	178	0	0
T3	953	80	0	0
T4	290308	177	0	0
T7	267276	115	0	0
T8	11362	64	0	0
T9	5830	302	0	0
T10	17699	1172	0	0
T11	1925	58	0	0
T12	581236	0	0	0
T13	0	116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237190	0	0
T1	66590	84	0	0
T2	2182	10	0	0
T3	953	18	0	0
T4	290308	9	0	0
T7	267276	11	0	0
T8	11362	14	0	0
T9	5830	68	0	0
T10	17699	274	0	0
T11	1925	11	0	0
T12	581236	0	0	0
T13	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237190	0	0
T1	66590	84	0	0
T2	2182	10	0	0
T3	953	18	0	0
T4	290308	9	0	0
T7	267276	11	0	0
T8	11362	14	0	0
T9	5830	68	0	0
T10	17699	274	0	0
T11	1925	11	0	0
T12	581236	0	0	0
T13	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	1249088	0	0
T1	66590	134	0	0
T2	2182	50	0	0
T3	953	29	0	0
T4	290308	63	0	0
T7	267276	29	0	0
T8	11362	14	0	0
T9	5830	136	0	0
T10	17699	413	0	0
T11	1925	11	0	0
T12	581236	0	0	0
T13	0	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237190	0	0
T1	66590	84	0	0
T2	2182	10	0	0
T3	953	18	0	0
T4	290308	9	0	0
T7	267276	11	0	0
T8	11362	14	0	0
T9	5830	68	0	0
T10	17699	274	0	0
T11	1925	11	0	0
T12	581236	0	0	0
T13	0	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	228769	0	0
GntImpliesValid_A	441843153	228769	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	228769	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3088079	0	0
ReadyAndValidImplyGrant_A	441843153	228769	0	0
ReqAndReadyImplyGrant_A	441843153	228769	0	0
ReqImpliesValid_A	441843153	579783	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	228769	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228769	0	0
T1	66590	85	0	0
T2	2182	7	0	0
T3	953	12	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	13	0	0
T9	5830	61	0	0
T10	17699	237	0	0
T11	1925	5	0	0
T12	581236	940	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228769	0	0
T1	66590	85	0	0
T2	2182	7	0	0
T3	953	12	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	13	0	0
T9	5830	61	0	0
T10	17699	237	0	0
T11	1925	5	0	0
T12	581236	940	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228769	0	0
T1	66590	85	0	0
T2	2182	7	0	0
T3	953	12	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	13	0	0
T9	5830	61	0	0
T10	17699	237	0	0
T11	1925	5	0	0
T12	581236	940	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3088079	0	0
T1	66590	627	0	0
T2	2182	7	0	0
T3	953	11	0	0
T4	290308	19	0	0
T7	267276	47	0	0
T8	11362	105	0	0
T9	5830	57	0	0
T10	17699	221	0	0
T11	1925	6	0	0
T12	581236	3102	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228769	0	0
T1	66590	85	0	0
T2	2182	7	0	0
T3	953	12	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	13	0	0
T9	5830	61	0	0
T10	17699	237	0	0
T11	1925	5	0	0
T12	581236	940	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228769	0	0
T1	66590	85	0	0
T2	2182	7	0	0
T3	953	12	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	13	0	0
T9	5830	61	0	0
T10	17699	237	0	0
T11	1925	5	0	0
T12	581236	940	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	579783	0	0
T1	66590	90	0	0
T2	2182	8	0	0
T3	953	14	0	0
T4	290308	5	0	0
T7	267276	13	0	0
T8	11362	13	0	0
T9	5830	66	0	0
T10	17699	254	0	0
T11	1925	5	0	0
T12	581236	2369	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228769	0	0
T1	66590	85	0	0
T2	2182	7	0	0
T3	953	12	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	13	0	0
T9	5830	61	0	0
T10	17699	237	0	0
T11	1925	5	0	0
T12	581236	940	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	234628	0	0
GntImpliesValid_A	441843153	234628	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	234628	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3041268	0	0
ReadyAndValidImplyGrant_A	441843153	234628	0	0
ReqAndReadyImplyGrant_A	441843153	234628	0	0
ReqImpliesValid_A	441843153	556945	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	234628	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	234628	0	0
T1	66590	97	0	0
T2	2182	10	0	0
T3	953	14	0	0
T4	290308	8	0	0
T7	267276	17	0	0
T8	11362	16	0	0
T9	5830	55	0	0
T10	17699	243	0	0
T11	1925	12	0	0
T12	581236	504	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	234628	0	0
T1	66590	97	0	0
T2	2182	10	0	0
T3	953	14	0	0
T4	290308	8	0	0
T7	267276	17	0	0
T8	11362	16	0	0
T9	5830	55	0	0
T10	17699	243	0	0
T11	1925	12	0	0
T12	581236	504	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	234628	0	0
T1	66590	97	0	0
T2	2182	10	0	0
T3	953	14	0	0
T4	290308	8	0	0
T7	267276	17	0	0
T8	11362	16	0	0
T9	5830	55	0	0
T10	17699	243	0	0
T11	1925	12	0	0
T12	581236	504	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3041268	0	0
T1	66590	739	0	0
T2	2182	8	0	0
T3	953	15	0	0
T4	290308	27	0	0
T7	267276	54	0	0
T8	11362	87	0	0
T9	5830	51	0	0
T10	17699	230	0	0
T11	1925	13	0	0
T12	581236	1694	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	234628	0	0
T1	66590	97	0	0
T2	2182	10	0	0
T3	953	14	0	0
T4	290308	8	0	0
T7	267276	17	0	0
T8	11362	16	0	0
T9	5830	55	0	0
T10	17699	243	0	0
T11	1925	12	0	0
T12	581236	504	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	234628	0	0
T1	66590	97	0	0
T2	2182	10	0	0
T3	953	14	0	0
T4	290308	8	0	0
T7	267276	17	0	0
T8	11362	16	0	0
T9	5830	55	0	0
T10	17699	243	0	0
T11	1925	12	0	0
T12	581236	504	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	556945	0	0
T1	66590	97	0	0
T2	2182	13	0	0
T3	953	14	0	0
T4	290308	8	0	0
T7	267276	17	0	0
T8	11362	16	0	0
T9	5830	60	0	0
T10	17699	257	0	0
T11	1925	12	0	0
T12	581236	1129	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	234628	0	0
T1	66590	97	0	0
T2	2182	10	0	0
T3	953	14	0	0
T4	290308	8	0	0
T7	267276	17	0	0
T8	11362	16	0	0
T9	5830	55	0	0
T10	17699	243	0	0
T11	1925	12	0	0
T12	581236	504	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	237558	0	0
GntImpliesValid_A	441843153	237558	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	237558	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3015080	0	0
ReadyAndValidImplyGrant_A	441843153	237558	0	0
ReqAndReadyImplyGrant_A	441843153	237558	0	0
ReqImpliesValid_A	441843153	618279	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	237558	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237558	0	0
T1	66590	90	0	0
T2	2182	7	0	0
T3	953	13	0	0
T4	290308	8	0	0
T7	267276	11	0	0
T8	11362	12	0	0
T9	5830	67	0	0
T10	17699	226	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237558	0	0
T1	66590	90	0	0
T2	2182	7	0	0
T3	953	13	0	0
T4	290308	8	0	0
T7	267276	11	0	0
T8	11362	12	0	0
T9	5830	67	0	0
T10	17699	226	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237558	0	0
T1	66590	90	0	0
T2	2182	7	0	0
T3	953	13	0	0
T4	290308	8	0	0
T7	267276	11	0	0
T8	11362	12	0	0
T9	5830	67	0	0
T10	17699	226	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3015080	0	0
T1	66590	661	0	0
T2	2182	8	0	0
T3	953	14	0	0
T4	290308	49	0	0
T7	267276	45	0	0
T8	11362	94	0	0
T9	5830	64	0	0
T10	17699	214	0	0
T11	1925	13	0	0
T12	581236	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237558	0	0
T1	66590	90	0	0
T2	2182	7	0	0
T3	953	13	0	0
T4	290308	8	0	0
T7	267276	11	0	0
T8	11362	12	0	0
T9	5830	67	0	0
T10	17699	226	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237558	0	0
T1	66590	90	0	0
T2	2182	7	0	0
T3	953	13	0	0
T4	290308	8	0	0
T7	267276	11	0	0
T8	11362	12	0	0
T9	5830	67	0	0
T10	17699	226	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	618279	0	0
T1	66590	90	0	0
T2	2182	7	0	0
T3	953	13	0	0
T4	290308	8	0	0
T7	267276	11	0	0
T8	11362	12	0	0
T9	5830	71	0	0
T10	17699	239	0	0
T11	1925	14	0	0
T12	581236	0	0	0
T13	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	237558	0	0
T1	66590	90	0	0
T2	2182	7	0	0
T3	953	13	0	0
T4	290308	8	0	0
T7	267276	11	0	0
T8	11362	12	0	0
T9	5830	67	0	0
T10	17699	226	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T23
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T23

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	227115	0	0
GntImpliesValid_A	441843153	227115	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	227115	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3024471	0	0
ReadyAndValidImplyGrant_A	441843153	227115	0	0
ReqAndReadyImplyGrant_A	441843153	227115	0	0
ReqImpliesValid_A	441843153	572373	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	227115	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227115	0	0
T1	66590	103	0	0
T2	2182	13	0	0
T3	953	8	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	15	0	0
T9	5830	70	0	0
T10	17699	226	0	0
T11	1925	15	0	0
T12	581236	0	0	0
T13	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227115	0	0
T1	66590	103	0	0
T2	2182	13	0	0
T3	953	8	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	15	0	0
T9	5830	70	0	0
T10	17699	226	0	0
T11	1925	15	0	0
T12	581236	0	0	0
T13	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227115	0	0
T1	66590	103	0	0
T2	2182	13	0	0
T3	953	8	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	15	0	0
T9	5830	70	0	0
T10	17699	226	0	0
T11	1925	15	0	0
T12	581236	0	0	0
T13	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3024471	0	0
T1	66590	836	0	0
T2	2182	14	0	0
T3	953	9	0	0
T4	290308	14	0	0
T7	267276	61	0	0
T8	11362	117	0	0
T9	5830	65	0	0
T10	17699	214	0	0
T11	1925	16	0	0
T12	581236	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227115	0	0
T1	66590	103	0	0
T2	2182	13	0	0
T3	953	8	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	15	0	0
T9	5830	70	0	0
T10	17699	226	0	0
T11	1925	15	0	0
T12	581236	0	0	0
T13	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227115	0	0
T1	66590	103	0	0
T2	2182	13	0	0
T3	953	8	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	15	0	0
T9	5830	70	0	0
T10	17699	226	0	0
T11	1925	15	0	0
T12	581236	0	0	0
T13	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	572373	0	0
T1	66590	103	0	0
T2	2182	13	0	0
T3	953	8	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	15	0	0
T9	5830	76	0	0
T10	17699	239	0	0
T11	1925	15	0	0
T12	581236	0	0	0
T13	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227115	0	0
T1	66590	103	0	0
T2	2182	13	0	0
T3	953	8	0	0
T4	290308	5	0	0
T7	267276	12	0	0
T8	11362	15	0	0
T9	5830	70	0	0
T10	17699	226	0	0
T11	1925	15	0	0
T12	581236	0	0	0
T13	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	229458	0	0
GntImpliesValid_A	441843153	229458	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	229458	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3006062	0	0
ReadyAndValidImplyGrant_A	441843153	229458	0	0
ReqAndReadyImplyGrant_A	441843153	229458	0	0
ReqImpliesValid_A	441843153	576358	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	229458	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	229458	0	0
T1	66590	99	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	17	0	0
T7	267276	16	0	0
T8	11362	11	0	0
T9	5830	68	0	0
T10	17699	217	0	0
T11	1925	10	0	0
T12	581236	495	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	229458	0	0
T1	66590	99	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	17	0	0
T7	267276	16	0	0
T8	11362	11	0	0
T9	5830	68	0	0
T10	17699	217	0	0
T11	1925	10	0	0
T12	581236	495	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	229458	0	0
T1	66590	99	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	17	0	0
T7	267276	16	0	0
T8	11362	11	0	0
T9	5830	68	0	0
T10	17699	217	0	0
T11	1925	10	0	0
T12	581236	495	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3006062	0	0
T1	66590	751	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	89	0	0
T7	267276	61	0	0
T8	11362	88	0	0
T9	5830	66	0	0
T10	17699	209	0	0
T11	1925	11	0	0
T12	581236	1754	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	229458	0	0
T1	66590	99	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	17	0	0
T7	267276	16	0	0
T8	11362	11	0	0
T9	5830	68	0	0
T10	17699	217	0	0
T11	1925	10	0	0
T12	581236	495	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	229458	0	0
T1	66590	99	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	17	0	0
T7	267276	16	0	0
T8	11362	11	0	0
T9	5830	68	0	0
T10	17699	217	0	0
T11	1925	10	0	0
T12	581236	495	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	576358	0	0
T1	66590	99	0	0
T2	2182	14	0	0
T3	953	13	0	0
T4	290308	21	0	0
T7	267276	16	0	0
T8	11362	11	0	0
T9	5830	71	0	0
T10	17699	226	0	0
T11	1925	10	0	0
T12	581236	1235	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	229458	0	0
T1	66590	99	0	0
T2	2182	13	0	0
T3	953	12	0	0
T4	290308	17	0	0
T7	267276	16	0	0
T8	11362	11	0	0
T9	5830	68	0	0
T10	17699	217	0	0
T11	1925	10	0	0
T12	581236	495	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	233249	0	0
GntImpliesValid_A	441843153	233249	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	233249	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	2999007	0	0
ReadyAndValidImplyGrant_A	441843153	233249	0	0
ReqAndReadyImplyGrant_A	441843153	233249	0	0
ReqImpliesValid_A	441843153	586563	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	233249	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233249	0	0
T1	66590	89	0	0
T2	2182	14	0	0
T3	953	15	0	0
T4	290308	7	0	0
T7	267276	10	0	0
T8	11362	15	0	0
T9	5830	66	0	0
T10	17699	253	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233249	0	0
T1	66590	89	0	0
T2	2182	14	0	0
T3	953	15	0	0
T4	290308	7	0	0
T7	267276	10	0	0
T8	11362	15	0	0
T9	5830	66	0	0
T10	17699	253	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233249	0	0
T1	66590	89	0	0
T2	2182	14	0	0
T3	953	15	0	0
T4	290308	7	0	0
T7	267276	10	0	0
T8	11362	15	0	0
T9	5830	66	0	0
T10	17699	253	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	2999007	0	0
T1	66590	700	0	0
T2	2182	15	0	0
T3	953	15	0	0
T4	290308	34	0	0
T7	267276	39	0	0
T8	11362	112	0	0
T9	5830	63	0	0
T10	17699	241	0	0
T11	1925	14	0	0
T12	581236	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233249	0	0
T1	66590	89	0	0
T2	2182	14	0	0
T3	953	15	0	0
T4	290308	7	0	0
T7	267276	10	0	0
T8	11362	15	0	0
T9	5830	66	0	0
T10	17699	253	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233249	0	0
T1	66590	89	0	0
T2	2182	14	0	0
T3	953	15	0	0
T4	290308	7	0	0
T7	267276	10	0	0
T8	11362	15	0	0
T9	5830	66	0	0
T10	17699	253	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	586563	0	0
T1	66590	92	0	0
T2	2182	14	0	0
T3	953	16	0	0
T4	290308	7	0	0
T7	267276	14	0	0
T8	11362	22	0	0
T9	5830	70	0	0
T10	17699	266	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233249	0	0
T1	66590	89	0	0
T2	2182	14	0	0
T3	953	15	0	0
T4	290308	7	0	0
T7	267276	10	0	0
T8	11362	15	0	0
T9	5830	66	0	0
T10	17699	253	0	0
T11	1925	13	0	0
T12	581236	0	0	0
T13	0	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	233992	0	0
GntImpliesValid_A	441843153	233992	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	233992	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3093542	0	0
ReadyAndValidImplyGrant_A	441843153	233992	0	0
ReqAndReadyImplyGrant_A	441843153	233992	0	0
ReqImpliesValid_A	441843153	598726	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	233992	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233992	0	0
T1	66590	84	0	0
T2	2182	16	0	0
T3	953	12	0	0
T4	290308	4	0	0
T7	267276	12	0	0
T8	11362	18	0	0
T9	5830	52	0	0
T10	17699	214	0	0
T11	1925	17	0	0
T12	581236	502	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233992	0	0
T1	66590	84	0	0
T2	2182	16	0	0
T3	953	12	0	0
T4	290308	4	0	0
T7	267276	12	0	0
T8	11362	18	0	0
T9	5830	52	0	0
T10	17699	214	0	0
T11	1925	17	0	0
T12	581236	502	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233992	0	0
T1	66590	84	0	0
T2	2182	16	0	0
T3	953	12	0	0
T4	290308	4	0	0
T7	267276	12	0	0
T8	11362	18	0	0
T9	5830	52	0	0
T10	17699	214	0	0
T11	1925	17	0	0
T12	581236	502	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3093542	0	0
T1	66590	624	0	0
T2	2182	17	0	0
T3	953	12	0	0
T4	290308	22	0	0
T7	267276	35	0	0
T8	11362	125	0	0
T9	5830	49	0	0
T10	17699	206	0	0
T11	1925	16	0	0
T12	581236	1633	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233992	0	0
T1	66590	84	0	0
T2	2182	16	0	0
T3	953	12	0	0
T4	290308	4	0	0
T7	267276	12	0	0
T8	11362	18	0	0
T9	5830	52	0	0
T10	17699	214	0	0
T11	1925	17	0	0
T12	581236	502	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233992	0	0
T1	66590	84	0	0
T2	2182	16	0	0
T3	953	12	0	0
T4	290308	4	0	0
T7	267276	12	0	0
T8	11362	18	0	0
T9	5830	52	0	0
T10	17699	214	0	0
T11	1925	17	0	0
T12	581236	502	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	598726	0	0
T1	66590	84	0	0
T2	2182	16	0	0
T3	953	13	0	0
T4	290308	4	0	0
T7	267276	12	0	0
T8	11362	18	0	0
T9	5830	56	0	0
T10	17699	223	0	0
T11	1925	19	0	0
T12	581236	1172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	233992	0	0
T1	66590	84	0	0
T2	2182	16	0	0
T3	953	12	0	0
T4	290308	4	0	0
T7	267276	12	0	0
T8	11362	18	0	0
T9	5830	52	0	0
T10	17699	214	0	0
T11	1925	17	0	0
T12	581236	502	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	216914	0	0
GntImpliesValid_A	441843153	216914	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	216914	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3043045	0	0
ReadyAndValidImplyGrant_A	441843153	216914	0	0
ReqAndReadyImplyGrant_A	441843153	216914	0	0
ReqImpliesValid_A	441843153	531690	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	216914	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	216914	0	0
T1	66590	97	0	0
T2	2182	13	0	0
T3	953	9	0	0
T4	290308	7	0	0
T7	267276	8	0	0
T8	11362	17	0	0
T9	5830	60	0	0
T10	17699	253	0	0
T11	1925	9	0	0
T12	581236	970	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	216914	0	0
T1	66590	97	0	0
T2	2182	13	0	0
T3	953	9	0	0
T4	290308	7	0	0
T7	267276	8	0	0
T8	11362	17	0	0
T9	5830	60	0	0
T10	17699	253	0	0
T11	1925	9	0	0
T12	581236	970	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	216914	0	0
T1	66590	97	0	0
T2	2182	13	0	0
T3	953	9	0	0
T4	290308	7	0	0
T7	267276	8	0	0
T8	11362	17	0	0
T9	5830	60	0	0
T10	17699	253	0	0
T11	1925	9	0	0
T12	581236	970	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3043045	0	0
T1	66590	843	0	0
T2	2182	13	0	0
T3	953	9	0	0
T4	290308	21	0	0
T7	267276	38	0	0
T8	11362	91	0	0
T9	5830	59	0	0
T10	17699	237	0	0
T11	1925	9	0	0
T12	581236	3228	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	216914	0	0
T1	66590	97	0	0
T2	2182	13	0	0
T3	953	9	0	0
T4	290308	7	0	0
T7	267276	8	0	0
T8	11362	17	0	0
T9	5830	60	0	0
T10	17699	253	0	0
T11	1925	9	0	0
T12	581236	970	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	216914	0	0
T1	66590	97	0	0
T2	2182	13	0	0
T3	953	9	0	0
T4	290308	7	0	0
T7	267276	8	0	0
T8	11362	17	0	0
T9	5830	60	0	0
T10	17699	253	0	0
T11	1925	9	0	0
T12	581236	970	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	531690	0	0
T1	66590	113	0	0
T2	2182	14	0	0
T3	953	10	0	0
T4	290308	13	0	0
T7	267276	9	0	0
T8	11362	29	0	0
T9	5830	62	0	0
T10	17699	270	0	0
T11	1925	10	0	0
T12	581236	2371	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	216914	0	0
T1	66590	97	0	0
T2	2182	13	0	0
T3	953	9	0	0
T4	290308	7	0	0
T7	267276	8	0	0
T8	11362	17	0	0
T9	5830	60	0	0
T10	17699	253	0	0
T11	1925	9	0	0
T12	581236	970	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	248555	0	0
GntImpliesValid_A	441843153	248555	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	248555	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3191906	0	0
ReadyAndValidImplyGrant_A	441843153	248555	0	0
ReqAndReadyImplyGrant_A	441843153	248555	0	0
ReqImpliesValid_A	441843153	597175	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	248555	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	248555	0	0
T1	66590	92	0	0
T2	2182	8	0	0
T3	953	13	0	0
T4	290308	6	0	0
T7	267276	13	0	0
T8	11362	14	0	0
T9	5830	113	0	0
T10	17699	272	0	0
T11	1925	2	0	0
T12	581236	463	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	248555	0	0
T1	66590	92	0	0
T2	2182	8	0	0
T3	953	13	0	0
T4	290308	6	0	0
T7	267276	13	0	0
T8	11362	14	0	0
T9	5830	113	0	0
T10	17699	272	0	0
T11	1925	2	0	0
T12	581236	463	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	248555	0	0
T1	66590	92	0	0
T2	2182	8	0	0
T3	953	13	0	0
T4	290308	6	0	0
T7	267276	13	0	0
T8	11362	14	0	0
T9	5830	113	0	0
T10	17699	272	0	0
T11	1925	2	0	0
T12	581236	463	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3191906	0	0
T1	66590	654	0	0
T2	2182	9	0	0
T3	953	13	0	0
T4	290308	24	0	0
T7	267276	39	0	0
T8	11362	128	0	0
T9	5830	109	0	0
T10	17699	249	0	0
T11	1925	3	0	0
T12	581236	1459	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	248555	0	0
T1	66590	92	0	0
T2	2182	8	0	0
T3	953	13	0	0
T4	290308	6	0	0
T7	267276	13	0	0
T8	11362	14	0	0
T9	5830	113	0	0
T10	17699	272	0	0
T11	1925	2	0	0
T12	581236	463	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	248555	0	0
T1	66590	92	0	0
T2	2182	8	0	0
T3	953	13	0	0
T4	290308	6	0	0
T7	267276	13	0	0
T8	11362	14	0	0
T9	5830	113	0	0
T10	17699	272	0	0
T11	1925	2	0	0
T12	581236	463	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	597175	0	0
T1	66590	112	0	0
T2	2182	8	0	0
T3	953	14	0	0
T4	290308	6	0	0
T7	267276	13	0	0
T8	11362	23	0	0
T9	5830	118	0	0
T10	17699	296	0	0
T11	1925	2	0	0
T12	581236	1182	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	248555	0	0
T1	66590	92	0	0
T2	2182	8	0	0
T3	953	13	0	0
T4	290308	6	0	0
T7	267276	13	0	0
T8	11362	14	0	0
T9	5830	113	0	0
T10	17699	272	0	0
T11	1925	2	0	0
T12	581236	463	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	231370	0	0
GntImpliesValid_A	441843153	231370	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	231370	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3059868	0	0
ReadyAndValidImplyGrant_A	441843153	231370	0	0
ReqAndReadyImplyGrant_A	441843153	231370	0	0
ReqImpliesValid_A	441843153	568055	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	231370	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	231370	0	0
T1	66590	86	0	0
T2	2182	6	0	0
T3	953	9	0	0
T4	290308	10	0	0
T7	267276	12	0	0
T8	11362	22	0	0
T9	5830	52	0	0
T10	17699	231	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	231370	0	0
T1	66590	86	0	0
T2	2182	6	0	0
T3	953	9	0	0
T4	290308	10	0	0
T7	267276	12	0	0
T8	11362	22	0	0
T9	5830	52	0	0
T10	17699	231	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	231370	0	0
T1	66590	86	0	0
T2	2182	6	0	0
T3	953	9	0	0
T4	290308	10	0	0
T7	267276	12	0	0
T8	11362	22	0	0
T9	5830	52	0	0
T10	17699	231	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3059868	0	0
T1	66590	665	0	0
T2	2182	7	0	0
T3	953	9	0	0
T4	290308	50	0	0
T7	267276	49	0	0
T8	11362	138	0	0
T9	5830	53	0	0
T10	17699	219	0	0
T11	1925	7	0	0
T12	581236	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	231370	0	0
T1	66590	86	0	0
T2	2182	6	0	0
T3	953	9	0	0
T4	290308	10	0	0
T7	267276	12	0	0
T8	11362	22	0	0
T9	5830	52	0	0
T10	17699	231	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	231370	0	0
T1	66590	86	0	0
T2	2182	6	0	0
T3	953	9	0	0
T4	290308	10	0	0
T7	267276	12	0	0
T8	11362	22	0	0
T9	5830	52	0	0
T10	17699	231	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	568055	0	0
T1	66590	103	0	0
T2	2182	6	0	0
T3	953	10	0	0
T4	290308	13	0	0
T7	267276	12	0	0
T8	11362	34	0	0
T9	5830	52	0	0
T10	17699	244	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	231370	0	0
T1	66590	86	0	0
T2	2182	6	0	0
T3	953	9	0	0
T4	290308	10	0	0
T7	267276	12	0	0
T8	11362	22	0	0
T9	5830	52	0	0
T10	17699	231	0	0
T11	1925	6	0	0
T12	581236	0	0	0
T13	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	227923	0	0
GntImpliesValid_A	441843153	227923	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	227923	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3022060	0	0
ReadyAndValidImplyGrant_A	441843153	227923	0	0
ReqAndReadyImplyGrant_A	441843153	227923	0	0
ReqImpliesValid_A	441843153	574425	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	227923	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227923	0	0
T1	66590	93	0	0
T2	2182	11	0	0
T3	953	17	0	0
T4	290308	13	0	0
T7	267276	17	0	0
T8	11362	10	0	0
T9	5830	61	0	0
T10	17699	236	0	0
T11	1925	8	0	0
T12	581236	524	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227923	0	0
T1	66590	93	0	0
T2	2182	11	0	0
T3	953	17	0	0
T4	290308	13	0	0
T7	267276	17	0	0
T8	11362	10	0	0
T9	5830	61	0	0
T10	17699	236	0	0
T11	1925	8	0	0
T12	581236	524	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227923	0	0
T1	66590	93	0	0
T2	2182	11	0	0
T3	953	17	0	0
T4	290308	13	0	0
T7	267276	17	0	0
T8	11362	10	0	0
T9	5830	61	0	0
T10	17699	236	0	0
T11	1925	8	0	0
T12	581236	524	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3022060	0	0
T1	66590	746	0	0
T2	2182	11	0	0
T3	953	18	0	0
T4	290308	54	0	0
T7	267276	76	0	0
T8	11362	72	0	0
T9	5830	60	0	0
T10	17699	226	0	0
T11	1925	9	0	0
T12	581236	1902	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227923	0	0
T1	66590	93	0	0
T2	2182	11	0	0
T3	953	17	0	0
T4	290308	13	0	0
T7	267276	17	0	0
T8	11362	10	0	0
T9	5830	61	0	0
T10	17699	236	0	0
T11	1925	8	0	0
T12	581236	524	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227923	0	0
T1	66590	93	0	0
T2	2182	11	0	0
T3	953	17	0	0
T4	290308	13	0	0
T7	267276	17	0	0
T8	11362	10	0	0
T9	5830	61	0	0
T10	17699	236	0	0
T11	1925	8	0	0
T12	581236	524	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	574425	0	0
T1	66590	93	0	0
T2	2182	12	0	0
T3	953	17	0	0
T4	290308	31	0	0
T7	267276	41	0	0
T8	11362	10	0	0
T9	5830	63	0	0
T10	17699	247	0	0
T11	1925	8	0	0
T12	581236	1156	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	227923	0	0
T1	66590	93	0	0
T2	2182	11	0	0
T3	953	17	0	0
T4	290308	13	0	0
T7	267276	17	0	0
T8	11362	10	0	0
T9	5830	61	0	0
T10	17699	236	0	0
T11	1925	8	0	0
T12	581236	524	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	235614	0	0
GntImpliesValid_A	441843153	235614	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	235614	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3013563	0	0
ReadyAndValidImplyGrant_A	441843153	235614	0	0
ReqAndReadyImplyGrant_A	441843153	235614	0	0
ReqImpliesValid_A	441843153	606677	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	235614	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	235614	0	0
T1	66590	94	0	0
T2	2182	11	0	0
T3	953	8	0	0
T4	290308	11	0	0
T7	267276	10	0	0
T8	11362	16	0	0
T9	5830	54	0	0
T10	17699	222	0	0
T11	1925	12	0	0
T12	581236	452	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	235614	0	0
T1	66590	94	0	0
T2	2182	11	0	0
T3	953	8	0	0
T4	290308	11	0	0
T7	267276	10	0	0
T8	11362	16	0	0
T9	5830	54	0	0
T10	17699	222	0	0
T11	1925	12	0	0
T12	581236	452	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	235614	0	0
T1	66590	94	0	0
T2	2182	11	0	0
T3	953	8	0	0
T4	290308	11	0	0
T7	267276	10	0	0
T8	11362	16	0	0
T9	5830	54	0	0
T10	17699	222	0	0
T11	1925	12	0	0
T12	581236	452	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3013563	0	0
T1	66590	717	0	0
T2	2182	12	0	0
T3	953	9	0	0
T4	290308	56	0	0
T7	267276	43	0	0
T8	11362	114	0	0
T9	5830	52	0	0
T10	17699	217	0	0
T11	1925	13	0	0
T12	581236	1444	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	235614	0	0
T1	66590	94	0	0
T2	2182	11	0	0
T3	953	8	0	0
T4	290308	11	0	0
T7	267276	10	0	0
T8	11362	16	0	0
T9	5830	54	0	0
T10	17699	222	0	0
T11	1925	12	0	0
T12	581236	452	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	235614	0	0
T1	66590	94	0	0
T2	2182	11	0	0
T3	953	8	0	0
T4	290308	11	0	0
T7	267276	10	0	0
T8	11362	16	0	0
T9	5830	54	0	0
T10	17699	222	0	0
T11	1925	12	0	0
T12	581236	452	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	606677	0	0
T1	66590	102	0	0
T2	2182	11	0	0
T3	953	8	0	0
T4	290308	19	0	0
T7	267276	12	0	0
T8	11362	16	0	0
T9	5830	57	0	0
T10	17699	228	0	0
T11	1925	12	0	0
T12	581236	1070	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	235614	0	0
T1	66590	94	0	0
T2	2182	11	0	0
T3	953	8	0	0
T4	290308	11	0	0
T7	267276	10	0	0
T8	11362	16	0	0
T9	5830	54	0	0
T10	17699	222	0	0
T11	1925	12	0	0
T12	581236	452	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	236064	0	0
GntImpliesValid_A	441843153	236064	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	236064	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3038521	0	0
ReadyAndValidImplyGrant_A	441843153	236064	0	0
ReqAndReadyImplyGrant_A	441843153	236064	0	0
ReqImpliesValid_A	441843153	620858	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	236064	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	236064	0	0
T1	66590	98	0	0
T2	2182	6	0	0
T3	953	19	0	0
T4	290308	7	0	0
T7	267276	12	0	0
T8	11362	12	0	0
T9	5830	47	0	0
T10	17699	229	0	0
T11	1925	15	0	0
T12	581236	947	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	236064	0	0
T1	66590	98	0	0
T2	2182	6	0	0
T3	953	19	0	0
T4	290308	7	0	0
T7	267276	12	0	0
T8	11362	12	0	0
T9	5830	47	0	0
T10	17699	229	0	0
T11	1925	15	0	0
T12	581236	947	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	236064	0	0
T1	66590	98	0	0
T2	2182	6	0	0
T3	953	19	0	0
T4	290308	7	0	0
T7	267276	12	0	0
T8	11362	12	0	0
T9	5830	47	0	0
T10	17699	229	0	0
T11	1925	15	0	0
T12	581236	947	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3038521	0	0
T1	66590	747	0	0
T2	2182	7	0	0
T3	953	19	0	0
T4	290308	34	0	0
T7	267276	54	0	0
T8	11362	90	0	0
T9	5830	47	0	0
T10	17699	219	0	0
T11	1925	15	0	0
T12	581236	2802	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	236064	0	0
T1	66590	98	0	0
T2	2182	6	0	0
T3	953	19	0	0
T4	290308	7	0	0
T7	267276	12	0	0
T8	11362	12	0	0
T9	5830	47	0	0
T10	17699	229	0	0
T11	1925	15	0	0
T12	581236	947	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	236064	0	0
T1	66590	98	0	0
T2	2182	6	0	0
T3	953	19	0	0
T4	290308	7	0	0
T7	267276	12	0	0
T8	11362	12	0	0
T9	5830	47	0	0
T10	17699	229	0	0
T11	1925	15	0	0
T12	581236	947	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	620858	0	0
T1	66590	98	0	0
T2	2182	6	0	0
T3	953	20	0	0
T4	290308	7	0	0
T7	267276	12	0	0
T8	11362	12	0	0
T9	5830	48	0	0
T10	17699	240	0	0
T11	1925	16	0	0
T12	581236	2354	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	236064	0	0
T1	66590	98	0	0
T2	2182	6	0	0
T3	953	19	0	0
T4	290308	7	0	0
T7	267276	12	0	0
T8	11362	12	0	0
T9	5830	47	0	0
T10	17699	229	0	0
T11	1925	15	0	0
T12	581236	947	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	228785	0	0
GntImpliesValid_A	441843153	228785	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	228785	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	3094020	0	0
ReadyAndValidImplyGrant_A	441843153	228785	0	0
ReqAndReadyImplyGrant_A	441843153	228785	0	0
ReqImpliesValid_A	441843153	563798	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	0	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	228785	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228785	0	0
T1	66590	82	0	0
T2	2182	14	0	0
T3	953	16	0	0
T4	290308	9	0	0
T7	267276	14	0	0
T8	11362	7	0	0
T9	5830	59	0	0
T10	17699	232	0	0
T11	1925	11	0	0
T12	581236	471	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228785	0	0
T1	66590	82	0	0
T2	2182	14	0	0
T3	953	16	0	0
T4	290308	9	0	0
T7	267276	14	0	0
T8	11362	7	0	0
T9	5830	59	0	0
T10	17699	232	0	0
T11	1925	11	0	0
T12	581236	471	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228785	0	0
T1	66590	82	0	0
T2	2182	14	0	0
T3	953	16	0	0
T4	290308	9	0	0
T7	267276	14	0	0
T8	11362	7	0	0
T9	5830	59	0	0
T10	17699	232	0	0
T11	1925	11	0	0
T12	581236	471	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	3094020	0	0
T1	66590	679	0	0
T2	2182	12	0	0
T3	953	16	0	0
T4	290308	28	0	0
T7	267276	64	0	0
T8	11362	52	0	0
T9	5830	59	0	0
T10	17699	221	0	0
T11	1925	12	0	0
T12	581236	1482	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228785	0	0
T1	66590	82	0	0
T2	2182	14	0	0
T3	953	16	0	0
T4	290308	9	0	0
T7	267276	14	0	0
T8	11362	7	0	0
T9	5830	59	0	0
T10	17699	232	0	0
T11	1925	11	0	0
T12	581236	471	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228785	0	0
T1	66590	82	0	0
T2	2182	14	0	0
T3	953	16	0	0
T4	290308	9	0	0
T7	267276	14	0	0
T8	11362	7	0	0
T9	5830	59	0	0
T10	17699	232	0	0
T11	1925	11	0	0
T12	581236	471	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	563798	0	0
T1	66590	89	0	0
T2	2182	17	0	0
T3	953	17	0	0
T4	290308	12	0	0
T7	267276	14	0	0
T8	11362	11	0	0
T9	5830	60	0	0
T10	17699	244	0	0
T11	1925	11	0	0
T12	581236	1218	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	228785	0	0
T1	66590	82	0	0
T2	2182	14	0	0
T3	953	16	0	0
T4	290308	9	0	0
T7	267276	14	0	0
T8	11362	7	0	0
T9	5830	59	0	0
T10	17699	232	0	0
T11	1925	11	0	0
T12	581236	471	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	934623	0	0
GntImpliesValid_A	441843153	934623	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	934623	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	11419271	0	0
ReadyAndValidImplyGrant_A	441843153	934623	0	0
ReqAndReadyImplyGrant_A	441843153	934623	0	0
ReqImpliesValid_A	441843153	2357279	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	16735	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	934623	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	934623	0	0
T1	66590	360	0	0
T2	2182	52	0	0
T3	953	59	0	0
T4	290308	41	0	0
T7	267276	65	0	0
T8	11362	62	0	0
T9	5830	279	0	0
T10	17699	1037	0	0
T11	1925	40	0	0
T12	581236	1042	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	934623	0	0
T1	66590	360	0	0
T2	2182	52	0	0
T3	953	59	0	0
T4	290308	41	0	0
T7	267276	65	0	0
T8	11362	62	0	0
T9	5830	279	0	0
T10	17699	1037	0	0
T11	1925	40	0	0
T12	581236	1042	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	934623	0	0
T1	66590	360	0	0
T2	2182	52	0	0
T3	953	59	0	0
T4	290308	41	0	0
T7	267276	65	0	0
T8	11362	62	0	0
T9	5830	279	0	0
T10	17699	1037	0	0
T11	1925	40	0	0
T12	581236	1042	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	11419271	0	0
T1	66590	2429	0	0
T2	2182	1	0	0
T3	953	1	0	0
T4	290308	162	0	0
T7	267276	202	0	0
T8	11362	398	0	0
T9	5830	1	0	0
T10	17699	1	0	0
T11	1925	1	0	0
T12	581236	3505	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	934623	0	0
T1	66590	360	0	0
T2	2182	52	0	0
T3	953	59	0	0
T4	290308	41	0	0
T7	267276	65	0	0
T8	11362	62	0	0
T9	5830	279	0	0
T10	17699	1037	0	0
T11	1925	40	0	0
T12	581236	1042	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	934623	0	0
T1	66590	360	0	0
T2	2182	52	0	0
T3	953	59	0	0
T4	290308	41	0	0
T7	267276	65	0	0
T8	11362	62	0	0
T9	5830	279	0	0
T10	17699	1037	0	0
T11	1925	40	0	0
T12	581236	1042	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	2357279	0	0
T1	66590	378	0	0
T2	2182	52	0	0
T3	953	59	0	0
T4	290308	52	0	0
T7	267276	97	0	0
T8	11362	96	0	0
T9	5830	279	0	0
T10	17699	1037	0	0
T11	1925	40	0	0
T12	581236	1296	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	16735	0	900
T3	953	4	0	1
T4	290308	0	0	1
T7	267276	0	0	1
T8	11362	0	0	1
T9	5830	5	0	1
T10	17699	16	0	1
T11	1925	0	0	1
T12	581236	0	0	1
T13	10250	0	0	1
T14	0	28	0	0
T15	0	6	0	0
T16	0	4	0	0
T17	0	2	0	0
T18	0	7	0	0
T20	0	6	0	0
T21	0	6	0	0
T23	268615	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	934623	0	0
T1	66590	360	0	0
T2	2182	52	0	0
T3	953	59	0	0
T4	290308	41	0	0
T7	267276	65	0	0
T8	11362	62	0	0
T9	5830	279	0	0
T10	17699	1037	0	0
T11	1925	40	0	0
T12	581236	1042	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441843153	441714947	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441843153	928738	0	0
GntImpliesValid_A	441843153	928738	0	0
GrantKnown_A	441843153	441714947	0	0
IdxKnown_A	441843153	441714947	0	0
IndexIsCorrect_A	441843153	928738	0	0
LockArbDecision_A	441843153	0	0	0
NoReadyValidNoGrant_A	441843153	369855452	0	0
ReadyAndValidImplyGrant_A	441843153	928738	0	0
ReqAndReadyImplyGrant_A	441843153	928738	0	0
ReqImpliesValid_A	441843153	13320221	0	0
ReqStaysHighUntilGranted0_M	441843153	0	0	0
RoundRobin_A	441843153	29400	0	900
ValidKnown_A	441843153	441714947	0	0
gen_data_port_assertion.DataFlow_A	441843153	928738	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	928738	0	0
T1	66590	373	0	0
T2	2182	47	0	0
T3	953	48	0	0
T4	290308	36	0	0
T7	267276	53	0	0
T8	11362	42	0	0
T9	5830	243	0	0
T10	17699	1038	0	0
T11	1925	57	0	0
T12	581236	956	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	928738	0	0
T1	66590	373	0	0
T2	2182	47	0	0
T3	953	48	0	0
T4	290308	36	0	0
T7	267276	53	0	0
T8	11362	42	0	0
T9	5830	243	0	0
T10	17699	1038	0	0
T11	1925	57	0	0
T12	581236	956	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	928738	0	0
T1	66590	373	0	0
T2	2182	47	0	0
T3	953	48	0	0
T4	290308	36	0	0
T7	267276	53	0	0
T8	11362	42	0	0
T9	5830	243	0	0
T10	17699	1038	0	0
T11	1925	57	0	0
T12	581236	956	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	369855452	0	0
T1	66590	57889	0	0
T2	2182	1	0	0
T3	953	1	0	0
T4	290308	241725	0	0
T7	267276	222769	0	0
T8	11362	9907	0	0
T9	5830	1	0	0
T10	17699	1	0	0
T11	1925	1	0	0
T12	581236	484092	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	928738	0	0
T1	66590	373	0	0
T2	2182	47	0	0
T3	953	48	0	0
T4	290308	36	0	0
T7	267276	53	0	0
T8	11362	42	0	0
T9	5830	243	0	0
T10	17699	1038	0	0
T11	1925	57	0	0
T12	581236	956	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	928738	0	0
T1	66590	373	0	0
T2	2182	47	0	0
T3	953	48	0	0
T4	290308	36	0	0
T7	267276	53	0	0
T8	11362	42	0	0
T9	5830	243	0	0
T10	17699	1038	0	0
T11	1925	57	0	0
T12	581236	956	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	13320221	0	0
T1	66590	2874	0	0
T2	2182	47	0	0
T3	953	48	0	0
T4	290308	168	0	0
T7	267276	216	0	0
T8	11362	343	0	0
T9	5830	243	0	0
T10	17699	1038	0	0
T11	1925	57	0	0
T12	581236	4217	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	29400	0	900
T10	17699	13	0	1
T11	1925	0	0	1
T12	581236	0	0	1
T13	10250	0	0	1
T14	242773	14	0	1
T15	387928	1	0	1
T16	668955	17	0	1
T17	4694	5	0	1
T18	0	6	0	0
T19	0	2	0	0
T20	0	6	0	0
T21	0	3	0	0
T22	0	13	0	0
T23	268615	0	0	1
T24	131139	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	441714947	0	0
T1	66590	66524	0	0
T2	2182	2130	0	0
T3	953	930	0	0
T4	290308	290263	0	0
T7	267276	267265	0	0
T8	11362	11353	0	0
T9	5830	5795	0	0
T10	17699	17660	0	0
T11	1925	1871	0	0
T12	581236	581234	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441843153	928738	0	0
T1	66590	373	0	0
T2	2182	47	0	0
T3	953	48	0	0
T4	290308	36	0	0
T7	267276	53	0	0
T8	11362	42	0	0
T9	5830	243	0	0
T10	17699	1038	0	0
T11	1925	57	0	0
T12	581236	956	0	0