Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1495036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

237353

1

T1

18

T2

2853

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	588101	1			T1	48		T2	7032		T3	55
values[0x0]	556914	1			T1	44		T2	6777		T3	61
values[0x1]	587374	1			T1	58		T2	6895		T3	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1155346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

577043

1

T1

55

T2

6953

T3

74

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26417	1			T1	3		T2	329		T7	185
valid_sources[0x01]	26883	1			T1	2		T2	303		T3	1
valid_sources[0x02]	27491	1			T1	1		T2	317		T7	230
valid_sources[0x03]	26406	1			T1	3		T2	336		T7	89
valid_sources[0x04]	28171	1			T1	6		T2	331		T3	3
valid_sources[0x05]	27054	1			T1	2		T2	333		T7	219
valid_sources[0x06]	28396	1			T2	329		T7	131		T8	30
valid_sources[0x07]	26901	1			T1	1		T2	323		T7	185
valid_sources[0x08]	27068	1			T2	349		T7	536		T8	46
valid_sources[0x09]	27030	1			T1	4		T2	342		T7	291
valid_sources[0x0a]	26906	1			T1	3		T2	294		T7	84
valid_sources[0x0b]	26429	1			T1	1		T2	317		T7	145
valid_sources[0x0c]	27851	1			T1	1		T2	346		T3	24
valid_sources[0x0d]	26089	1			T1	1		T2	321		T7	410
valid_sources[0x0e]	26261	1			T1	2		T2	314		T3	32
valid_sources[0x0f]	28288	1			T1	2		T2	347		T7	292
valid_sources[0x10]	26669	1			T1	4		T2	324		T7	83
valid_sources[0x11]	28206	1			T1	5		T2	372		T3	12
valid_sources[0x12]	26874	1			T1	3		T2	299		T3	9
valid_sources[0x13]	27888	1			T1	2		T2	343		T7	187
valid_sources[0x14]	27755	1			T1	1		T2	305		T7	119
valid_sources[0x15]	27236	1			T1	4		T2	282		T3	5
valid_sources[0x16]	27770	1			T1	1		T2	344		T7	217
valid_sources[0x17]	27122	1			T1	5		T2	333		T7	251
valid_sources[0x18]	26241	1			T1	2		T2	329		T7	95
valid_sources[0x19]	27256	1			T1	1		T2	329		T7	293
valid_sources[0x1a]	27750	1			T1	2		T2	285		T7	204
valid_sources[0x1b]	27415	1			T1	4		T2	290		T7	218
valid_sources[0x1c]	26661	1			T2	360		T3	21		T7	103
valid_sources[0x1d]	26611	1			T1	3		T2	302		T7	134
valid_sources[0x1e]	26742	1			T1	2		T2	316		T7	191
valid_sources[0x1f]	26619	1			T1	2		T2	302		T7	122
valid_sources[0x20]	26552	1			T1	4		T2	381		T7	101

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24854

1

T1

2

T2

282

T3

2

values[0x0]

all_enables

biggest_size

187498

1

T1

14

T2

2276

T3

24

values[0x1]

all_enables

biggest_size

25001

1

T1

2

T2

295

T3

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1514571	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246341

1

T1

29

T2

2908

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	602252	1			T1	48		T2	6792		T3	67
values[0x0]	556262	1			T1	59		T2	6513		T3	60
values[0x1]	602398	1			T1	40		T2	6912		T3	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1163236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

597676

1

T1

52

T2

6899

T3

57

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27912	1			T1	1		T2	310		T3	1
valid_sources[0x01]	27351	1			T1	9		T2	347		T3	5
valid_sources[0x02]	27845	1			T2	295		T3	2		T7	203
valid_sources[0x03]	27405	1			T2	276		T3	2		T7	204
valid_sources[0x04]	27801	1			T1	4		T2	313		T3	7
valid_sources[0x05]	27493	1			T1	2		T2	276		T3	6
valid_sources[0x06]	27140	1			T1	2		T2	330		T7	208
valid_sources[0x07]	27765	1			T1	1		T2	311		T3	5
valid_sources[0x08]	27283	1			T1	1		T2	319		T3	5
valid_sources[0x09]	27242	1			T1	3		T2	314		T7	214
valid_sources[0x0a]	27378	1			T1	1		T2	290		T7	211
valid_sources[0x0b]	27015	1			T1	2		T2	331		T3	2
valid_sources[0x0c]	27749	1			T1	6		T2	347		T3	3
valid_sources[0x0d]	27162	1			T2	309		T3	1		T7	225
valid_sources[0x0e]	27309	1			T1	5		T2	282		T3	10
valid_sources[0x0f]	27986	1			T1	8		T2	308		T3	1
valid_sources[0x10]	27875	1			T1	3		T2	295		T7	221
valid_sources[0x11]	28053	1			T1	2		T2	346		T3	1
valid_sources[0x12]	27795	1			T1	2		T2	336		T3	3
valid_sources[0x13]	27424	1			T1	6		T2	330		T3	2
valid_sources[0x14]	27379	1			T1	1		T2	303		T3	11
valid_sources[0x15]	27756	1			T1	1		T2	278		T3	3
valid_sources[0x16]	27380	1			T1	5		T2	334		T3	1
valid_sources[0x17]	28255	1			T2	321		T7	197		T8	30
valid_sources[0x18]	27410	1			T2	298		T3	2		T7	222
valid_sources[0x19]	27525	1			T2	286		T3	1		T7	210
valid_sources[0x1a]	27268	1			T2	291		T7	188		T8	39
valid_sources[0x1b]	27557	1			T1	2		T2	309		T3	3
valid_sources[0x1c]	27889	1			T1	6		T2	326		T3	3
valid_sources[0x1d]	28362	1			T1	4		T2	324		T3	3
valid_sources[0x1e]	27341	1			T1	1		T2	318		T3	3
valid_sources[0x1f]	27869	1			T2	359		T3	5		T7	140
valid_sources[0x20]	27176	1			T1	4		T2	299		T3	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25873

1

T1

4

T2

287

T3

5

values[0x0]

all_enables

biggest_size

194878

1

T1

24

T2

2349

T3

17

values[0x1]

all_enables

biggest_size

25590

1

T1

1

T2

272

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1512065	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

240032

1

T1

15

T2

2907

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	594678	1			T1	31		T2	7039		T3	36
values[0x0]	563125	1			T1	39		T2	6799		T3	36
values[0x1]	594294	1			T1	43		T2	7048		T3	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1169041	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

583056

1

T1

38

T2

6981

T3

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27329	1			T1	2		T2	311		T7	184
valid_sources[0x01]	27387	1			T1	6		T2	277		T7	169
valid_sources[0x02]	27406	1			T1	4		T2	397		T7	148
valid_sources[0x03]	26481	1			T1	1		T2	303		T3	6
valid_sources[0x04]	27701	1			T1	3		T2	339		T7	153
valid_sources[0x05]	28192	1			T1	1		T2	355		T7	260
valid_sources[0x06]	26891	1			T1	3		T2	340		T3	2
valid_sources[0x07]	27306	1			T1	1		T2	284		T7	104
valid_sources[0x08]	27182	1			T1	1		T2	365		T7	147
valid_sources[0x09]	27523	1			T1	1		T2	263		T7	252
valid_sources[0x0a]	27318	1			T2	316		T3	3		T7	255
valid_sources[0x0b]	27525	1			T1	4		T2	296		T7	210
valid_sources[0x0c]	27422	1			T1	4		T2	253		T7	298
valid_sources[0x0d]	26817	1			T1	3		T2	327		T7	154
valid_sources[0x0e]	27290	1			T1	1		T2	334		T7	128
valid_sources[0x0f]	28564	1			T1	1		T2	310		T7	299
valid_sources[0x10]	27497	1			T1	2		T2	302		T7	104
valid_sources[0x11]	27335	1			T1	1		T2	349		T7	282
valid_sources[0x12]	28885	1			T1	1		T2	373		T7	476
valid_sources[0x13]	27644	1			T2	306		T7	203		T8	34
valid_sources[0x14]	27426	1			T1	1		T2	247		T7	73
valid_sources[0x15]	27343	1			T1	1		T2	263		T3	10
valid_sources[0x16]	27990	1			T1	2		T2	318		T7	195
valid_sources[0x17]	27636	1			T1	1		T2	381		T7	257
valid_sources[0x18]	27327	1			T1	1		T2	323		T7	117
valid_sources[0x19]	27168	1			T2	259		T7	140		T8	25
valid_sources[0x1a]	27965	1			T1	3		T2	380		T3	16
valid_sources[0x1b]	27179	1			T1	1		T2	403		T7	291
valid_sources[0x1c]	26938	1			T1	1		T2	359		T7	222
valid_sources[0x1d]	26578	1			T1	1		T2	286		T7	138
valid_sources[0x1e]	26554	1			T1	1		T2	326		T7	145
valid_sources[0x1f]	27583	1			T1	2		T2	325		T7	99
valid_sources[0x20]	26150	1			T1	1		T2	340		T7	124

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25065

1

T1

1

T2

288

T3

1

values[0x0]

all_enables

biggest_size

189844

1

T1

14

T2

2312

T3

16

values[0x1]

all_enables

biggest_size

25123

1

T2

307

T3

1

T7

172