Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7457052	0	0
GntImpliesValid_A	2147483647	7457052	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7457052	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	453720539	0	0
ReadyAndValidImplyGrant_A	2147483647	7457052	0	0
ReqAndReadyImplyGrant_A	2147483647	7457052	0	0
ReqImpliesValid_A	2147483647	32771579	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	47311	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7457052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7448112	7446576	0	0
T2	12403152	12401424	0	0
T3	5562000	5561400	0	0
T4	10247496	10245960	0	0
T7	1724208	1722768	0	0
T8	7343784	7343712	0	0
T9	1213152	1212168	0	0
T10	44280	43368	0	0
T11	15819744	15818784	0	0
T12	60648	58776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7457052	0	0
T1	7448112	410	0	0
T2	12403152	51860	0	0
T3	5562000	476	0	0
T4	10247496	474	0	0
T7	1724208	33650	0	0
T8	7343784	6260	0	0
T9	1213152	3528	0	0
T10	44280	391	0	0
T11	15819744	1366	0	0
T12	60648	408	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7457052	0	0
T1	7448112	410	0	0
T2	12403152	51860	0	0
T3	5562000	476	0	0
T4	10247496	474	0	0
T7	1724208	33650	0	0
T8	7343784	6260	0	0
T9	1213152	3528	0	0
T10	44280	391	0	0
T11	15819744	1366	0	0
T12	60648	408	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7448112	7446576	0	0
T2	12403152	12401424	0	0
T3	5562000	5561400	0	0
T4	10247496	10245960	0	0
T7	1724208	1722768	0	0
T8	7343784	7343712	0	0
T9	1213152	1212168	0	0
T10	44280	43368	0	0
T11	15819744	15818784	0	0
T12	60648	58776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7448112	7446576	0	0
T2	12403152	12401424	0	0
T3	5562000	5561400	0	0
T4	10247496	10245960	0	0
T7	1724208	1722768	0	0
T8	7343784	7343712	0	0
T9	1213152	1212168	0	0
T10	44280	43368	0	0
T11	15819744	15818784	0	0
T12	60648	58776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7457052	0	0
T1	7448112	410	0	0
T2	12403152	51860	0	0
T3	5562000	476	0	0
T4	10247496	474	0	0
T7	1724208	33650	0	0
T8	7343784	6260	0	0
T9	1213152	3528	0	0
T10	44280	391	0	0
T11	15819744	1366	0	0
T12	60648	408	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	453720539	0	0
T1	7448112	260025	0	0
T2	12403152	713229	0	0
T3	5562000	194910	0	0
T4	10247496	548198	0	0
T7	1724208	21600	0	0
T8	7343784	2054285	0	0
T9	1213152	71028	0	0
T10	44280	496	0	0
T11	15819744	1034891	0	0
T12	60648	760	0	0
T13	0	90462	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7457052	0	0
T1	7448112	410	0	0
T2	12403152	51860	0	0
T3	5562000	476	0	0
T4	10247496	474	0	0
T7	1724208	33650	0	0
T8	7343784	6260	0	0
T9	1213152	3528	0	0
T10	44280	391	0	0
T11	15819744	1366	0	0
T12	60648	408	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7457052	0	0
T1	7448112	410	0	0
T2	12403152	51860	0	0
T3	5562000	476	0	0
T4	10247496	474	0	0
T7	1724208	33650	0	0
T8	7343784	6260	0	0
T9	1213152	3528	0	0
T10	44280	391	0	0
T11	15819744	1366	0	0
T12	60648	408	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32771579	0	0
T1	7448112	817	0	0
T2	12403152	184715	0	0
T3	5562000	806	0	0
T4	10247496	19763	0	0
T7	1724208	63122	0	0
T8	7343784	347985	0	0
T9	1213152	7494	0	0
T10	44280	487	0	0
T11	15819744	86843	0	0
T12	60648	483	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47311	0	21600
T2	1033596	47	0	2
T3	463500	0	0	2
T4	853958	0	0	2
T7	143684	844	0	2
T8	611982	0	0	2
T9	101096	0	0	2
T10	3690	0	0	2
T11	1318312	0	0	2
T12	5054	0	0	2
T13	212492	0	0	2
T14	0	3	0	0
T15	0	481	0	0
T16	0	1	0	0
T17	0	41	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	9	0	0
T22	0	44	0	0
T23	0	8	0	0
T24	0	1	0	0
T25	0	33	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7448112	7446576	0	0
T2	12403152	12401424	0	0
T3	5562000	5561400	0	0
T4	10247496	10245960	0	0
T7	1724208	1722768	0	0
T8	7343784	7343712	0	0
T9	1213152	1212168	0	0
T10	44280	43368	0	0
T11	15819744	15818784	0	0
T12	60648	58776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7457052	0	0
T1	7448112	410	0	0
T2	12403152	51860	0	0
T3	5562000	476	0	0
T4	10247496	474	0	0
T7	1724208	33650	0	0
T8	7343784	6260	0	0
T9	1213152	3528	0	0
T10	44280	391	0	0
T11	15819744	1366	0	0
T12	60648	408	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	820473	0	0
GntImpliesValid_A	422207318	820473	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	820473	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	11326412	0	0
ReadyAndValidImplyGrant_A	422207318	820473	0	0
ReqAndReadyImplyGrant_A	422207318	820473	0	0
ReqImpliesValid_A	422207318	2260500	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	820473	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820473	0	0
T1	310338	54	0	0
T2	516798	6792	0	0
T3	231750	55	0	0
T4	426979	55	0	0
T7	71842	5669	0	0
T8	305991	681	0	0
T9	50548	374	0	0
T10	1845	45	0	0
T11	659156	149	0	0
T12	2527	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820473	0	0
T1	310338	54	0	0
T2	516798	6792	0	0
T3	231750	55	0	0
T4	426979	55	0	0
T7	71842	5669	0	0
T8	305991	681	0	0
T9	50548	374	0	0
T10	1845	45	0	0
T11	659156	149	0	0
T12	2527	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820473	0	0
T1	310338	54	0	0
T2	516798	6792	0	0
T3	231750	55	0	0
T4	426979	55	0	0
T7	71842	5669	0	0
T8	305991	681	0	0
T9	50548	374	0	0
T10	1845	45	0	0
T11	659156	149	0	0
T12	2527	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	11326412	0	0
T1	310338	218	0	0
T2	516798	42093	0	0
T3	231750	244	0	0
T4	426979	15430	0	0
T7	71842	2562	0	0
T8	305991	235788	0	0
T9	50548	2692	0	0
T10	1845	35	0	0
T11	659156	48034	0	0
T12	2527	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820473	0	0
T1	310338	54	0	0
T2	516798	6792	0	0
T3	231750	55	0	0
T4	426979	55	0	0
T7	71842	5669	0	0
T8	305991	681	0	0
T9	50548	374	0	0
T10	1845	45	0	0
T11	659156	149	0	0
T12	2527	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820473	0	0
T1	310338	54	0	0
T2	516798	6792	0	0
T3	231750	55	0	0
T4	426979	55	0	0
T7	71842	5669	0	0
T8	305991	681	0	0
T9	50548	374	0	0
T10	1845	45	0	0
T11	659156	149	0	0
T12	2527	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2260500	0	0
T1	310338	78	0	0
T2	516798	23704	0	0
T3	231750	85	0	0
T4	426979	913	0	0
T7	71842	8778	0	0
T8	305991	20390	0	0
T9	50548	572	0	0
T10	1845	56	0	0
T11	659156	4468	0	0
T12	2527	59	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820473	0	0
T1	310338	54	0	0
T2	516798	6792	0	0
T3	231750	55	0	0
T4	426979	55	0	0
T7	71842	5669	0	0
T8	305991	681	0	0
T9	50548	374	0	0
T10	1845	45	0	0
T11	659156	149	0	0
T12	2527	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	836991	0	0
GntImpliesValid_A	422207318	836991	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	836991	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	11312429	0	0
ReadyAndValidImplyGrant_A	422207318	836991	0	0
ReqAndReadyImplyGrant_A	422207318	836991	0	0
ReqImpliesValid_A	422207318	2307066	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	836991	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	836991	0	0
T1	310338	40	0	0
T2	516798	6662	0	0
T3	231750	70	0	0
T4	426979	46	0	0
T7	71842	4177	0	0
T8	305991	689	0	0
T9	50548	374	0	0
T10	1845	41	0	0
T11	659156	130	0	0
T12	2527	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	836991	0	0
T1	310338	40	0	0
T2	516798	6662	0	0
T3	231750	70	0	0
T4	426979	46	0	0
T7	71842	4177	0	0
T8	305991	689	0	0
T9	50548	374	0	0
T10	1845	41	0	0
T11	659156	130	0	0
T12	2527	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	836991	0	0
T1	310338	40	0	0
T2	516798	6662	0	0
T3	231750	70	0	0
T4	426979	46	0	0
T7	71842	4177	0	0
T8	305991	689	0	0
T9	50548	374	0	0
T10	1845	41	0	0
T11	659156	130	0	0
T12	2527	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	11312429	0	0
T1	310338	179	0	0
T2	516798	40450	0	0
T3	231750	281	0	0
T4	426979	17290	0	0
T7	71842	2491	0	0
T8	305991	238024	0	0
T9	50548	2485	0	0
T10	1845	30	0	0
T11	659156	48215	0	0
T12	2527	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	836991	0	0
T1	310338	40	0	0
T2	516798	6662	0	0
T3	231750	70	0	0
T4	426979	46	0	0
T7	71842	4177	0	0
T8	305991	689	0	0
T9	50548	374	0	0
T10	1845	41	0	0
T11	659156	130	0	0
T12	2527	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	836991	0	0
T1	310338	40	0	0
T2	516798	6662	0	0
T3	231750	70	0	0
T4	426979	46	0	0
T7	71842	4177	0	0
T8	305991	689	0	0
T9	50548	374	0	0
T10	1845	41	0	0
T11	659156	130	0	0
T12	2527	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2307066	0	0
T1	310338	42	0	0
T2	516798	23700	0	0
T3	231750	116	0	0
T4	426979	344	0	0
T7	71842	5865	0	0
T8	305991	23212	0	0
T9	50548	513	0	0
T10	1845	53	0	0
T11	659156	5812	0	0
T12	2527	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	836991	0	0
T1	310338	40	0	0
T2	516798	6662	0	0
T3	231750	70	0	0
T4	426979	46	0	0
T7	71842	4177	0	0
T8	305991	689	0	0
T9	50548	374	0	0
T10	1845	41	0	0
T11	659156	130	0	0
T12	2527	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	197204	0	0
GntImpliesValid_A	422207318	197204	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	197204	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2807738	0	0
ReadyAndValidImplyGrant_A	422207318	197204	0	0
ReqAndReadyImplyGrant_A	422207318	197204	0	0
ReqImpliesValid_A	422207318	501587	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	197204	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	197204	0	0
T1	310338	9	0	0
T2	516798	1203	0	0
T3	231750	7	0	0
T4	426979	17	0	0
T7	71842	786	0	0
T8	305991	163	0	0
T9	50548	89	0	0
T10	1845	13	0	0
T11	659156	24	0	0
T12	2527	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	197204	0	0
T1	310338	9	0	0
T2	516798	1203	0	0
T3	231750	7	0	0
T4	426979	17	0	0
T7	71842	786	0	0
T8	305991	163	0	0
T9	50548	89	0	0
T10	1845	13	0	0
T11	659156	24	0	0
T12	2527	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	197204	0	0
T1	310338	9	0	0
T2	516798	1203	0	0
T3	231750	7	0	0
T4	426979	17	0	0
T7	71842	786	0	0
T8	305991	163	0	0
T9	50548	89	0	0
T10	1845	13	0	0
T11	659156	24	0	0
T12	2527	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2807738	0	0
T1	310338	42	0	0
T2	516798	7904	0	0
T3	231750	37	0	0
T4	426979	3441	0	0
T7	71842	396	0	0
T8	305991	47997	0	0
T9	50548	724	0	0
T10	1845	13	0	0
T11	659156	6249	0	0
T12	2527	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	197204	0	0
T1	310338	9	0	0
T2	516798	1203	0	0
T3	231750	7	0	0
T4	426979	17	0	0
T7	71842	786	0	0
T8	305991	163	0	0
T9	50548	89	0	0
T10	1845	13	0	0
T11	659156	24	0	0
T12	2527	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	197204	0	0
T1	310338	9	0	0
T2	516798	1203	0	0
T3	231750	7	0	0
T4	426979	17	0	0
T7	71842	786	0	0
T8	305991	163	0	0
T9	50548	89	0	0
T10	1845	13	0	0
T11	659156	24	0	0
T12	2527	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	501587	0	0
T1	310338	19	0	0
T2	516798	3499	0	0
T3	231750	7	0	0
T4	426979	396	0	0
T7	71842	1178	0	0
T8	305991	2686	0	0
T9	50548	110	0	0
T10	1845	14	0	0
T11	659156	24	0	0
T12	2527	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	197204	0	0
T1	310338	9	0	0
T2	516798	1203	0	0
T3	231750	7	0	0
T4	426979	17	0	0
T7	71842	786	0	0
T8	305991	163	0	0
T9	50548	89	0	0
T10	1845	13	0	0
T11	659156	24	0	0
T12	2527	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	202649	0	0
GntImpliesValid_A	422207318	202649	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	202649	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2871804	0	0
ReadyAndValidImplyGrant_A	422207318	202649	0	0
ReqAndReadyImplyGrant_A	422207318	202649	0	0
ReqImpliesValid_A	422207318	521232	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	202649	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202649	0	0
T1	310338	13	0	0
T2	516798	1747	0	0
T3	231750	11	0	0
T4	426979	15	0	0
T7	71842	853	0	0
T8	305991	173	0	0
T9	50548	102	0	0
T10	1845	10	0	0
T11	659156	48	0	0
T12	2527	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202649	0	0
T1	310338	13	0	0
T2	516798	1747	0	0
T3	231750	11	0	0
T4	426979	15	0	0
T7	71842	853	0	0
T8	305991	173	0	0
T9	50548	102	0	0
T10	1845	10	0	0
T11	659156	48	0	0
T12	2527	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202649	0	0
T1	310338	13	0	0
T2	516798	1747	0	0
T3	231750	11	0	0
T4	426979	15	0	0
T7	71842	853	0	0
T8	305991	173	0	0
T9	50548	102	0	0
T10	1845	10	0	0
T11	659156	48	0	0
T12	2527	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2871804	0	0
T1	310338	61	0	0
T2	516798	11990	0	0
T3	231750	58	0	0
T4	426979	5276	0	0
T7	71842	547	0	0
T8	305991	59078	0	0
T9	50548	768	0	0
T10	1845	11	0	0
T11	659156	17065	0	0
T12	2527	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202649	0	0
T1	310338	13	0	0
T2	516798	1747	0	0
T3	231750	11	0	0
T4	426979	15	0	0
T7	71842	853	0	0
T8	305991	173	0	0
T9	50548	102	0	0
T10	1845	10	0	0
T11	659156	48	0	0
T12	2527	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202649	0	0
T1	310338	13	0	0
T2	516798	1747	0	0
T3	231750	11	0	0
T4	426979	15	0	0
T7	71842	853	0	0
T8	305991	173	0	0
T9	50548	102	0	0
T10	1845	10	0	0
T11	659156	48	0	0
T12	2527	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	521232	0	0
T1	310338	13	0	0
T2	516798	4643	0	0
T3	231750	11	0	0
T4	426979	15	0	0
T7	71842	1161	0	0
T8	305991	1083	0	0
T9	50548	120	0	0
T10	1845	10	0	0
T11	659156	423	0	0
T12	2527	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202649	0	0
T1	310338	13	0	0
T2	516798	1747	0	0
T3	231750	11	0	0
T4	426979	15	0	0
T7	71842	853	0	0
T8	305991	173	0	0
T9	50548	102	0	0
T10	1845	10	0	0
T11	659156	48	0	0
T12	2527	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	193632	0	0
GntImpliesValid_A	422207318	193632	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	193632	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	5294840	0	0
ReadyAndValidImplyGrant_A	422207318	193632	0	0
ReqAndReadyImplyGrant_A	422207318	193632	0	0
ReqImpliesValid_A	422207318	1011487	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	193632	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	193632	0	0
T1	310338	10	0	0
T2	516798	723	0	0
T3	231750	12	0	0
T4	426979	16	0	0
T7	71842	1655	0	0
T8	305991	168	0	0
T9	50548	106	0	0
T10	1845	7	0	0
T11	659156	37	0	0
T12	2527	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	193632	0	0
T1	310338	10	0	0
T2	516798	723	0	0
T3	231750	12	0	0
T4	426979	16	0	0
T7	71842	1655	0	0
T8	305991	168	0	0
T9	50548	106	0	0
T10	1845	7	0	0
T11	659156	37	0	0
T12	2527	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	193632	0	0
T1	310338	10	0	0
T2	516798	723	0	0
T3	231750	12	0	0
T4	426979	16	0	0
T7	71842	1655	0	0
T8	305991	168	0	0
T9	50548	106	0	0
T10	1845	7	0	0
T11	659156	37	0	0
T12	2527	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	5294840	0	0
T1	310338	251	0	0
T2	516798	11096	0	0
T3	231750	71	0	0
T4	426979	4558	0	0
T7	71842	2426	0	0
T8	305991	46350	0	0
T9	50548	3850	0	0
T10	1845	38	0	0
T11	659156	14174	0	0
T12	2527	55	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	193632	0	0
T1	310338	10	0	0
T2	516798	723	0	0
T3	231750	12	0	0
T4	426979	16	0	0
T7	71842	1655	0	0
T8	305991	168	0	0
T9	50548	106	0	0
T10	1845	7	0	0
T11	659156	37	0	0
T12	2527	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	193632	0	0
T1	310338	10	0	0
T2	516798	723	0	0
T3	231750	12	0	0
T4	426979	16	0	0
T7	71842	1655	0	0
T8	305991	168	0	0
T9	50548	106	0	0
T10	1845	7	0	0
T11	659156	37	0	0
T12	2527	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	1011487	0	0
T1	310338	10	0	0
T2	516798	1171	0	0
T3	231750	12	0	0
T4	426979	16	0	0
T7	71842	7326	0	0
T8	305991	1141	0	0
T9	50548	266	0	0
T10	1845	7	0	0
T11	659156	589	0	0
T12	2527	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	193632	0	0
T1	310338	10	0	0
T2	516798	723	0	0
T3	231750	12	0	0
T4	426979	16	0	0
T7	71842	1655	0	0
T8	305991	168	0	0
T9	50548	106	0	0
T10	1845	7	0	0
T11	659156	37	0	0
T12	2527	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	199572	0	0
GntImpliesValid_A	422207318	199572	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	199572	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	4981045	0	0
ReadyAndValidImplyGrant_A	422207318	199572	0	0
ReqAndReadyImplyGrant_A	422207318	199572	0	0
ReqImpliesValid_A	422207318	1227173	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	199572	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	199572	0	0
T1	310338	10	0	0
T2	516798	721	0	0
T3	231750	6	0	0
T4	426979	13	0	0
T7	71842	1356	0	0
T8	305991	171	0	0
T9	50548	96	0	0
T10	1845	8	0	0
T11	659156	33	0	0
T12	2527	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	199572	0	0
T1	310338	10	0	0
T2	516798	721	0	0
T3	231750	6	0	0
T4	426979	13	0	0
T7	71842	1356	0	0
T8	305991	171	0	0
T9	50548	96	0	0
T10	1845	8	0	0
T11	659156	33	0	0
T12	2527	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	199572	0	0
T1	310338	10	0	0
T2	516798	721	0	0
T3	231750	6	0	0
T4	426979	13	0	0
T7	71842	1356	0	0
T8	305991	171	0	0
T9	50548	96	0	0
T10	1845	8	0	0
T11	659156	33	0	0
T12	2527	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	4981045	0	0
T1	310338	85	0	0
T2	516798	6678	0	0
T3	231750	62	0	0
T4	426979	4341	0	0
T7	71842	3144	0	0
T8	305991	50438	0	0
T9	50548	1164	0	0
T10	1845	83	0	0
T11	659156	9326	0	0
T12	2527	115	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	199572	0	0
T1	310338	10	0	0
T2	516798	721	0	0
T3	231750	6	0	0
T4	426979	13	0	0
T7	71842	1356	0	0
T8	305991	171	0	0
T9	50548	96	0	0
T10	1845	8	0	0
T11	659156	33	0	0
T12	2527	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	199572	0	0
T1	310338	10	0	0
T2	516798	721	0	0
T3	231750	6	0	0
T4	426979	13	0	0
T7	71842	1356	0	0
T8	305991	171	0	0
T9	50548	96	0	0
T10	1845	8	0	0
T11	659156	33	0	0
T12	2527	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	1227173	0	0
T1	310338	10	0	0
T2	516798	878	0	0
T3	231750	6	0	0
T4	426979	354	0	0
T7	71842	11244	0	0
T8	305991	1552	0	0
T9	50548	151	0	0
T10	1845	18	0	0
T11	659156	33	0	0
T12	2527	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	199572	0	0
T1	310338	10	0	0
T2	516798	721	0	0
T3	231750	6	0	0
T4	426979	13	0	0
T7	71842	1356	0	0
T8	305991	171	0	0
T9	50548	96	0	0
T10	1845	8	0	0
T11	659156	33	0	0
T12	2527	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	214736	0	0
GntImpliesValid_A	422207318	214736	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	214736	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	5418639	0	0
ReadyAndValidImplyGrant_A	422207318	214736	0	0
ReqAndReadyImplyGrant_A	422207318	214736	0	0
ReqImpliesValid_A	422207318	1220900	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	214736	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	214736	0	0
T1	310338	9	0	0
T2	516798	770	0	0
T3	231750	19	0	0
T4	426979	18	0	0
T7	71842	862	0	0
T8	305991	186	0	0
T9	50548	108	0	0
T10	1845	12	0	0
T11	659156	39	0	0
T12	2527	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	214736	0	0
T1	310338	9	0	0
T2	516798	770	0	0
T3	231750	19	0	0
T4	426979	18	0	0
T7	71842	862	0	0
T8	305991	186	0	0
T9	50548	108	0	0
T10	1845	12	0	0
T11	659156	39	0	0
T12	2527	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	214736	0	0
T1	310338	9	0	0
T2	516798	770	0	0
T3	231750	19	0	0
T4	426979	18	0	0
T7	71842	862	0	0
T8	305991	186	0	0
T9	50548	108	0	0
T10	1845	12	0	0
T11	659156	39	0	0
T12	2527	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	5418639	0	0
T1	310338	192	0	0
T2	516798	7300	0	0
T3	231750	118	0	0
T4	426979	12700	0	0
T7	71842	2498	0	0
T8	305991	65083	0	0
T9	50548	1189	0	0
T10	1845	50	0	0
T11	659156	10123	0	0
T12	2527	255	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	214736	0	0
T1	310338	9	0	0
T2	516798	770	0	0
T3	231750	19	0	0
T4	426979	18	0	0
T7	71842	862	0	0
T8	305991	186	0	0
T9	50548	108	0	0
T10	1845	12	0	0
T11	659156	39	0	0
T12	2527	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	214736	0	0
T1	310338	9	0	0
T2	516798	770	0	0
T3	231750	19	0	0
T4	426979	18	0	0
T7	71842	862	0	0
T8	305991	186	0	0
T9	50548	108	0	0
T10	1845	12	0	0
T11	659156	39	0	0
T12	2527	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	1220900	0	0
T1	310338	108	0	0
T2	516798	1097	0	0
T3	231750	28	0	0
T4	426979	1222	0	0
T7	71842	2714	0	0
T8	305991	5192	0	0
T9	50548	221	0	0
T10	1845	22	0	0
T11	659156	39	0	0
T12	2527	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	214736	0	0
T1	310338	9	0	0
T2	516798	770	0	0
T3	231750	19	0	0
T4	426979	18	0	0
T7	71842	862	0	0
T8	305991	186	0	0
T9	50548	108	0	0
T10	1845	12	0	0
T11	659156	39	0	0
T12	2527	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	211211	0	0
GntImpliesValid_A	422207318	211211	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	211211	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	5246136	0	0
ReadyAndValidImplyGrant_A	422207318	211211	0	0
ReqAndReadyImplyGrant_A	422207318	211211	0	0
ReqImpliesValid_A	422207318	1277609	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	211211	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211211	0	0
T1	310338	7	0	0
T2	516798	1673	0	0
T3	231750	12	0	0
T4	426979	8	0	0
T7	71842	778	0	0
T8	305991	181	0	0
T9	50548	88	0	0
T10	1845	15	0	0
T11	659156	39	0	0
T12	2527	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211211	0	0
T1	310338	7	0	0
T2	516798	1673	0	0
T3	231750	12	0	0
T4	426979	8	0	0
T7	71842	778	0	0
T8	305991	181	0	0
T9	50548	88	0	0
T10	1845	15	0	0
T11	659156	39	0	0
T12	2527	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211211	0	0
T1	310338	7	0	0
T2	516798	1673	0	0
T3	231750	12	0	0
T4	426979	8	0	0
T7	71842	778	0	0
T8	305991	181	0	0
T9	50548	88	0	0
T10	1845	15	0	0
T11	659156	39	0	0
T12	2527	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	5246136	0	0
T1	310338	59	0	0
T2	516798	11030	0	0
T3	231750	88	0	0
T4	426979	4682	0	0
T7	71842	1611	0	0
T8	305991	34247	0	0
T9	50548	1535	0	0
T10	1845	74	0	0
T11	659156	50835	0	0
T12	2527	57	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211211	0	0
T1	310338	7	0	0
T2	516798	1673	0	0
T3	231750	12	0	0
T4	426979	8	0	0
T7	71842	778	0	0
T8	305991	181	0	0
T9	50548	88	0	0
T10	1845	15	0	0
T11	659156	39	0	0
T12	2527	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211211	0	0
T1	310338	7	0	0
T2	516798	1673	0	0
T3	231750	12	0	0
T4	426979	8	0	0
T7	71842	778	0	0
T8	305991	181	0	0
T9	50548	88	0	0
T10	1845	15	0	0
T11	659156	39	0	0
T12	2527	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	1277609	0	0
T1	310338	7	0	0
T2	516798	6295	0	0
T3	231750	12	0	0
T4	426979	8	0	0
T7	71842	3120	0	0
T8	305991	924	0	0
T9	50548	179	0	0
T10	1845	60	0	0
T11	659156	7906	0	0
T12	2527	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211211	0	0
T1	310338	7	0	0
T2	516798	1673	0	0
T3	231750	12	0	0
T4	426979	8	0	0
T7	71842	778	0	0
T8	305991	181	0	0
T9	50548	88	0	0
T10	1845	15	0	0
T11	659156	39	0	0
T12	2527	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	212664	0	0
GntImpliesValid_A	422207318	212664	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	212664	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2925701	0	0
ReadyAndValidImplyGrant_A	422207318	212664	0	0
ReqAndReadyImplyGrant_A	422207318	212664	0	0
ReqImpliesValid_A	422207318	558079	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	212664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	212664	0	0
T1	310338	15	0	0
T2	516798	1306	0	0
T3	231750	13	0	0
T4	426979	19	0	0
T7	71842	346	0	0
T8	305991	173	0	0
T9	50548	85	0	0
T10	1845	10	0	0
T11	659156	36	0	0
T12	2527	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	212664	0	0
T1	310338	15	0	0
T2	516798	1306	0	0
T3	231750	13	0	0
T4	426979	19	0	0
T7	71842	346	0	0
T8	305991	173	0	0
T9	50548	85	0	0
T10	1845	10	0	0
T11	659156	36	0	0
T12	2527	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	212664	0	0
T1	310338	15	0	0
T2	516798	1306	0	0
T3	231750	13	0	0
T4	426979	19	0	0
T7	71842	346	0	0
T8	305991	173	0	0
T9	50548	85	0	0
T10	1845	10	0	0
T11	659156	36	0	0
T12	2527	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2925701	0	0
T1	310338	58	0	0
T2	516798	8881	0	0
T3	231750	55	0	0
T4	426979	4562	0	0
T7	71842	345	0	0
T8	305991	59922	0	0
T9	50548	635	0	0
T10	1845	11	0	0
T11	659156	9936	0	0
T12	2527	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	212664	0	0
T1	310338	15	0	0
T2	516798	1306	0	0
T3	231750	13	0	0
T4	426979	19	0	0
T7	71842	346	0	0
T8	305991	173	0	0
T9	50548	85	0	0
T10	1845	10	0	0
T11	659156	36	0	0
T12	2527	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	212664	0	0
T1	310338	15	0	0
T2	516798	1306	0	0
T3	231750	13	0	0
T4	426979	19	0	0
T7	71842	346	0	0
T8	305991	173	0	0
T9	50548	85	0	0
T10	1845	10	0	0
T11	659156	36	0	0
T12	2527	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	558079	0	0
T1	310338	22	0	0
T2	516798	1912	0	0
T3	231750	16	0	0
T4	426979	634	0	0
T7	71842	349	0	0
T8	305991	2468	0	0
T9	50548	93	0	0
T10	1845	10	0	0
T11	659156	82	0	0
T12	2527	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	212664	0	0
T1	310338	15	0	0
T2	516798	1306	0	0
T3	231750	13	0	0
T4	426979	19	0	0
T7	71842	346	0	0
T8	305991	173	0	0
T9	50548	85	0	0
T10	1845	10	0	0
T11	659156	36	0	0
T12	2527	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	211976	0	0
GntImpliesValid_A	422207318	211976	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	211976	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2878723	0	0
ReadyAndValidImplyGrant_A	422207318	211976	0	0
ReqAndReadyImplyGrant_A	422207318	211976	0	0
ReqImpliesValid_A	422207318	557532	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	211976	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211976	0	0
T1	310338	12	0	0
T2	516798	1726	0	0
T3	231750	11	0	0
T4	426979	19	0	0
T7	71842	1295	0	0
T8	305991	173	0	0
T9	50548	88	0	0
T10	1845	9	0	0
T11	659156	50	0	0
T12	2527	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211976	0	0
T1	310338	12	0	0
T2	516798	1726	0	0
T3	231750	11	0	0
T4	426979	19	0	0
T7	71842	1295	0	0
T8	305991	173	0	0
T9	50548	88	0	0
T10	1845	9	0	0
T11	659156	50	0	0
T12	2527	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211976	0	0
T1	310338	12	0	0
T2	516798	1726	0	0
T3	231750	11	0	0
T4	426979	19	0	0
T7	71842	1295	0	0
T8	305991	173	0	0
T9	50548	88	0	0
T10	1845	9	0	0
T11	659156	50	0	0
T12	2527	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2878723	0	0
T1	310338	53	0	0
T2	516798	12148	0	0
T3	231750	57	0	0
T4	426979	4387	0	0
T7	71842	758	0	0
T8	305991	59191	0	0
T9	50548	694	0	0
T10	1845	10	0	0
T11	659156	16622	0	0
T12	2527	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211976	0	0
T1	310338	12	0	0
T2	516798	1726	0	0
T3	231750	11	0	0
T4	426979	19	0	0
T7	71842	1295	0	0
T8	305991	173	0	0
T9	50548	88	0	0
T10	1845	9	0	0
T11	659156	50	0	0
T12	2527	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211976	0	0
T1	310338	12	0	0
T2	516798	1726	0	0
T3	231750	11	0	0
T4	426979	19	0	0
T7	71842	1295	0	0
T8	305991	173	0	0
T9	50548	88	0	0
T10	1845	9	0	0
T11	659156	50	0	0
T12	2527	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	557532	0	0
T1	310338	12	0	0
T2	516798	3642	0	0
T3	231750	13	0	0
T4	426979	19	0	0
T7	71842	1834	0	0
T8	305991	1781	0	0
T9	50548	104	0	0
T10	1845	9	0	0
T11	659156	231	0	0
T12	2527	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211976	0	0
T1	310338	12	0	0
T2	516798	1726	0	0
T3	231750	11	0	0
T4	426979	19	0	0
T7	71842	1295	0	0
T8	305991	173	0	0
T9	50548	88	0	0
T10	1845	9	0	0
T11	659156	50	0	0
T12	2527	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	209536	0	0
GntImpliesValid_A	422207318	209536	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	209536	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2827925	0	0
ReadyAndValidImplyGrant_A	422207318	209536	0	0
ReqAndReadyImplyGrant_A	422207318	209536	0	0
ReqImpliesValid_A	422207318	554068	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	209536	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209536	0	0
T1	310338	17	0	0
T2	516798	2093	0	0
T3	231750	20	0	0
T4	426979	7	0	0
T7	71842	309	0	0
T8	305991	171	0	0
T9	50548	108	0	0
T10	1845	10	0	0
T11	659156	38	0	0
T12	2527	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209536	0	0
T1	310338	17	0	0
T2	516798	2093	0	0
T3	231750	20	0	0
T4	426979	7	0	0
T7	71842	309	0	0
T8	305991	171	0	0
T9	50548	108	0	0
T10	1845	10	0	0
T11	659156	38	0	0
T12	2527	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209536	0	0
T1	310338	17	0	0
T2	516798	2093	0	0
T3	231750	20	0	0
T4	426979	7	0	0
T7	71842	309	0	0
T8	305991	171	0	0
T9	50548	108	0	0
T10	1845	10	0	0
T11	659156	38	0	0
T12	2527	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2827925	0	0
T1	310338	86	0	0
T2	516798	12962	0	0
T3	231750	75	0	0
T4	426979	1885	0	0
T7	71842	307	0	0
T8	305991	56003	0	0
T9	50548	730	0	0
T10	1845	11	0	0
T11	659156	12876	0	0
T12	2527	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209536	0	0
T1	310338	17	0	0
T2	516798	2093	0	0
T3	231750	20	0	0
T4	426979	7	0	0
T7	71842	309	0	0
T8	305991	171	0	0
T9	50548	108	0	0
T10	1845	10	0	0
T11	659156	38	0	0
T12	2527	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209536	0	0
T1	310338	17	0	0
T2	516798	2093	0	0
T3	231750	20	0	0
T4	426979	7	0	0
T7	71842	309	0	0
T8	305991	171	0	0
T9	50548	108	0	0
T10	1845	10	0	0
T11	659156	38	0	0
T12	2527	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	554068	0	0
T1	310338	19	0	0
T2	516798	7462	0	0
T3	231750	24	0	0
T4	426979	7	0	0
T7	71842	313	0	0
T8	305991	836	0	0
T9	50548	120	0	0
T10	1845	10	0	0
T11	659156	836	0	0
T12	2527	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209536	0	0
T1	310338	17	0	0
T2	516798	2093	0	0
T3	231750	20	0	0
T4	426979	7	0	0
T7	71842	309	0	0
T8	305991	171	0	0
T9	50548	108	0	0
T10	1845	10	0	0
T11	659156	38	0	0
T12	2527	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	202174	0	0
GntImpliesValid_A	422207318	202174	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	202174	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2805124	0	0
ReadyAndValidImplyGrant_A	422207318	202174	0	0
ReqAndReadyImplyGrant_A	422207318	202174	0	0
ReqImpliesValid_A	422207318	539617	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	202174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202174	0	0
T1	310338	9	0	0
T2	516798	1240	0	0
T3	231750	13	0	0
T4	426979	14	0	0
T7	71842	1781	0	0
T8	305991	184	0	0
T9	50548	109	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202174	0	0
T1	310338	9	0	0
T2	516798	1240	0	0
T3	231750	13	0	0
T4	426979	14	0	0
T7	71842	1781	0	0
T8	305991	184	0	0
T9	50548	109	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202174	0	0
T1	310338	9	0	0
T2	516798	1240	0	0
T3	231750	13	0	0
T4	426979	14	0	0
T7	71842	1781	0	0
T8	305991	184	0	0
T9	50548	109	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2805124	0	0
T1	310338	41	0	0
T2	516798	9348	0	0
T3	231750	56	0	0
T4	426979	3782	0	0
T7	71842	831	0	0
T8	305991	60631	0	0
T9	50548	810	0	0
T10	1845	11	0	0
T11	659156	19225	0	0
T12	2527	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202174	0	0
T1	310338	9	0	0
T2	516798	1240	0	0
T3	231750	13	0	0
T4	426979	14	0	0
T7	71842	1781	0	0
T8	305991	184	0	0
T9	50548	109	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202174	0	0
T1	310338	9	0	0
T2	516798	1240	0	0
T3	231750	13	0	0
T4	426979	14	0	0
T7	71842	1781	0	0
T8	305991	184	0	0
T9	50548	109	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	539617	0	0
T1	310338	9	0	0
T2	516798	1883	0	0
T3	231750	22	0	0
T4	426979	208	0	0
T7	71842	2733	0	0
T8	305991	3749	0	0
T9	50548	168	0	0
T10	1845	14	0	0
T11	659156	739	0	0
T12	2527	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	202174	0	0
T1	310338	9	0	0
T2	516798	1240	0	0
T3	231750	13	0	0
T4	426979	14	0	0
T7	71842	1781	0	0
T8	305991	184	0	0
T9	50548	109	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	208016	0	0
GntImpliesValid_A	422207318	208016	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	208016	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2783551	0	0
ReadyAndValidImplyGrant_A	422207318	208016	0	0
ReqAndReadyImplyGrant_A	422207318	208016	0	0
ReqImpliesValid_A	422207318	536566	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	208016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208016	0	0
T1	310338	16	0	0
T2	516798	781	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	834	0	0
T8	305991	171	0	0
T9	50548	85	0	0
T10	1845	7	0	0
T11	659156	55	0	0
T12	2527	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208016	0	0
T1	310338	16	0	0
T2	516798	781	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	834	0	0
T8	305991	171	0	0
T9	50548	85	0	0
T10	1845	7	0	0
T11	659156	55	0	0
T12	2527	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208016	0	0
T1	310338	16	0	0
T2	516798	781	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	834	0	0
T8	305991	171	0	0
T9	50548	85	0	0
T10	1845	7	0	0
T11	659156	55	0	0
T12	2527	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2783551	0	0
T1	310338	57	0	0
T2	516798	6095	0	0
T3	231750	53	0	0
T4	426979	4676	0	0
T7	71842	330	0	0
T8	305991	56476	0	0
T9	50548	628	0	0
T10	1845	8	0	0
T11	659156	15142	0	0
T12	2527	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208016	0	0
T1	310338	16	0	0
T2	516798	781	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	834	0	0
T8	305991	171	0	0
T9	50548	85	0	0
T10	1845	7	0	0
T11	659156	55	0	0
T12	2527	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208016	0	0
T1	310338	16	0	0
T2	516798	781	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	834	0	0
T8	305991	171	0	0
T9	50548	85	0	0
T10	1845	7	0	0
T11	659156	55	0	0
T12	2527	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	536566	0	0
T1	310338	16	0	0
T2	516798	882	0	0
T3	231750	15	0	0
T4	426979	18	0	0
T7	71842	1340	0	0
T8	305991	2655	0	0
T9	50548	102	0	0
T10	1845	7	0	0
T11	659156	1266	0	0
T12	2527	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208016	0	0
T1	310338	16	0	0
T2	516798	781	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	834	0	0
T8	305991	171	0	0
T9	50548	85	0	0
T10	1845	7	0	0
T11	659156	55	0	0
T12	2527	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	216105	0	0
GntImpliesValid_A	422207318	216105	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	216105	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2807063	0	0
ReadyAndValidImplyGrant_A	422207318	216105	0	0
ReqAndReadyImplyGrant_A	422207318	216105	0	0
ReqImpliesValid_A	422207318	575462	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	216105	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	216105	0	0
T1	310338	5	0	0
T2	516798	1194	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	798	0	0
T8	305991	177	0	0
T9	50548	118	0	0
T10	1845	6	0	0
T11	659156	34	0	0
T12	2527	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	216105	0	0
T1	310338	5	0	0
T2	516798	1194	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	798	0	0
T8	305991	177	0	0
T9	50548	118	0	0
T10	1845	6	0	0
T11	659156	34	0	0
T12	2527	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	216105	0	0
T1	310338	5	0	0
T2	516798	1194	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	798	0	0
T8	305991	177	0	0
T9	50548	118	0	0
T10	1845	6	0	0
T11	659156	34	0	0
T12	2527	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2807063	0	0
T1	310338	38	0	0
T2	516798	8466	0	0
T3	231750	65	0	0
T4	426979	6211	0	0
T7	71842	561	0	0
T8	305991	54123	0	0
T9	50548	880	0	0
T10	1845	7	0	0
T11	659156	10379	0	0
T12	2527	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	216105	0	0
T1	310338	5	0	0
T2	516798	1194	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	798	0	0
T8	305991	177	0	0
T9	50548	118	0	0
T10	1845	6	0	0
T11	659156	34	0	0
T12	2527	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	216105	0	0
T1	310338	5	0	0
T2	516798	1194	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	798	0	0
T8	305991	177	0	0
T9	50548	118	0	0
T10	1845	6	0	0
T11	659156	34	0	0
T12	2527	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	575462	0	0
T1	310338	5	0	0
T2	516798	1868	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	1037	0	0
T8	305991	1868	0	0
T9	50548	152	0	0
T10	1845	6	0	0
T11	659156	1299	0	0
T12	2527	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	216105	0	0
T1	310338	5	0	0
T2	516798	1194	0	0
T3	231750	14	0	0
T4	426979	18	0	0
T7	71842	798	0	0
T8	305991	177	0	0
T9	50548	118	0	0
T10	1845	6	0	0
T11	659156	34	0	0
T12	2527	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	209593	0	0
GntImpliesValid_A	422207318	209593	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	209593	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2885926	0	0
ReadyAndValidImplyGrant_A	422207318	209593	0	0
ReqAndReadyImplyGrant_A	422207318	209593	0	0
ReqImpliesValid_A	422207318	573001	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	209593	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209593	0	0
T1	310338	13	0	0
T2	516798	721	0	0
T3	231750	8	0	0
T4	426979	12	0	0
T7	71842	318	0	0
T8	305991	175	0	0
T9	50548	106	0	0
T10	1845	13	0	0
T11	659156	42	0	0
T12	2527	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209593	0	0
T1	310338	13	0	0
T2	516798	721	0	0
T3	231750	8	0	0
T4	426979	12	0	0
T7	71842	318	0	0
T8	305991	175	0	0
T9	50548	106	0	0
T10	1845	13	0	0
T11	659156	42	0	0
T12	2527	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209593	0	0
T1	310338	13	0	0
T2	516798	721	0	0
T3	231750	8	0	0
T4	426979	12	0	0
T7	71842	318	0	0
T8	305991	175	0	0
T9	50548	106	0	0
T10	1845	13	0	0
T11	659156	42	0	0
T12	2527	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2885926	0	0
T1	310338	38	0	0
T2	516798	5651	0	0
T3	231750	32	0	0
T4	426979	4004	0	0
T7	71842	313	0	0
T8	305991	57279	0	0
T9	50548	846	0	0
T10	1845	12	0	0
T11	659156	13960	0	0
T12	2527	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209593	0	0
T1	310338	13	0	0
T2	516798	721	0	0
T3	231750	8	0	0
T4	426979	12	0	0
T7	71842	318	0	0
T8	305991	175	0	0
T9	50548	106	0	0
T10	1845	13	0	0
T11	659156	42	0	0
T12	2527	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209593	0	0
T1	310338	13	0	0
T2	516798	721	0	0
T3	231750	8	0	0
T4	426979	12	0	0
T7	71842	318	0	0
T8	305991	175	0	0
T9	50548	106	0	0
T10	1845	13	0	0
T11	659156	42	0	0
T12	2527	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	573001	0	0
T1	310338	22	0	0
T2	516798	783	0	0
T3	231750	8	0	0
T4	426979	12	0	0
T7	71842	325	0	0
T8	305991	1213	0	0
T9	50548	118	0	0
T10	1845	15	0	0
T11	659156	173	0	0
T12	2527	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	209593	0	0
T1	310338	13	0	0
T2	516798	721	0	0
T3	231750	8	0	0
T4	426979	12	0	0
T7	71842	318	0	0
T8	305991	175	0	0
T9	50548	106	0	0
T10	1845	13	0	0
T11	659156	42	0	0
T12	2527	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	208908	0	0
GntImpliesValid_A	422207318	208908	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	208908	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2831983	0	0
ReadyAndValidImplyGrant_A	422207318	208908	0	0
ReqAndReadyImplyGrant_A	422207318	208908	0	0
ReqImpliesValid_A	422207318	563161	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	208908	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208908	0	0
T1	310338	15	0	0
T2	516798	780	0	0
T3	231750	15	0	0
T4	426979	8	0	0
T7	71842	328	0	0
T8	305991	194	0	0
T9	50548	89	0	0
T10	1845	5	0	0
T11	659156	34	0	0
T12	2527	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208908	0	0
T1	310338	15	0	0
T2	516798	780	0	0
T3	231750	15	0	0
T4	426979	8	0	0
T7	71842	328	0	0
T8	305991	194	0	0
T9	50548	89	0	0
T10	1845	5	0	0
T11	659156	34	0	0
T12	2527	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208908	0	0
T1	310338	15	0	0
T2	516798	780	0	0
T3	231750	15	0	0
T4	426979	8	0	0
T7	71842	328	0	0
T8	305991	194	0	0
T9	50548	89	0	0
T10	1845	5	0	0
T11	659156	34	0	0
T12	2527	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2831983	0	0
T1	310338	67	0	0
T2	516798	5781	0	0
T3	231750	77	0	0
T4	426979	3270	0	0
T7	71842	325	0	0
T8	305991	64048	0	0
T9	50548	615	0	0
T10	1845	6	0	0
T11	659156	9874	0	0
T12	2527	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208908	0	0
T1	310338	15	0	0
T2	516798	780	0	0
T3	231750	15	0	0
T4	426979	8	0	0
T7	71842	328	0	0
T8	305991	194	0	0
T9	50548	89	0	0
T10	1845	5	0	0
T11	659156	34	0	0
T12	2527	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208908	0	0
T1	310338	15	0	0
T2	516798	780	0	0
T3	231750	15	0	0
T4	426979	8	0	0
T7	71842	328	0	0
T8	305991	194	0	0
T9	50548	89	0	0
T10	1845	5	0	0
T11	659156	34	0	0
T12	2527	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	563161	0	0
T1	310338	26	0	0
T2	516798	917	0	0
T3	231750	24	0	0
T4	426979	8	0	0
T7	71842	333	0	0
T8	305991	3472	0	0
T9	50548	91	0	0
T10	1845	5	0	0
T11	659156	748	0	0
T12	2527	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	208908	0	0
T1	310338	15	0	0
T2	516798	780	0	0
T3	231750	15	0	0
T4	426979	8	0	0
T7	71842	328	0	0
T8	305991	194	0	0
T9	50548	89	0	0
T10	1845	5	0	0
T11	659156	34	0	0
T12	2527	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	219508	0	0
GntImpliesValid_A	422207318	219508	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	219508	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2828987	0	0
ReadyAndValidImplyGrant_A	422207318	219508	0	0
ReqAndReadyImplyGrant_A	422207318	219508	0	0
ReqImpliesValid_A	422207318	545089	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	219508	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	219508	0	0
T1	310338	13	0	0
T2	516798	2568	0	0
T3	231750	9	0	0
T4	426979	12	0	0
T7	71842	403	0	0
T8	305991	170	0	0
T9	50548	178	0	0
T10	1845	11	0	0
T11	659156	44	0	0
T12	2527	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	219508	0	0
T1	310338	13	0	0
T2	516798	2568	0	0
T3	231750	9	0	0
T4	426979	12	0	0
T7	71842	403	0	0
T8	305991	170	0	0
T9	50548	178	0	0
T10	1845	11	0	0
T11	659156	44	0	0
T12	2527	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	219508	0	0
T1	310338	13	0	0
T2	516798	2568	0	0
T3	231750	9	0	0
T4	426979	12	0	0
T7	71842	403	0	0
T8	305991	170	0	0
T9	50548	178	0	0
T10	1845	11	0	0
T11	659156	44	0	0
T12	2527	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2828987	0	0
T1	310338	54	0	0
T2	516798	14109	0	0
T3	231750	33	0	0
T4	426979	5551	0	0
T7	71842	394	0	0
T8	305991	54355	0	0
T9	50548	1383	0	0
T10	1845	12	0	0
T11	659156	15596	0	0
T12	2527	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	219508	0	0
T1	310338	13	0	0
T2	516798	2568	0	0
T3	231750	9	0	0
T4	426979	12	0	0
T7	71842	403	0	0
T8	305991	170	0	0
T9	50548	178	0	0
T10	1845	11	0	0
T11	659156	44	0	0
T12	2527	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	219508	0	0
T1	310338	13	0	0
T2	516798	2568	0	0
T3	231750	9	0	0
T4	426979	12	0	0
T7	71842	403	0	0
T8	305991	170	0	0
T9	50548	178	0	0
T10	1845	11	0	0
T11	659156	44	0	0
T12	2527	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	545089	0	0
T1	310338	13	0	0
T2	516798	5623	0	0
T3	231750	9	0	0
T4	426979	25	0	0
T7	71842	414	0	0
T8	305991	2172	0	0
T9	50548	233	0	0
T10	1845	11	0	0
T11	659156	485	0	0
T12	2527	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	219508	0	0
T1	310338	13	0	0
T2	516798	2568	0	0
T3	231750	9	0	0
T4	426979	12	0	0
T7	71842	403	0	0
T8	305991	170	0	0
T9	50548	178	0	0
T10	1845	11	0	0
T11	659156	44	0	0
T12	2527	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	198502	0	0
GntImpliesValid_A	422207318	198502	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	198502	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2822195	0	0
ReadyAndValidImplyGrant_A	422207318	198502	0	0
ReqAndReadyImplyGrant_A	422207318	198502	0	0
ReqImpliesValid_A	422207318	513072	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	198502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	198502	0	0
T1	310338	14	0	0
T2	516798	776	0	0
T3	231750	11	0	0
T4	426979	22	0	0
T7	71842	343	0	0
T8	305991	193	0	0
T9	50548	85	0	0
T10	1845	12	0	0
T11	659156	42	0	0
T12	2527	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	198502	0	0
T1	310338	14	0	0
T2	516798	776	0	0
T3	231750	11	0	0
T4	426979	22	0	0
T7	71842	343	0	0
T8	305991	193	0	0
T9	50548	85	0	0
T10	1845	12	0	0
T11	659156	42	0	0
T12	2527	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	198502	0	0
T1	310338	14	0	0
T2	516798	776	0	0
T3	231750	11	0	0
T4	426979	22	0	0
T7	71842	343	0	0
T8	305991	193	0	0
T9	50548	85	0	0
T10	1845	12	0	0
T11	659156	42	0	0
T12	2527	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2822195	0	0
T1	310338	68	0	0
T2	516798	5993	0	0
T3	231750	62	0	0
T4	426979	4210	0	0
T7	71842	338	0	0
T8	305991	62504	0	0
T9	50548	646	0	0
T10	1845	13	0	0
T11	659156	12213	0	0
T12	2527	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	198502	0	0
T1	310338	14	0	0
T2	516798	776	0	0
T3	231750	11	0	0
T4	426979	22	0	0
T7	71842	343	0	0
T8	305991	193	0	0
T9	50548	85	0	0
T10	1845	12	0	0
T11	659156	42	0	0
T12	2527	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	198502	0	0
T1	310338	14	0	0
T2	516798	776	0	0
T3	231750	11	0	0
T4	426979	22	0	0
T7	71842	343	0	0
T8	305991	193	0	0
T9	50548	85	0	0
T10	1845	12	0	0
T11	659156	42	0	0
T12	2527	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	513072	0	0
T1	310338	14	0	0
T2	516798	948	0	0
T3	231750	11	0	0
T4	426979	1368	0	0
T7	71842	350	0	0
T8	305991	3558	0	0
T9	50548	109	0	0
T10	1845	12	0	0
T11	659156	42	0	0
T12	2527	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	198502	0	0
T1	310338	14	0	0
T2	516798	776	0	0
T3	231750	11	0	0
T4	426979	22	0	0
T7	71842	343	0	0
T8	305991	193	0	0
T9	50548	85	0	0
T10	1845	12	0	0
T11	659156	42	0	0
T12	2527	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	204648	0	0
GntImpliesValid_A	422207318	204648	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	204648	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2802575	0	0
ReadyAndValidImplyGrant_A	422207318	204648	0	0
ReqAndReadyImplyGrant_A	422207318	204648	0	0
ReqImpliesValid_A	422207318	502545	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	204648	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	204648	0	0
T1	310338	12	0	0
T2	516798	1344	0	0
T3	231750	10	0	0
T4	426979	13	0	0
T7	71842	1329	0	0
T8	305991	170	0	0
T9	50548	95	0	0
T10	1845	21	0	0
T11	659156	45	0	0
T12	2527	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	204648	0	0
T1	310338	12	0	0
T2	516798	1344	0	0
T3	231750	10	0	0
T4	426979	13	0	0
T7	71842	1329	0	0
T8	305991	170	0	0
T9	50548	95	0	0
T10	1845	21	0	0
T11	659156	45	0	0
T12	2527	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	204648	0	0
T1	310338	12	0	0
T2	516798	1344	0	0
T3	231750	10	0	0
T4	426979	13	0	0
T7	71842	1329	0	0
T8	305991	170	0	0
T9	50548	95	0	0
T10	1845	21	0	0
T11	659156	45	0	0
T12	2527	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2802575	0	0
T1	310338	63	0	0
T2	516798	6988	0	0
T3	231750	27	0	0
T4	426979	6862	0	0
T7	71842	354	0	0
T8	305991	52622	0	0
T9	50548	657	0	0
T10	1845	21	0	0
T11	659156	13511	0	0
T12	2527	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	204648	0	0
T1	310338	12	0	0
T2	516798	1344	0	0
T3	231750	10	0	0
T4	426979	13	0	0
T7	71842	1329	0	0
T8	305991	170	0	0
T9	50548	95	0	0
T10	1845	21	0	0
T11	659156	45	0	0
T12	2527	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	204648	0	0
T1	310338	12	0	0
T2	516798	1344	0	0
T3	231750	10	0	0
T4	426979	13	0	0
T7	71842	1329	0	0
T8	305991	170	0	0
T9	50548	95	0	0
T10	1845	21	0	0
T11	659156	45	0	0
T12	2527	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	502545	0	0
T1	310338	20	0	0
T2	516798	3278	0	0
T3	231750	15	0	0
T4	426979	13	0	0
T7	71842	2306	0	0
T8	305991	1602	0	0
T9	50548	132	0	0
T10	1845	22	0	0
T11	659156	1660	0	0
T12	2527	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	204648	0	0
T1	310338	12	0	0
T2	516798	1344	0	0
T3	231750	10	0	0
T4	426979	13	0	0
T7	71842	1329	0	0
T8	305991	170	0	0
T9	50548	95	0	0
T10	1845	21	0	0
T11	659156	45	0	0
T12	2527	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	203149	0	0
GntImpliesValid_A	422207318	203149	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	203149	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2784099	0	0
ReadyAndValidImplyGrant_A	422207318	203149	0	0
ReqAndReadyImplyGrant_A	422207318	203149	0	0
ReqImpliesValid_A	422207318	526442	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	203149	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	203149	0	0
T1	310338	11	0	0
T2	516798	1708	0	0
T3	231750	14	0	0
T4	426979	16	0	0
T7	71842	343	0	0
T8	305991	156	0	0
T9	50548	93	0	0
T10	1845	14	0	0
T11	659156	35	0	0
T12	2527	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	203149	0	0
T1	310338	11	0	0
T2	516798	1708	0	0
T3	231750	14	0	0
T4	426979	16	0	0
T7	71842	343	0	0
T8	305991	156	0	0
T9	50548	93	0	0
T10	1845	14	0	0
T11	659156	35	0	0
T12	2527	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	203149	0	0
T1	310338	11	0	0
T2	516798	1708	0	0
T3	231750	14	0	0
T4	426979	16	0	0
T7	71842	343	0	0
T8	305991	156	0	0
T9	50548	93	0	0
T10	1845	14	0	0
T11	659156	35	0	0
T12	2527	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2784099	0	0
T1	310338	45	0	0
T2	516798	9652	0	0
T3	231750	46	0	0
T4	426979	3625	0	0
T7	71842	337	0	0
T8	305991	48530	0	0
T9	50548	781	0	0
T10	1845	15	0	0
T11	659156	8900	0	0
T12	2527	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	203149	0	0
T1	310338	11	0	0
T2	516798	1708	0	0
T3	231750	14	0	0
T4	426979	16	0	0
T7	71842	343	0	0
T8	305991	156	0	0
T9	50548	93	0	0
T10	1845	14	0	0
T11	659156	35	0	0
T12	2527	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	203149	0	0
T1	310338	11	0	0
T2	516798	1708	0	0
T3	231750	14	0	0
T4	426979	16	0	0
T7	71842	343	0	0
T8	305991	156	0	0
T9	50548	93	0	0
T10	1845	14	0	0
T11	659156	35	0	0
T12	2527	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	526442	0	0
T1	310338	20	0	0
T2	516798	6957	0	0
T3	231750	18	0	0
T4	426979	758	0	0
T7	71842	351	0	0
T8	305991	1551	0	0
T9	50548	105	0	0
T10	1845	14	0	0
T11	659156	1932	0	0
T12	2527	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	203149	0	0
T1	310338	11	0	0
T2	516798	1708	0	0
T3	231750	14	0	0
T4	426979	16	0	0
T7	71842	343	0	0
T8	305991	156	0	0
T9	50548	93	0	0
T10	1845	14	0	0
T11	659156	35	0	0
T12	2527	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	211288	0	0
GntImpliesValid_A	422207318	211288	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	211288	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2806016	0	0
ReadyAndValidImplyGrant_A	422207318	211288	0	0
ReqAndReadyImplyGrant_A	422207318	211288	0	0
ReqImpliesValid_A	422207318	536840	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	211288	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211288	0	0
T1	310338	7	0	0
T2	516798	1761	0	0
T3	231750	11	0	0
T4	426979	11	0	0
T7	71842	874	0	0
T8	305991	152	0	0
T9	50548	90	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211288	0	0
T1	310338	7	0	0
T2	516798	1761	0	0
T3	231750	11	0	0
T4	426979	11	0	0
T7	71842	874	0	0
T8	305991	152	0	0
T9	50548	90	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211288	0	0
T1	310338	7	0	0
T2	516798	1761	0	0
T3	231750	11	0	0
T4	426979	11	0	0
T7	71842	874	0	0
T8	305991	152	0	0
T9	50548	90	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2806016	0	0
T1	310338	28	0	0
T2	516798	9741	0	0
T3	231750	45	0	0
T4	426979	2930	0	0
T7	71842	399	0	0
T8	305991	54932	0	0
T9	50548	702	0	0
T10	1845	11	0	0
T11	659156	14611	0	0
T12	2527	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211288	0	0
T1	310338	7	0	0
T2	516798	1761	0	0
T3	231750	11	0	0
T4	426979	11	0	0
T7	71842	874	0	0
T8	305991	152	0	0
T9	50548	90	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211288	0	0
T1	310338	7	0	0
T2	516798	1761	0	0
T3	231750	11	0	0
T4	426979	11	0	0
T7	71842	874	0	0
T8	305991	152	0	0
T9	50548	90	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	536840	0	0
T1	310338	7	0	0
T2	516798	7446	0	0
T3	231750	15	0	0
T4	426979	11	0	0
T7	71842	1351	0	0
T8	305991	1565	0	0
T9	50548	102	0	0
T10	1845	14	0	0
T11	659156	47	0	0
T12	2527	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211288	0	0
T1	310338	7	0	0
T2	516798	1761	0	0
T3	231750	11	0	0
T4	426979	11	0	0
T7	71842	874	0	0
T8	305991	152	0	0
T9	50548	90	0	0
T10	1845	12	0	0
T11	659156	47	0	0
T12	2527	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	211168	0	0
GntImpliesValid_A	422207318	211168	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	211168	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	2786924	0	0
ReadyAndValidImplyGrant_A	422207318	211168	0	0
ReqAndReadyImplyGrant_A	422207318	211168	0	0
ReqImpliesValid_A	422207318	541395	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	0	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	211168	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211168	0	0
T1	310338	7	0	0
T2	516798	1261	0	0
T3	231750	9	0	0
T4	426979	8	0	0
T7	71842	815	0	0
T8	305991	161	0	0
T9	50548	97	0	0
T10	1845	11	0	0
T11	659156	43	0	0
T12	2527	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211168	0	0
T1	310338	7	0	0
T2	516798	1261	0	0
T3	231750	9	0	0
T4	426979	8	0	0
T7	71842	815	0	0
T8	305991	161	0	0
T9	50548	97	0	0
T10	1845	11	0	0
T11	659156	43	0	0
T12	2527	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211168	0	0
T1	310338	7	0	0
T2	516798	1261	0	0
T3	231750	9	0	0
T4	426979	8	0	0
T7	71842	815	0	0
T8	305991	161	0	0
T9	50548	97	0	0
T10	1845	11	0	0
T11	659156	43	0	0
T12	2527	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2786924	0	0
T1	310338	42	0	0
T2	516798	6836	0	0
T3	231750	46	0	0
T4	426979	3444	0	0
T7	71842	330	0	0
T8	305991	49388	0	0
T9	50548	833	0	0
T10	1845	12	0	0
T11	659156	12899	0	0
T12	2527	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211168	0	0
T1	310338	7	0	0
T2	516798	1261	0	0
T3	231750	9	0	0
T4	426979	8	0	0
T7	71842	815	0	0
T8	305991	161	0	0
T9	50548	97	0	0
T10	1845	11	0	0
T11	659156	43	0	0
T12	2527	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211168	0	0
T1	310338	7	0	0
T2	516798	1261	0	0
T3	231750	9	0	0
T4	426979	8	0	0
T7	71842	815	0	0
T8	305991	161	0	0
T9	50548	97	0	0
T10	1845	11	0	0
T11	659156	43	0	0
T12	2527	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	541395	0	0
T1	310338	7	0	0
T2	516798	2728	0	0
T3	231750	9	0	0
T4	426979	8	0	0
T7	71842	1302	0	0
T8	305991	1621	0	0
T9	50548	113	0	0
T10	1845	11	0	0
T11	659156	429	0	0
T12	2527	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	211168	0	0
T1	310338	7	0	0
T2	516798	1261	0	0
T3	231750	9	0	0
T4	426979	8	0	0
T7	71842	815	0	0
T8	305991	161	0	0
T9	50548	97	0	0
T10	1845	11	0	0
T11	659156	43	0	0
T12	2527	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	820662	0	0
GntImpliesValid_A	422207318	820662	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	820662	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	10710337	0	0
ReadyAndValidImplyGrant_A	422207318	820662	0	0
ReqAndReadyImplyGrant_A	422207318	820662	0	0
ReqImpliesValid_A	422207318	2102366	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	17211	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	820662	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820662	0	0
T1	310338	38	0	0
T2	516798	5765	0	0
T3	231750	56	0	0
T4	426979	46	0	0
T7	71842	3348	0	0
T8	305991	713	0	0
T9	50548	385	0	0
T10	1845	41	0	0
T11	659156	133	0	0
T12	2527	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820662	0	0
T1	310338	38	0	0
T2	516798	5765	0	0
T3	231750	56	0	0
T4	426979	46	0	0
T7	71842	3348	0	0
T8	305991	713	0	0
T9	50548	385	0	0
T10	1845	41	0	0
T11	659156	133	0	0
T12	2527	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820662	0	0
T1	310338	38	0	0
T2	516798	5765	0	0
T3	231750	56	0	0
T4	426979	46	0	0
T7	71842	3348	0	0
T8	305991	713	0	0
T9	50548	385	0	0
T10	1845	41	0	0
T11	659156	133	0	0
T12	2527	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	10710337	0	0
T1	310338	125	0	0
T2	516798	31962	0	0
T3	231750	176	0	0
T4	426979	15198	0	0
T7	71842	2	0	0
T8	305991	218633	0	0
T9	50548	2494	0	0
T10	1845	1	0	0
T11	659156	39928	0	0
T12	2527	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820662	0	0
T1	310338	38	0	0
T2	516798	5765	0	0
T3	231750	56	0	0
T4	426979	46	0	0
T7	71842	3348	0	0
T8	305991	713	0	0
T9	50548	385	0	0
T10	1845	41	0	0
T11	659156	133	0	0
T12	2527	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820662	0	0
T1	310338	38	0	0
T2	516798	5765	0	0
T3	231750	56	0	0
T4	426979	46	0	0
T7	71842	3348	0	0
T8	305991	713	0	0
T9	50548	385	0	0
T10	1845	41	0	0
T11	659156	133	0	0
T12	2527	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	2102366	0	0
T1	310338	47	0	0
T2	516798	17217	0	0
T3	231750	78	0	0
T4	426979	309	0	0
T7	71842	3348	0	0
T8	305991	21562	0	0
T9	50548	602	0	0
T10	1845	41	0	0
T11	659156	4801	0	0
T12	2527	41	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	17211	0	900
T2	516798	22	0	1
T3	231750	0	0	1
T4	426979	0	0	1
T7	71842	138	0	1
T8	305991	0	0	1
T9	50548	0	0	1
T10	1845	0	0	1
T11	659156	0	0	1
T12	2527	0	0	1
T13	106246	0	0	1
T14	0	2	0	0
T17	0	41	0	0
T20	0	1	0	0
T21	0	5	0	0
T22	0	22	0	0
T23	0	8	0	0
T24	0	1	0	0
T25	0	33	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	820662	0	0
T1	310338	38	0	0
T2	516798	5765	0	0
T3	231750	56	0	0
T4	426979	46	0	0
T7	71842	3348	0	0
T8	305991	713	0	0
T9	50548	385	0	0
T10	1845	41	0	0
T11	659156	133	0	0
T12	2527	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422207318	422087488	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422207318	832687	0	0
GntImpliesValid_A	422207318	832687	0	0
GrantKnown_A	422207318	422087488	0	0
IdxKnown_A	422207318	422087488	0	0
IndexIsCorrect_A	422207318	832687	0	0
LockArbDecision_A	422207318	0	0	0
NoReadyValidNoGrant_A	422207318	354174367	0	0
ReadyAndValidImplyGrant_A	422207318	832687	0	0
ReqAndReadyImplyGrant_A	422207318	832687	0	0
ReqImpliesValid_A	422207318	12718790	0	0
ReqStaysHighUntilGranted0_M	422207318	0	0	0
RoundRobin_A	422207318	30100	0	900
ValidKnown_A	422207318	422087488	0	0
gen_data_port_assertion.DataFlow_A	422207318	832687	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	832687	0	0
T1	310338	54	0	0
T2	516798	6545	0	0
T3	231750	56	0	0
T4	426979	43	0	0
T7	71842	4050	0	0
T8	305991	715	0	0
T9	50548	380	0	0
T10	1845	46	0	0
T11	659156	142	0	0
T12	2527	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	832687	0	0
T1	310338	54	0	0
T2	516798	6545	0	0
T3	231750	56	0	0
T4	426979	43	0	0
T7	71842	4050	0	0
T8	305991	715	0	0
T9	50548	380	0	0
T10	1845	46	0	0
T11	659156	142	0	0
T12	2527	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	832687	0	0
T1	310338	54	0	0
T2	516798	6545	0	0
T3	231750	56	0	0
T4	426979	43	0	0
T7	71842	4050	0	0
T8	305991	715	0	0
T9	50548	380	0	0
T10	1845	46	0	0
T11	659156	142	0	0
T12	2527	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	354174367	0	0
T1	310338	258075	0	0
T2	516798	420075	0	0
T3	231750	193046	0	0
T4	426979	405883	0	0
T7	71842	1	0	0
T8	305991	268643	0	0
T9	50548	43287	0	0
T10	1845	1	0	0
T11	659156	605198	0	0
T12	2527	0	0	0
T13	0	90462	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	832687	0	0
T1	310338	54	0	0
T2	516798	6545	0	0
T3	231750	56	0	0
T4	426979	43	0	0
T7	71842	4050	0	0
T8	305991	715	0	0
T9	50548	380	0	0
T10	1845	46	0	0
T11	659156	142	0	0
T12	2527	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	832687	0	0
T1	310338	54	0	0
T2	516798	6545	0	0
T3	231750	56	0	0
T4	426979	43	0	0
T7	71842	4050	0	0
T8	305991	715	0	0
T9	50548	380	0	0
T10	1845	46	0	0
T11	659156	142	0	0
T12	2527	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	12718790	0	0
T1	310338	271	0	0
T2	516798	56182	0	0
T3	231750	238	0	0
T4	426979	13079	0	0
T7	71842	4050	0	0
T8	305991	240132	0	0
T9	50548	3018	0	0
T10	1845	46	0	0
T11	659156	52779	0	0
T12	2527	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	30100	0	900
T2	516798	25	0	1
T3	231750	0	0	1
T4	426979	0	0	1
T7	71842	706	0	1
T8	305991	0	0	1
T9	50548	0	0	1
T10	1845	0	0	1
T11	659156	0	0	1
T12	2527	0	0	1
T13	106246	0	0	1
T14	0	1	0	0
T15	0	481	0	0
T16	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	4	0	0
T22	0	22	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	422087488	0	0
T1	310338	310274	0	0
T2	516798	516726	0	0
T3	231750	231725	0	0
T4	426979	426915	0	0
T7	71842	71782	0	0
T8	305991	305988	0	0
T9	50548	50507	0	0
T10	1845	1807	0	0
T11	659156	659116	0	0
T12	2527	2449	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422207318	832687	0	0
T1	310338	54	0	0
T2	516798	6545	0	0
T3	231750	56	0	0
T4	426979	43	0	0
T7	71842	4050	0	0
T8	305991	715	0	0
T9	50548	380	0	0
T10	1845	46	0	0
T11	659156	142	0	0
T12	2527	30	0	0