Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1549395	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246331

1

T1

180

T2

1809

T3

121

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	609456	1			T1	406		T2	4268		T3	284
values[0x0]	577026	1			T1	404		T2	4275		T3	246
values[0x1]	609244	1			T1	410		T2	4393		T3	282

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1198047	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

597679

1

T1

415

T2

4314

T3

283

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27840	1			T1	3		T2	247		T3	18
valid_sources[0x01]	28151	1			T2	411		T3	12		T10	43
valid_sources[0x02]	27625	1			T1	18		T2	332		T3	12
valid_sources[0x03]	27504	1			T1	6		T2	60		T3	5
valid_sources[0x04]	27569	1			T2	90		T3	8		T10	33
valid_sources[0x05]	28350	1			T1	21		T2	171		T3	9
valid_sources[0x06]	28267	1			T1	60		T2	243		T3	14
valid_sources[0x07]	28682	1			T1	52		T2	233		T3	14
valid_sources[0x08]	28513	1			T1	15		T2	181		T3	13
valid_sources[0x09]	28729	1			T1	24		T2	171		T3	16
valid_sources[0x0a]	28438	1			T1	10		T2	143		T3	14
valid_sources[0x0b]	28856	1			T2	221		T3	14		T10	24
valid_sources[0x0c]	28697	1			T1	31		T2	202		T3	20
valid_sources[0x0d]	27695	1			T2	260		T3	8		T10	26
valid_sources[0x0e]	27956	1			T1	39		T2	79		T3	5
valid_sources[0x0f]	27104	1			T1	20		T2	128		T3	17
valid_sources[0x10]	28110	1			T2	84		T3	14		T10	39
valid_sources[0x11]	27743	1			T2	84		T3	12		T10	32
valid_sources[0x12]	28616	1			T1	15		T2	177		T3	12
valid_sources[0x13]	28923	1			T1	4		T2	125		T3	8
valid_sources[0x14]	27971	1			T1	1		T2	206		T3	15
valid_sources[0x15]	28150	1			T1	20		T2	188		T3	22
valid_sources[0x16]	29610	1			T1	14		T2	192		T3	7
valid_sources[0x17]	27425	1			T1	44		T2	68		T3	5
valid_sources[0x18]	28466	1			T2	157		T3	16		T10	25
valid_sources[0x19]	28560	1			T1	36		T2	320		T3	19
valid_sources[0x1a]	27797	1			T2	119		T3	6		T10	25
valid_sources[0x1b]	28044	1			T1	62		T2	190		T3	19
valid_sources[0x1c]	27576	1			T1	6		T2	247		T3	11
valid_sources[0x1d]	27825	1			T1	4		T2	191		T3	21
valid_sources[0x1e]	27563	1			T1	3		T2	227		T3	9
valid_sources[0x1f]	27361	1			T1	54		T2	119		T3	14
valid_sources[0x20]	27608	1			T1	20		T2	178		T3	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25996

1

T1

22

T2

180

T3

11

values[0x0]

all_enables

biggest_size

194730

1

T1

141

T2

1453

T3

98

values[0x1]

all_enables

biggest_size

25605

1

T1

17

T2

176

T3

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1561916	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253917

1

T1

191

T2

1863

T3

134

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	621794	1			T1	407		T2	4326		T3	329
values[0x0]	572500	1			T1	388		T2	4238		T3	307
values[0x1]	621539	1			T1	403		T2	4360		T3	332

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1199404	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

616429

1

T1

424

T2

4353

T3

334

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27229	1			T1	29		T2	215		T3	13
valid_sources[0x01]	28778	1			T1	33		T2	294		T3	13
valid_sources[0x02]	27457	1			T1	25		T2	244		T3	12
valid_sources[0x03]	28894	1			T1	36		T2	185		T3	19
valid_sources[0x04]	28580	1			T1	20		T2	176		T3	16
valid_sources[0x05]	28552	1			T2	223		T3	10		T10	35
valid_sources[0x06]	27498	1			T1	9		T2	217		T3	16
valid_sources[0x07]	28881	1			T1	28		T2	223		T3	15
valid_sources[0x08]	28408	1			T2	265		T3	15		T10	29
valid_sources[0x09]	29125	1			T1	40		T2	200		T3	16
valid_sources[0x0a]	28360	1			T1	23		T2	275		T3	20
valid_sources[0x0b]	29265	1			T1	35		T2	139		T3	20
valid_sources[0x0c]	28516	1			T1	17		T2	178		T3	18
valid_sources[0x0d]	29066	1			T1	1		T2	213		T3	21
valid_sources[0x0e]	28577	1			T1	14		T2	195		T3	10
valid_sources[0x0f]	28255	1			T1	28		T2	245		T3	15
valid_sources[0x10]	28304	1			T1	7		T2	169		T3	18
valid_sources[0x11]	28009	1			T1	6		T2	106		T3	17
valid_sources[0x12]	28811	1			T1	20		T2	266		T3	13
valid_sources[0x13]	28460	1			T1	9		T2	150		T3	15
valid_sources[0x14]	28887	1			T1	17		T2	237		T3	12
valid_sources[0x15]	27828	1			T1	12		T2	240		T3	12
valid_sources[0x16]	28129	1			T1	5		T2	152		T3	17
valid_sources[0x17]	28178	1			T1	44		T2	168		T3	17
valid_sources[0x18]	28232	1			T1	25		T2	208		T3	14
valid_sources[0x19]	29158	1			T1	2		T2	188		T3	20
valid_sources[0x1a]	28449	1			T1	20		T2	114		T3	14
valid_sources[0x1b]	28572	1			T1	34		T2	202		T3	14
valid_sources[0x1c]	28202	1			T1	16		T2	179		T3	18
valid_sources[0x1d]	28463	1			T2	160		T3	15		T10	30
valid_sources[0x1e]	28087	1			T2	253		T3	13		T10	42
valid_sources[0x1f]	28114	1			T1	29		T2	164		T3	23
valid_sources[0x20]	27557	1			T1	8		T2	283		T3	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26546

1

T1

22

T2

182

T3

16

values[0x0]

all_enables

biggest_size

200665

1

T1

150

T2

1495

T3

102

values[0x1]

all_enables

biggest_size

26706

1

T1

19

T2

186

T3

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1562692	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248140

1

T1

153

T2

1865

T3

126

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	614970	1			T1	402		T2	4337		T3	285
values[0x0]	580967	1			T1	365		T2	4451		T3	293
values[0x1]	614895	1			T1	387		T2	4346		T3	325

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1208297	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

602535

1

T1

374

T2

4362

T3

309

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28175	1			T1	20		T2	267		T3	17
valid_sources[0x01]	28388	1			T1	15		T2	240		T3	15
valid_sources[0x02]	27950	1			T1	20		T2	257		T3	15
valid_sources[0x03]	28231	1			T1	29		T2	172		T3	14
valid_sources[0x04]	27891	1			T1	14		T2	168		T3	16
valid_sources[0x05]	27753	1			T1	17		T2	192		T3	18
valid_sources[0x06]	28583	1			T1	23		T2	212		T3	10
valid_sources[0x07]	28334	1			T1	13		T2	237		T3	7
valid_sources[0x08]	28682	1			T1	7		T2	234		T3	19
valid_sources[0x09]	28826	1			T1	16		T2	170		T3	13
valid_sources[0x0a]	28985	1			T1	22		T2	198		T3	11
valid_sources[0x0b]	28008	1			T1	21		T2	199		T3	10
valid_sources[0x0c]	28527	1			T1	8		T2	235		T3	10
valid_sources[0x0d]	28355	1			T1	23		T2	216		T3	12
valid_sources[0x0e]	28490	1			T1	22		T2	174		T3	19
valid_sources[0x0f]	27643	1			T1	24		T2	202		T3	11
valid_sources[0x10]	28303	1			T1	23		T2	207		T3	17
valid_sources[0x11]	28150	1			T1	14		T2	162		T3	10
valid_sources[0x12]	27972	1			T1	20		T2	237		T3	12
valid_sources[0x13]	29299	1			T1	14		T2	183		T3	12
valid_sources[0x14]	28801	1			T1	29		T2	225		T3	16
valid_sources[0x15]	27650	1			T1	17		T2	181		T3	11
valid_sources[0x16]	28397	1			T1	17		T2	182		T3	15
valid_sources[0x17]	27850	1			T1	17		T2	151		T3	16
valid_sources[0x18]	28405	1			T1	15		T2	200		T3	18
valid_sources[0x19]	28675	1			T1	13		T2	193		T3	14
valid_sources[0x1a]	28693	1			T1	23		T2	183		T3	13
valid_sources[0x1b]	28349	1			T1	26		T2	207		T3	11
valid_sources[0x1c]	28739	1			T1	14		T2	231		T3	11
valid_sources[0x1d]	27809	1			T1	24		T2	189		T3	19
valid_sources[0x1e]	28596	1			T1	19		T2	260		T3	7
valid_sources[0x1f]	27762	1			T1	22		T2	183		T3	14
valid_sources[0x20]	28293	1			T1	13		T2	295		T3	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25999

1

T1

15

T2

186

T3

9

values[0x0]

all_enables

biggest_size

196081

1

T1

121

T2

1525

T3

104

values[0x1]

all_enables

biggest_size

26060

1

T1

17

T2

154

T3

13