Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
153750 |
1 |
|
|
T1 |
43 |
|
T2 |
550 |
|
T3 |
32 |
auto[1] |
79830 |
1 |
|
|
T1 |
47 |
|
T2 |
69 |
|
T10 |
65 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
59296 |
1 |
|
|
T1 |
24 |
|
T2 |
201 |
|
T3 |
12 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
164447 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
69133 |
1 |
|
|
T1 |
32 |
|
T2 |
203 |
|
T3 |
14 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
18357 |
1 |
|
|
T1 |
6 |
|
T2 |
58 |
|
T3 |
3 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
144471 |
1 |
|
|
T1 |
53 |
|
T2 |
872 |
|
T3 |
22 |
auto[1] |
77291 |
1 |
|
|
T1 |
56 |
|
T2 |
289 |
|
T3 |
12 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
56351 |
1 |
|
|
T1 |
44 |
|
T2 |
396 |
|
T3 |
8 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
155855 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
65907 |
1 |
|
|
T1 |
37 |
|
T2 |
383 |
|
T3 |
8 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17532 |
1 |
|
|
T1 |
16 |
|
T2 |
124 |
|
T3 |
1 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
140456 |
1 |
|
|
T1 |
29 |
|
T2 |
655 |
|
T3 |
45 |
auto[1] |
82454 |
1 |
|
|
T1 |
66 |
|
T2 |
11 |
|
T3 |
4 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
56180 |
1 |
|
|
T1 |
35 |
|
T2 |
206 |
|
T3 |
17 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
156733 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
66177 |
1 |
|
|
T1 |
29 |
|
T2 |
200 |
|
T3 |
19 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17479 |
1 |
|
|
T1 |
11 |
|
T2 |
65 |
|
T3 |
7 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
134320 |
1 |
|
|
T1 |
36 |
|
T2 |
416 |
|
T3 |
24 |
auto[1] |
71365 |
1 |
|
|
T1 |
63 |
|
T2 |
228 |
|
T3 |
20 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
51810 |
1 |
|
|
T1 |
28 |
|
T2 |
200 |
|
T3 |
15 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
144844 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
60841 |
1 |
|
|
T1 |
33 |
|
T2 |
215 |
|
T3 |
16 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16064 |
1 |
|
|
T1 |
10 |
|
T2 |
69 |
|
T3 |
3 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
135921 |
1 |
|
|
T1 |
75 |
|
T2 |
748 |
|
T3 |
26 |
auto[1] |
76437 |
1 |
|
|
T1 |
14 |
|
T2 |
1559 |
|
T3 |
5 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
53700 |
1 |
|
|
T1 |
33 |
|
T2 |
766 |
|
T3 |
9 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
149298 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63060 |
1 |
|
|
T1 |
31 |
|
T2 |
726 |
|
T3 |
6 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16764 |
1 |
|
|
T1 |
15 |
|
T2 |
248 |
|
T3 |
1 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
137803 |
1 |
|
|
T1 |
31 |
|
T2 |
871 |
|
T3 |
24 |
auto[1] |
78501 |
1 |
|
|
T1 |
62 |
|
T2 |
662 |
|
T3 |
2 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
53864 |
1 |
|
|
T1 |
31 |
|
T2 |
451 |
|
T3 |
8 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
152562 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63742 |
1 |
|
|
T1 |
27 |
|
T2 |
509 |
|
T3 |
7 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16684 |
1 |
|
|
T1 |
10 |
|
T2 |
156 |
|
T3 |
3 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
566966 |
1 |
|
|
T1 |
288 |
|
T2 |
2852 |
|
T3 |
127 |
auto[1] |
301234 |
1 |
|
|
T1 |
94 |
|
T2 |
792 |
|
T3 |
31 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
220605 |
1 |
|
|
T1 |
141 |
|
T2 |
1193 |
|
T3 |
59 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
605199 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
263001 |
1 |
|
|
T1 |
124 |
|
T2 |
1235 |
|
T3 |
52 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
69497 |
1 |
|
|
T1 |
45 |
|
T2 |
381 |
|
T3 |
17 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
152605 |
1 |
|
|
T1 |
89 |
|
T2 |
1861 |
|
T3 |
27 |
auto[1] |
85500 |
1 |
|
|
T1 |
16 |
|
T2 |
302 |
|
T3 |
13 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
59605 |
1 |
|
|
T1 |
29 |
|
T2 |
704 |
|
T3 |
17 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
167837 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
70268 |
1 |
|
|
T1 |
34 |
|
T2 |
705 |
|
T3 |
14 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
18534 |
1 |
|
|
T1 |
7 |
|
T2 |
237 |
|
T3 |
6 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
138525 |
1 |
|
|
T1 |
61 |
|
T2 |
440 |
|
T3 |
22 |
auto[1] |
71515 |
1 |
|
|
T1 |
41 |
|
T2 |
205 |
|
T3 |
22 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
52499 |
1 |
|
|
T1 |
31 |
|
T2 |
207 |
|
T3 |
20 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
146464 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63576 |
1 |
|
|
T1 |
30 |
|
T2 |
236 |
|
T3 |
14 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16553 |
1 |
|
|
T1 |
5 |
|
T2 |
68 |
|
T3 |
8 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
143323 |
1 |
|
|
T1 |
28 |
|
T2 |
278 |
|
T3 |
10 |
auto[1] |
71338 |
1 |
|
|
T1 |
77 |
|
T2 |
352 |
|
T3 |
21 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
54697 |
1 |
|
|
T1 |
42 |
|
T2 |
204 |
|
T3 |
8 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
151085 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
63576 |
1 |
|
|
T1 |
31 |
|
T2 |
217 |
|
T3 |
12 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16978 |
1 |
|
|
T1 |
12 |
|
T2 |
61 |
|
T3 |
1 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
143455 |
1 |
|
|
T1 |
43 |
|
T2 |
806 |
|
T3 |
27 |
auto[1] |
79652 |
1 |
|
|
T1 |
49 |
|
T2 |
846 |
|
T3 |
1 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
57865 |
1 |
|
|
T1 |
37 |
|
T2 |
591 |
|
T3 |
10 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
155153 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
67954 |
1 |
|
|
T1 |
34 |
|
T2 |
571 |
|
T3 |
9 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
18443 |
1 |
|
|
T1 |
11 |
|
T2 |
189 |
|
T3 |
2 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
135424 |
1 |
|
|
T1 |
50 |
|
T2 |
360 |
|
T3 |
41 |
auto[1] |
71006 |
1 |
|
|
T1 |
59 |
|
T2 |
285 |
|
T3 |
4 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
52144 |
1 |
|
|
T1 |
47 |
|
T2 |
226 |
|
T3 |
20 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
144080 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
62350 |
1 |
|
|
T1 |
32 |
|
T2 |
224 |
|
T3 |
15 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
16367 |
1 |
|
|
T1 |
15 |
|
T2 |
85 |
|
T3 |
5 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
136855 |
1 |
|
|
T1 |
37 |
|
T2 |
263 |
|
T3 |
47 |
auto[1] |
81348 |
1 |
|
|
T1 |
55 |
|
T2 |
360 |
|
T3 |
3 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
55412 |
1 |
|
|
T1 |
29 |
|
T2 |
201 |
|
T3 |
16 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
152071 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
66132 |
1 |
|
|
T1 |
28 |
|
T2 |
186 |
|
T3 |
18 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17454 |
1 |
|
|
T1 |
13 |
|
T2 |
56 |
|
T3 |
6 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
146854 |
1 |
|
|
T1 |
81 |
|
T2 |
1555 |
|
T3 |
26 |
auto[1] |
78674 |
1 |
|
|
T1 |
29 |
|
T2 |
767 |
|
T3 |
4 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
56505 |
1 |
|
|
T1 |
46 |
|
T2 |
740 |
|
T3 |
13 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
159093 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
66435 |
1 |
|
|
T1 |
35 |
|
T2 |
757 |
|
T3 |
9 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17614 |
1 |
|
|
T1 |
15 |
|
T2 |
263 |
|
T3 |
4 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
587435 |
1 |
|
|
T1 |
216 |
|
T2 |
1599 |
|
T3 |
126 |
auto[1] |
305611 |
1 |
|
|
T1 |
167 |
|
T2 |
2067 |
|
T3 |
16 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
227222 |
1 |
|
|
T1 |
120 |
|
T2 |
1230 |
|
T3 |
57 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
622176 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
270870 |
1 |
|
|
T1 |
137 |
|
T2 |
1257 |
|
T3 |
43 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
71757 |
1 |
|
|
T1 |
41 |
|
T2 |
391 |
|
T3 |
16 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
152398 |
1 |
|
|
T1 |
77 |
|
T2 |
528 |
|
T3 |
8 |
auto[1] |
77828 |
1 |
|
|
T1 |
28 |
|
T2 |
136 |
|
T3 |
16 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
57853 |
1 |
|
|
T1 |
38 |
|
T2 |
217 |
|
T3 |
9 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
162378 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
67848 |
1 |
|
|
T1 |
39 |
|
T2 |
192 |
|
T3 |
10 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17865 |
1 |
|
|
T1 |
13 |
|
T2 |
65 |
|
T3 |
5 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
601230 |
1 |
|
|
T1 |
227 |
|
T2 |
2958 |
|
T3 |
135 |
auto[1] |
308912 |
1 |
|
|
T1 |
181 |
|
T2 |
1532 |
|
T3 |
21 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
233091 |
1 |
|
|
T1 |
143 |
|
T2 |
1503 |
|
T3 |
47 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
633768 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
276374 |
1 |
|
|
T1 |
136 |
|
T2 |
1496 |
|
T3 |
58 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
73679 |
1 |
|
|
T1 |
53 |
|
T2 |
504 |
|
T3 |
17 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
153726 |
1 |
|
|
T1 |
30 |
|
T2 |
1016 |
|
T3 |
23 |
auto[1] |
77019 |
1 |
|
|
T1 |
60 |
|
T2 |
123 |
|
T3 |
13 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
58111 |
1 |
|
|
T1 |
26 |
|
T2 |
383 |
|
T3 |
14 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
162714 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
68031 |
1 |
|
|
T1 |
34 |
|
T2 |
394 |
|
T3 |
13 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17896 |
1 |
|
|
T1 |
6 |
|
T2 |
130 |
|
T3 |
8 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
154991 |
1 |
|
|
T1 |
58 |
|
T2 |
419 |
|
T3 |
22 |
auto[1] |
89098 |
1 |
|
|
T1 |
51 |
|
T2 |
670 |
|
T3 |
38 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
61311 |
1 |
|
|
T1 |
39 |
|
T2 |
361 |
|
T3 |
20 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
170110 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
73979 |
1 |
|
|
T1 |
37 |
|
T2 |
375 |
|
T3 |
25 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
19382 |
1 |
|
|
T1 |
13 |
|
T2 |
120 |
|
T3 |
8 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
140511 |
1 |
|
|
T1 |
63 |
|
T2 |
226 |
|
T3 |
14 |
auto[1] |
75783 |
1 |
|
|
T1 |
22 |
|
T2 |
431 |
|
T3 |
19 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
54690 |
1 |
|
|
T1 |
27 |
|
T2 |
236 |
|
T3 |
7 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
152207 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
64087 |
1 |
|
|
T1 |
30 |
|
T2 |
230 |
|
T3 |
11 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17103 |
1 |
|
|
T1 |
8 |
|
T2 |
83 |
|
T3 |
2 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
148696 |
1 |
|
|
T1 |
37 |
|
T2 |
613 |
|
T3 |
35 |
auto[1] |
73135 |
1 |
|
|
T1 |
66 |
|
T2 |
493 |
|
T3 |
3 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
56036 |
1 |
|
|
T1 |
39 |
|
T2 |
376 |
|
T3 |
16 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
155787 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
66044 |
1 |
|
|
T1 |
39 |
|
T2 |
370 |
|
T3 |
9 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17440 |
1 |
|
|
T1 |
17 |
|
T2 |
130 |
|
T3 |
4 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
592605 |
1 |
|
|
T1 |
352 |
|
T2 |
2954 |
|
T3 |
56 |
auto[1] |
301997 |
1 |
|
|
T1 |
52 |
|
T2 |
2096 |
|
T3 |
96 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
229388 |
1 |
|
|
T1 |
118 |
|
T2 |
1713 |
|
T3 |
51 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
622367 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
272235 |
1 |
|
|
T1 |
153 |
|
T2 |
1727 |
|
T3 |
47 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
72875 |
1 |
|
|
T1 |
41 |
|
T2 |
570 |
|
T3 |
13 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
141315 |
1 |
|
|
T1 |
68 |
|
T2 |
928 |
|
T3 |
35 |
auto[1] |
75211 |
1 |
|
|
T1 |
45 |
|
T2 |
262 |
|
T3 |
6 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
54499 |
1 |
|
|
T1 |
27 |
|
T2 |
390 |
|
T3 |
10 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
152254 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
64272 |
1 |
|
|
T1 |
38 |
|
T2 |
367 |
|
T3 |
10 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
17091 |
1 |
|
|
T1 |
13 |
|
T2 |
128 |
|
T3 |
2 |
Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
145065 |
1 |
|
|
T1 |
81 |
|
T2 |
188 |
|
T3 |
19 |
auto[1] |
78538 |
1 |
|
|
T1 |
19 |
|
T2 |
451 |
|
T3 |
8 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
57600 |
1 |
|
|
T1 |
41 |
|
T2 |
213 |
|
T3 |
8 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
155685 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
67918 |
1 |
|
|
T1 |
33 |
|
T2 |
234 |
|
T3 |
9 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
18248 |
1 |
|
|
T1 |
13 |
|
T2 |
82 |
|
T3 |
2 |