Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8000673	0	0
GntImpliesValid_A	2147483647	8000673	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8000673	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	481564562	0	0
ReadyAndValidImplyGrant_A	2147483647	8000673	0	0
ReqAndReadyImplyGrant_A	2147483647	8000673	0	0
ReqImpliesValid_A	2147483647	35665933	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	58896	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8000673	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	142032	141144	0	0
T2	1453896	1452720	0	0
T3	81576	80760	0	0
T7	812928	789600	0	0
T8	284328	283872	0	0
T9	9319680	9319032	0	0
T10	277320	275880	0	0
T11	42000	41352	0	0
T12	5880768	5880696	0	0
T13	12161592	12160656	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8000673	0	0
T1	142032	3572	0	0
T2	1453896	38944	0	0
T3	81576	1351	0	0
T7	812928	3969	0	0
T8	284328	448	0	0
T9	9319680	417	0	0
T10	277320	5911	0	0
T11	42000	406	0	0
T12	5880768	6548	0	0
T13	12161592	488	0	0
T14	0	177	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8000673	0	0
T1	142032	3572	0	0
T2	1453896	38944	0	0
T3	81576	1351	0	0
T7	812928	3969	0	0
T8	284328	448	0	0
T9	9319680	417	0	0
T10	277320	5911	0	0
T11	42000	406	0	0
T12	5880768	6548	0	0
T13	12161592	488	0	0
T14	0	177	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	142032	141144	0	0
T2	1453896	1452720	0	0
T3	81576	80760	0	0
T7	812928	789600	0	0
T8	284328	283872	0	0
T9	9319680	9319032	0	0
T10	277320	275880	0	0
T11	42000	41352	0	0
T12	5880768	5880696	0	0
T13	12161592	12160656	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	142032	141144	0	0
T2	1453896	1452720	0	0
T3	81576	80760	0	0
T7	812928	789600	0	0
T8	284328	283872	0	0
T9	9319680	9319032	0	0
T10	277320	275880	0	0
T11	42000	41352	0	0
T12	5880768	5880696	0	0
T13	12161592	12160656	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8000673	0	0
T1	142032	3572	0	0
T2	1453896	38944	0	0
T3	81576	1351	0	0
T7	812928	3969	0	0
T8	284328	448	0	0
T9	9319680	417	0	0
T10	277320	5911	0	0
T11	42000	406	0	0
T12	5880768	6548	0	0
T13	12161592	488	0	0
T14	0	177	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	481564562	0	0
T1	142032	3622	0	0
T2	1453896	29042	0	0
T3	81576	1621	0	0
T7	812928	50815	0	0
T8	284328	13180	0	0
T9	9319680	475289	0	0
T10	277320	8312	0	0
T11	42000	483	0	0
T12	5880768	225714	0	0
T13	12161592	641410	0	0
T14	0	610	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8000673	0	0
T1	142032	3572	0	0
T2	1453896	38944	0	0
T3	81576	1351	0	0
T7	812928	3969	0	0
T8	284328	448	0	0
T9	9319680	417	0	0
T10	277320	5911	0	0
T11	42000	406	0	0
T12	5880768	6548	0	0
T13	12161592	488	0	0
T14	0	177	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8000673	0	0
T1	142032	3572	0	0
T2	1453896	38944	0	0
T3	81576	1351	0	0
T7	812928	3969	0	0
T8	284328	448	0	0
T9	9319680	417	0	0
T10	277320	5911	0	0
T11	42000	406	0	0
T12	5880768	6548	0	0
T13	12161592	488	0	0
T14	0	177	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35665933	0	0
T1	142032	4074	0	0
T2	1453896	49056	0	0
T3	81576	1572	0	0
T7	812928	12043	0	0
T8	284328	1004	0	0
T9	9319680	28100	0	0
T10	277320	7336	0	0
T11	42000	435	0	0
T12	5880768	15534	0	0
T13	12161592	22382	0	0
T14	0	221	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	58896	0	21600
T1	11836	15	0	2
T2	121158	498	0	2
T3	6798	3	0	2
T4	0	14	0	0
T7	67744	1	0	2
T8	23694	0	0	2
T9	776640	0	0	2
T10	23110	19	0	2
T11	3500	0	0	2
T12	490064	0	0	2
T13	1013466	0	0	2
T15	0	1427	0	0
T16	0	8	0	0
T17	0	82	0	0
T18	0	75	0	0
T19	0	12	0	0
T20	0	84	0	0
T21	0	10	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	142032	141144	0	0
T2	1453896	1452720	0	0
T3	81576	80760	0	0
T7	812928	789600	0	0
T8	284328	283872	0	0
T9	9319680	9319032	0	0
T10	277320	275880	0	0
T11	42000	41352	0	0
T12	5880768	5880696	0	0
T13	12161592	12160656	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8000673	0	0
T1	142032	3572	0	0
T2	1453896	38944	0	0
T3	81576	1351	0	0
T7	812928	3969	0	0
T8	284328	448	0	0
T9	9319680	417	0	0
T10	277320	5911	0	0
T11	42000	406	0	0
T12	5880768	6548	0	0
T13	12161592	488	0	0
T14	0	177	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	910509	0	0
GntImpliesValid_A	441684311	910509	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	910509	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	12916688	0	0
ReadyAndValidImplyGrant_A	441684311	910509	0	0
ReqAndReadyImplyGrant_A	441684311	910509	0	0
ReqImpliesValid_A	441684311	2633236	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	910509	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	910509	0	0
T1	5918	408	0	0
T2	60579	4490	0	0
T3	3399	156	0	0
T7	33872	420	0	0
T8	11847	62	0	0
T9	388320	56	0	0
T10	11555	635	0	0
T11	1750	35	0	0
T12	245032	512	0	0
T13	506733	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	910509	0	0
T1	5918	408	0	0
T2	60579	4490	0	0
T3	3399	156	0	0
T7	33872	420	0	0
T8	11847	62	0	0
T9	388320	56	0	0
T10	11555	635	0	0
T11	1750	35	0	0
T12	245032	512	0	0
T13	506733	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	910509	0	0
T1	5918	408	0	0
T2	60579	4490	0	0
T3	3399	156	0	0
T7	33872	420	0	0
T8	11847	62	0	0
T9	388320	56	0	0
T10	11555	635	0	0
T11	1750	35	0	0
T12	245032	512	0	0
T13	506733	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	12916688	0	0
T1	5918	296	0	0
T2	60579	3135	0	0
T3	3399	137	0	0
T7	33872	3191	0	0
T8	11847	464	0	0
T9	388320	15536	0	0
T10	11555	484	0	0
T11	1750	31	0	0
T12	245032	2124	0	0
T13	506733	14843	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	910509	0	0
T1	5918	408	0	0
T2	60579	4490	0	0
T3	3399	156	0	0
T7	33872	420	0	0
T8	11847	62	0	0
T9	388320	56	0	0
T10	11555	635	0	0
T11	1750	35	0	0
T12	245032	512	0	0
T13	506733	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	910509	0	0
T1	5918	408	0	0
T2	60579	4490	0	0
T3	3399	156	0	0
T7	33872	420	0	0
T8	11847	62	0	0
T9	388320	56	0	0
T10	11555	635	0	0
T11	1750	35	0	0
T12	245032	512	0	0
T13	506733	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	2633236	0	0
T1	5918	521	0	0
T2	60579	5849	0	0
T3	3399	176	0	0
T7	33872	760	0	0
T8	11847	83	0	0
T9	388320	1010	0	0
T10	11555	787	0	0
T11	1750	40	0	0
T12	245032	713	0	0
T13	506733	1195	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	910509	0	0
T1	5918	408	0	0
T2	60579	4490	0	0
T3	3399	156	0	0
T7	33872	420	0	0
T8	11847	62	0	0
T9	388320	56	0	0
T10	11555	635	0	0
T11	1750	35	0	0
T12	245032	512	0	0
T13	506733	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	868390	0	0
GntImpliesValid_A	441684311	868390	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	868390	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	12750440	0	0
ReadyAndValidImplyGrant_A	441684311	868390	0	0
ReqAndReadyImplyGrant_A	441684311	868390	0	0
ReqImpliesValid_A	441684311	2502274	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	868390	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	868390	0	0
T1	5918	382	0	0
T2	60579	3644	0	0
T3	3399	158	0	0
T7	33872	425	0	0
T8	11847	48	0	0
T9	388320	44	0	0
T10	11555	663	0	0
T11	1750	35	0	0
T12	245032	532	0	0
T13	506733	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	868390	0	0
T1	5918	382	0	0
T2	60579	3644	0	0
T3	3399	158	0	0
T7	33872	425	0	0
T8	11847	48	0	0
T9	388320	44	0	0
T10	11555	663	0	0
T11	1750	35	0	0
T12	245032	532	0	0
T13	506733	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	868390	0	0
T1	5918	382	0	0
T2	60579	3644	0	0
T3	3399	158	0	0
T7	33872	425	0	0
T8	11847	48	0	0
T9	388320	44	0	0
T10	11555	663	0	0
T11	1750	35	0	0
T12	245032	532	0	0
T13	506733	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	12750440	0	0
T1	5918	280	0	0
T2	60579	2941	0	0
T3	3399	131	0	0
T7	33872	3283	0	0
T8	11847	366	0	0
T9	388320	16865	0	0
T10	11555	488	0	0
T11	1750	31	0	0
T12	245032	2248	0	0
T13	506733	15248	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	868390	0	0
T1	5918	382	0	0
T2	60579	3644	0	0
T3	3399	158	0	0
T7	33872	425	0	0
T8	11847	48	0	0
T9	388320	44	0	0
T10	11555	663	0	0
T11	1750	35	0	0
T12	245032	532	0	0
T13	506733	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	868390	0	0
T1	5918	382	0	0
T2	60579	3644	0	0
T3	3399	158	0	0
T7	33872	425	0	0
T8	11847	48	0	0
T9	388320	44	0	0
T10	11555	663	0	0
T11	1750	35	0	0
T12	245032	532	0	0
T13	506733	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	2502274	0	0
T1	5918	485	0	0
T2	60579	4351	0	0
T3	3399	186	0	0
T7	33872	701	0	0
T8	11847	100	0	0
T9	388320	2074	0	0
T10	11555	839	0	0
T11	1750	40	0	0
T12	245032	817	0	0
T13	506733	179	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	868390	0	0
T1	5918	382	0	0
T2	60579	3644	0	0
T3	3399	158	0	0
T7	33872	425	0	0
T8	11847	48	0	0
T9	388320	44	0	0
T10	11555	663	0	0
T11	1750	35	0	0
T12	245032	532	0	0
T13	506733	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	225577	0	0
GntImpliesValid_A	441684311	225577	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	225577	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3227327	0	0
ReadyAndValidImplyGrant_A	441684311	225577	0	0
ReqAndReadyImplyGrant_A	441684311	225577	0	0
ReqImpliesValid_A	441684311	597696	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	225577	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	225577	0	0
T1	5918	110	0	0
T2	60579	2322	0	0
T3	3399	30	0	0
T7	33872	234	0	0
T8	11847	9	0	0
T9	388320	8	0	0
T10	11555	173	0	0
T11	1750	12	0	0
T12	245032	1406	0	0
T13	506733	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	225577	0	0
T1	5918	110	0	0
T2	60579	2322	0	0
T3	3399	30	0	0
T7	33872	234	0	0
T8	11847	9	0	0
T9	388320	8	0	0
T10	11555	173	0	0
T11	1750	12	0	0
T12	245032	1406	0	0
T13	506733	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	225577	0	0
T1	5918	110	0	0
T2	60579	2322	0	0
T3	3399	30	0	0
T7	33872	234	0	0
T8	11847	9	0	0
T9	388320	8	0	0
T10	11555	173	0	0
T11	1750	12	0	0
T12	245032	1406	0	0
T13	506733	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3227327	0	0
T1	5918	104	0	0
T2	60579	1161	0	0
T3	3399	30	0	0
T7	33872	1570	0	0
T8	11847	41	0	0
T9	388320	1533	0	0
T10	11555	165	0	0
T11	1750	13	0	0
T12	245032	4551	0	0
T13	506733	3856	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	225577	0	0
T1	5918	110	0	0
T2	60579	2322	0	0
T3	3399	30	0	0
T7	33872	234	0	0
T8	11847	9	0	0
T9	388320	8	0	0
T10	11555	173	0	0
T11	1750	12	0	0
T12	245032	1406	0	0
T13	506733	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	225577	0	0
T1	5918	110	0	0
T2	60579	2322	0	0
T3	3399	30	0	0
T7	33872	234	0	0
T8	11847	9	0	0
T9	388320	8	0	0
T10	11555	173	0	0
T11	1750	12	0	0
T12	245032	1406	0	0
T13	506733	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	597696	0	0
T1	5918	117	0	0
T2	60579	3487	0	0
T3	3399	31	0	0
T7	33872	409	0	0
T8	11847	9	0	0
T9	388320	8	0	0
T10	11555	182	0	0
T11	1750	12	0	0
T12	245032	3449	0	0
T13	506733	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	225577	0	0
T1	5918	110	0	0
T2	60579	2322	0	0
T3	3399	30	0	0
T7	33872	234	0	0
T8	11847	9	0	0
T9	388320	8	0	0
T10	11555	173	0	0
T11	1750	12	0	0
T12	245032	1406	0	0
T13	506733	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	230780	0	0
GntImpliesValid_A	441684311	230780	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	230780	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3252275	0	0
ReadyAndValidImplyGrant_A	441684311	230780	0	0
ReqAndReadyImplyGrant_A	441684311	230780	0	0
ReqImpliesValid_A	441684311	609034	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	230780	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230780	0	0
T1	5918	90	0	0
T2	60579	1139	0	0
T3	3399	36	0	0
T7	33872	68	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	160	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230780	0	0
T1	5918	90	0	0
T2	60579	1139	0	0
T3	3399	36	0	0
T7	33872	68	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	160	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230780	0	0
T1	5918	90	0	0
T2	60579	1139	0	0
T3	3399	36	0	0
T7	33872	68	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	160	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3252275	0	0
T1	5918	87	0	0
T2	60579	839	0	0
T3	3399	35	0	0
T7	33872	540	0	0
T8	11847	84	0	0
T9	388320	2167	0	0
T10	11555	155	0	0
T11	1750	14	0	0
T12	245032	1	0	0
T13	506733	7489	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230780	0	0
T1	5918	90	0	0
T2	60579	1139	0	0
T3	3399	36	0	0
T7	33872	68	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	160	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230780	0	0
T1	5918	90	0	0
T2	60579	1139	0	0
T3	3399	36	0	0
T7	33872	68	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	160	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	609034	0	0
T1	5918	94	0	0
T2	60579	1443	0	0
T3	3399	38	0	0
T7	33872	97	0	0
T8	11847	26	0	0
T9	388320	9	0	0
T10	11555	166	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	453	0	0
T14	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230780	0	0
T1	5918	90	0	0
T2	60579	1139	0	0
T3	3399	36	0	0
T7	33872	68	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	160	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	218317	0	0
GntImpliesValid_A	441684311	218317	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	218317	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	4516151	0	0
ReadyAndValidImplyGrant_A	441684311	218317	0	0
ReqAndReadyImplyGrant_A	441684311	218317	0	0
ReqImpliesValid_A	441684311	957147	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	218317	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	218317	0	0
T1	5918	92	0	0
T2	60579	623	0	0
T3	3399	50	0	0
T7	33872	83	0	0
T8	11847	8	0	0
T9	388320	9	0	0
T10	11555	183	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	218317	0	0
T1	5918	92	0	0
T2	60579	623	0	0
T3	3399	50	0	0
T7	33872	83	0	0
T8	11847	8	0	0
T9	388320	9	0	0
T10	11555	183	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	218317	0	0
T1	5918	92	0	0
T2	60579	623	0	0
T3	3399	50	0	0
T7	33872	83	0	0
T8	11847	8	0	0
T9	388320	9	0	0
T10	11555	183	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	4516151	0	0
T1	5918	394	0	0
T2	60579	2119	0	0
T3	3399	349	0	0
T7	33872	1046	0	0
T8	11847	55	0	0
T9	388320	2377	0	0
T10	11555	2086	0	0
T11	1750	67	0	0
T12	245032	0	0	0
T13	506733	7093	0	0
T14	0	191	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	218317	0	0
T1	5918	92	0	0
T2	60579	623	0	0
T3	3399	50	0	0
T7	33872	83	0	0
T8	11847	8	0	0
T9	388320	9	0	0
T10	11555	183	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	218317	0	0
T1	5918	92	0	0
T2	60579	623	0	0
T3	3399	50	0	0
T7	33872	83	0	0
T8	11847	8	0	0
T9	388320	9	0	0
T10	11555	183	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	957147	0	0
T1	5918	139	0	0
T2	60579	700	0	0
T3	3399	138	0	0
T7	33872	121	0	0
T8	11847	11	0	0
T9	388320	217	0	0
T10	11555	763	0	0
T11	1750	19	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	218317	0	0
T1	5918	92	0	0
T2	60579	623	0	0
T3	3399	50	0	0
T7	33872	83	0	0
T8	11847	8	0	0
T9	388320	9	0	0
T10	11555	183	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	216446	0	0
GntImpliesValid_A	441684311	216446	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	216446	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	6136577	0	0
ReadyAndValidImplyGrant_A	441684311	216446	0	0
ReqAndReadyImplyGrant_A	441684311	216446	0	0
ReqImpliesValid_A	441684311	1291108	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	216446	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216446	0	0
T1	5918	85	0	0
T2	60579	657	0	0
T3	3399	33	0	0
T7	33872	420	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	143	0	0
T11	1750	9	0	0
T12	245032	511	0	0
T13	506733	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216446	0	0
T1	5918	85	0	0
T2	60579	657	0	0
T3	3399	33	0	0
T7	33872	420	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	143	0	0
T11	1750	9	0	0
T12	245032	511	0	0
T13	506733	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216446	0	0
T1	5918	85	0	0
T2	60579	657	0	0
T3	3399	33	0	0
T7	33872	420	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	143	0	0
T11	1750	9	0	0
T12	245032	511	0	0
T13	506733	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	6136577	0	0
T1	5918	324	0	0
T2	60579	2361	0	0
T3	3399	155	0	0
T7	33872	1881	0	0
T8	11847	153	0	0
T9	388320	2086	0	0
T10	11555	765	0	0
T11	1750	34	0	0
T12	245032	2840	0	0
T13	506733	26050	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216446	0	0
T1	5918	85	0	0
T2	60579	657	0	0
T3	3399	33	0	0
T7	33872	420	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	143	0	0
T11	1750	9	0	0
T12	245032	511	0	0
T13	506733	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216446	0	0
T1	5918	85	0	0
T2	60579	657	0	0
T3	3399	33	0	0
T7	33872	420	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	143	0	0
T11	1750	9	0	0
T12	245032	511	0	0
T13	506733	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	1291108	0	0
T1	5918	135	0	0
T2	60579	754	0	0
T3	3399	47	0	0
T7	33872	2423	0	0
T8	11847	10	0	0
T9	388320	48	0	0
T10	11555	299	0	0
T11	1750	12	0	0
T12	245032	1479	0	0
T13	506733	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216446	0	0
T1	5918	85	0	0
T2	60579	657	0	0
T3	3399	33	0	0
T7	33872	420	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	143	0	0
T11	1750	9	0	0
T12	245032	511	0	0
T13	506733	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	221930	0	0
GntImpliesValid_A	441684311	221930	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	221930	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	5274825	0	0
ReadyAndValidImplyGrant_A	441684311	221930	0	0
ReqAndReadyImplyGrant_A	441684311	221930	0	0
ReqImpliesValid_A	441684311	1198581	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	221930	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221930	0	0
T1	5918	103	0	0
T2	60579	1106	0	0
T3	3399	38	0	0
T7	33872	69	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	6	0	0
T12	245032	0	0	0
T13	506733	12	0	0
T14	0	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221930	0	0
T1	5918	103	0	0
T2	60579	1106	0	0
T3	3399	38	0	0
T7	33872	69	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	6	0	0
T12	245032	0	0	0
T13	506733	12	0	0
T14	0	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221930	0	0
T1	5918	103	0	0
T2	60579	1106	0	0
T3	3399	38	0	0
T7	33872	69	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	6	0	0
T12	245032	0	0	0
T13	506733	12	0	0
T14	0	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	5274825	0	0
T1	5918	373	0	0
T2	60579	2365	0	0
T3	3399	143	0	0
T7	33872	785	0	0
T8	11847	47	0	0
T9	388320	1946	0	0
T10	11555	1173	0	0
T11	1750	34	0	0
T12	245032	0	0	0
T13	506733	3112	0	0
T14	0	346	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221930	0	0
T1	5918	103	0	0
T2	60579	1106	0	0
T3	3399	38	0	0
T7	33872	69	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	6	0	0
T12	245032	0	0	0
T13	506733	12	0	0
T14	0	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221930	0	0
T1	5918	103	0	0
T2	60579	1106	0	0
T3	3399	38	0	0
T7	33872	69	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	6	0	0
T12	245032	0	0	0
T13	506733	12	0	0
T14	0	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	1198581	0	0
T1	5918	158	0	0
T2	60579	3244	0	0
T3	3399	59	0	0
T7	33872	96	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	306	0	0
T11	1750	6	0	0
T12	245032	0	0	0
T13	506733	12	0	0
T14	0	54	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221930	0	0
T1	5918	103	0	0
T2	60579	1106	0	0
T3	3399	38	0	0
T7	33872	69	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	6	0	0
T12	245032	0	0	0
T13	506733	12	0	0
T14	0	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	223732	0	0
GntImpliesValid_A	441684311	223732	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	223732	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	5284115	0	0
ReadyAndValidImplyGrant_A	441684311	223732	0	0
ReqAndReadyImplyGrant_A	441684311	223732	0	0
ReqImpliesValid_A	441684311	1205999	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	223732	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223732	0	0
T1	5918	100	0	0
T2	60579	639	0	0
T3	3399	27	0	0
T7	33872	69	0	0
T8	11847	10	0	0
T9	388320	8	0	0
T10	11555	165	0	0
T11	1750	17	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223732	0	0
T1	5918	100	0	0
T2	60579	639	0	0
T3	3399	27	0	0
T7	33872	69	0	0
T8	11847	10	0	0
T9	388320	8	0	0
T10	11555	165	0	0
T11	1750	17	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223732	0	0
T1	5918	100	0	0
T2	60579	639	0	0
T3	3399	27	0	0
T7	33872	69	0	0
T8	11847	10	0	0
T9	388320	8	0	0
T10	11555	165	0	0
T11	1750	17	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	5284115	0	0
T1	5918	415	0	0
T2	60579	2586	0	0
T3	3399	127	0	0
T7	33872	549	0	0
T8	11847	162	0	0
T9	388320	1395	0	0
T10	11555	806	0	0
T11	1750	76	0	0
T12	245032	0	0	0
T13	506733	3287	0	0
T14	0	73	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223732	0	0
T1	5918	100	0	0
T2	60579	639	0	0
T3	3399	27	0	0
T7	33872	69	0	0
T8	11847	10	0	0
T9	388320	8	0	0
T10	11555	165	0	0
T11	1750	17	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223732	0	0
T1	5918	100	0	0
T2	60579	639	0	0
T3	3399	27	0	0
T7	33872	69	0	0
T8	11847	10	0	0
T9	388320	8	0	0
T10	11555	165	0	0
T11	1750	17	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	1205999	0	0
T1	5918	141	0	0
T2	60579	770	0	0
T3	3399	43	0	0
T7	33872	89	0	0
T8	11847	21	0	0
T9	388320	8	0	0
T10	11555	246	0	0
T11	1750	17	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223732	0	0
T1	5918	100	0	0
T2	60579	639	0	0
T3	3399	27	0	0
T7	33872	69	0	0
T8	11847	10	0	0
T9	388320	8	0	0
T10	11555	165	0	0
T11	1750	17	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	216423	0	0
GntImpliesValid_A	441684311	216423	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	216423	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3208725	0	0
ReadyAndValidImplyGrant_A	441684311	216423	0	0
ReqAndReadyImplyGrant_A	441684311	216423	0	0
ReqImpliesValid_A	441684311	591774	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	216423	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216423	0	0
T1	5918	93	0	0
T2	60579	1533	0	0
T3	3399	26	0	0
T7	33872	358	0	0
T8	11847	14	0	0
T9	388320	4	0	0
T10	11555	153	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	11	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216423	0	0
T1	5918	93	0	0
T2	60579	1533	0	0
T3	3399	26	0	0
T7	33872	358	0	0
T8	11847	14	0	0
T9	388320	4	0	0
T10	11555	153	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	11	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216423	0	0
T1	5918	93	0	0
T2	60579	1533	0	0
T3	3399	26	0	0
T7	33872	358	0	0
T8	11847	14	0	0
T9	388320	4	0	0
T10	11555	153	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	11	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3208725	0	0
T1	5918	87	0	0
T2	60579	1079	0	0
T3	3399	27	0	0
T7	33872	1476	0	0
T8	11847	71	0	0
T9	388320	1142	0	0
T10	11555	145	0	0
T11	1750	13	0	0
T12	245032	1	0	0
T13	506733	3674	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216423	0	0
T1	5918	93	0	0
T2	60579	1533	0	0
T3	3399	26	0	0
T7	33872	358	0	0
T8	11847	14	0	0
T9	388320	4	0	0
T10	11555	153	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	11	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216423	0	0
T1	5918	93	0	0
T2	60579	1533	0	0
T3	3399	26	0	0
T7	33872	358	0	0
T8	11847	14	0	0
T9	388320	4	0	0
T10	11555	153	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	11	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	591774	0	0
T1	5918	100	0	0
T2	60579	1991	0	0
T3	3399	26	0	0
T7	33872	2153	0	0
T8	11847	14	0	0
T9	388320	4	0	0
T10	11555	162	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	412	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216423	0	0
T1	5918	93	0	0
T2	60579	1533	0	0
T3	3399	26	0	0
T7	33872	358	0	0
T8	11847	14	0	0
T9	388320	4	0	0
T10	11555	153	0	0
T11	1750	13	0	0
T12	245032	0	0	0
T13	506733	11	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	238166	0	0
GntImpliesValid_A	441684311	238166	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	238166	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3284438	0	0
ReadyAndValidImplyGrant_A	441684311	238166	0	0
ReqAndReadyImplyGrant_A	441684311	238166	0	0
ReqImpliesValid_A	441684311	652251	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	238166	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	238166	0	0
T1	5918	105	0	0
T2	60579	2163	0	0
T3	3399	40	0	0
T7	33872	61	0	0
T8	11847	9	0	0
T9	388320	11	0	0
T10	11555	163	0	0
T11	1750	15	0	0
T12	245032	454	0	0
T13	506733	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	238166	0	0
T1	5918	105	0	0
T2	60579	2163	0	0
T3	3399	40	0	0
T7	33872	61	0	0
T8	11847	9	0	0
T9	388320	11	0	0
T10	11555	163	0	0
T11	1750	15	0	0
T12	245032	454	0	0
T13	506733	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	238166	0	0
T1	5918	105	0	0
T2	60579	2163	0	0
T3	3399	40	0	0
T7	33872	61	0	0
T8	11847	9	0	0
T9	388320	11	0	0
T10	11555	163	0	0
T11	1750	15	0	0
T12	245032	454	0	0
T13	506733	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3284438	0	0
T1	5918	98	0	0
T2	60579	1719	0	0
T3	3399	40	0	0
T7	33872	467	0	0
T8	11847	99	0	0
T9	388320	3154	0	0
T10	11555	157	0	0
T11	1750	15	0	0
T12	245032	1387	0	0
T13	506733	3000	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	238166	0	0
T1	5918	105	0	0
T2	60579	2163	0	0
T3	3399	40	0	0
T7	33872	61	0	0
T8	11847	9	0	0
T9	388320	11	0	0
T10	11555	163	0	0
T11	1750	15	0	0
T12	245032	454	0	0
T13	506733	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	238166	0	0
T1	5918	105	0	0
T2	60579	2163	0	0
T3	3399	40	0	0
T7	33872	61	0	0
T8	11847	9	0	0
T9	388320	11	0	0
T10	11555	163	0	0
T11	1750	15	0	0
T12	245032	454	0	0
T13	506733	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	652251	0	0
T1	5918	113	0	0
T2	60579	2611	0	0
T3	3399	41	0	0
T7	33872	69	0	0
T8	11847	9	0	0
T9	388320	11	0	0
T10	11555	170	0	0
T11	1750	16	0	0
T12	245032	1149	0	0
T13	506733	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	238166	0	0
T1	5918	105	0	0
T2	60579	2163	0	0
T3	3399	40	0	0
T7	33872	61	0	0
T8	11847	9	0	0
T9	388320	11	0	0
T10	11555	163	0	0
T11	1750	15	0	0
T12	245032	454	0	0
T13	506733	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	233629	0	0
GntImpliesValid_A	441684311	233629	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	233629	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3203427	0	0
ReadyAndValidImplyGrant_A	441684311	233629	0	0
ReqAndReadyImplyGrant_A	441684311	233629	0	0
ReqImpliesValid_A	441684311	622023	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	233629	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	233629	0	0
T1	5918	90	0	0
T2	60579	619	0	0
T3	3399	32	0	0
T7	33872	60	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	159	0	0
T11	1750	13	0	0
T12	245032	1086	0	0
T13	506733	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	233629	0	0
T1	5918	90	0	0
T2	60579	619	0	0
T3	3399	32	0	0
T7	33872	60	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	159	0	0
T11	1750	13	0	0
T12	245032	1086	0	0
T13	506733	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	233629	0	0
T1	5918	90	0	0
T2	60579	619	0	0
T3	3399	32	0	0
T7	33872	60	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	159	0	0
T11	1750	13	0	0
T12	245032	1086	0	0
T13	506733	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3203427	0	0
T1	5918	85	0	0
T2	60579	604	0	0
T3	3399	30	0	0
T7	33872	462	0	0
T8	11847	79	0	0
T9	388320	3224	0	0
T10	11555	149	0	0
T11	1750	13	0	0
T12	245032	3538	0	0
T13	506733	6555	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	233629	0	0
T1	5918	90	0	0
T2	60579	619	0	0
T3	3399	32	0	0
T7	33872	60	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	159	0	0
T11	1750	13	0	0
T12	245032	1086	0	0
T13	506733	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	233629	0	0
T1	5918	90	0	0
T2	60579	619	0	0
T3	3399	32	0	0
T7	33872	60	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	159	0	0
T11	1750	13	0	0
T12	245032	1086	0	0
T13	506733	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	622023	0	0
T1	5918	96	0	0
T2	60579	638	0	0
T3	3399	35	0	0
T7	33872	63	0	0
T8	11847	10	0	0
T9	388320	690	0	0
T10	11555	170	0	0
T11	1750	14	0	0
T12	245032	2565	0	0
T13	506733	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	233629	0	0
T1	5918	90	0	0
T2	60579	619	0	0
T3	3399	32	0	0
T7	33872	60	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	159	0	0
T11	1750	13	0	0
T12	245032	1086	0	0
T13	506733	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	212503	0	0
GntImpliesValid_A	441684311	212503	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	212503	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3186563	0	0
ReadyAndValidImplyGrant_A	441684311	212503	0	0
ReqAndReadyImplyGrant_A	441684311	212503	0	0
ReqImpliesValid_A	441684311	537341	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	212503	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	212503	0	0
T1	5918	89	0	0
T2	60579	2307	0	0
T3	3399	31	0	0
T7	33872	68	0	0
T8	11847	8	0	0
T9	388320	12	0	0
T10	11555	172	0	0
T11	1750	24	0	0
T12	245032	525	0	0
T13	506733	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	212503	0	0
T1	5918	89	0	0
T2	60579	2307	0	0
T3	3399	31	0	0
T7	33872	68	0	0
T8	11847	8	0	0
T9	388320	12	0	0
T10	11555	172	0	0
T11	1750	24	0	0
T12	245032	525	0	0
T13	506733	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	212503	0	0
T1	5918	89	0	0
T2	60579	2307	0	0
T3	3399	31	0	0
T7	33872	68	0	0
T8	11847	8	0	0
T9	388320	12	0	0
T10	11555	172	0	0
T11	1750	24	0	0
T12	245032	525	0	0
T13	506733	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3186563	0	0
T1	5918	88	0	0
T2	60579	931	0	0
T3	3399	32	0	0
T7	33872	549	0	0
T8	11847	55	0	0
T9	388320	5270	0	0
T10	11555	163	0	0
T11	1750	23	0	0
T12	245032	1731	0	0
T13	506733	3429	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	212503	0	0
T1	5918	89	0	0
T2	60579	2307	0	0
T3	3399	31	0	0
T7	33872	68	0	0
T8	11847	8	0	0
T9	388320	12	0	0
T10	11555	172	0	0
T11	1750	24	0	0
T12	245032	525	0	0
T13	506733	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	212503	0	0
T1	5918	89	0	0
T2	60579	2307	0	0
T3	3399	31	0	0
T7	33872	68	0	0
T8	11847	8	0	0
T9	388320	12	0	0
T10	11555	172	0	0
T11	1750	24	0	0
T12	245032	525	0	0
T13	506733	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	537341	0	0
T1	5918	91	0	0
T2	60579	3687	0	0
T3	3399	31	0	0
T7	33872	102	0	0
T8	11847	8	0	0
T9	388320	697	0	0
T10	11555	182	0	0
T11	1750	26	0	0
T12	245032	1241	0	0
T13	506733	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	212503	0	0
T1	5918	89	0	0
T2	60579	2307	0	0
T3	3399	31	0	0
T7	33872	68	0	0
T8	11847	8	0	0
T9	388320	12	0	0
T10	11555	172	0	0
T11	1750	24	0	0
T12	245032	525	0	0
T13	506733	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	221801	0	0
GntImpliesValid_A	441684311	221801	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	221801	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3238248	0	0
ReadyAndValidImplyGrant_A	441684311	221801	0	0
ReqAndReadyImplyGrant_A	441684311	221801	0	0
ReqImpliesValid_A	441684311	575075	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	221801	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221801	0	0
T1	5918	109	0	0
T2	60579	1161	0	0
T3	3399	34	0	0
T7	33872	58	0	0
T8	11847	12	0	0
T9	388320	15	0	0
T10	11555	161	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221801	0	0
T1	5918	109	0	0
T2	60579	1161	0	0
T3	3399	34	0	0
T7	33872	58	0	0
T8	11847	12	0	0
T9	388320	15	0	0
T10	11555	161	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221801	0	0
T1	5918	109	0	0
T2	60579	1161	0	0
T3	3399	34	0	0
T7	33872	58	0	0
T8	11847	12	0	0
T9	388320	15	0	0
T10	11555	161	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3238248	0	0
T1	5918	104	0	0
T2	60579	736	0	0
T3	3399	33	0	0
T7	33872	459	0	0
T8	11847	96	0	0
T9	388320	3243	0	0
T10	11555	157	0	0
T11	1750	9	0	0
T12	245032	1	0	0
T13	506733	5907	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221801	0	0
T1	5918	109	0	0
T2	60579	1161	0	0
T3	3399	34	0	0
T7	33872	58	0	0
T8	11847	12	0	0
T9	388320	15	0	0
T10	11555	161	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221801	0	0
T1	5918	109	0	0
T2	60579	1161	0	0
T3	3399	34	0	0
T7	33872	58	0	0
T8	11847	12	0	0
T9	388320	15	0	0
T10	11555	161	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	575075	0	0
T1	5918	115	0	0
T2	60579	1590	0	0
T3	3399	36	0	0
T7	33872	58	0	0
T8	11847	12	0	0
T9	388320	15	0	0
T10	11555	166	0	0
T11	1750	10	0	0
T12	245032	0	0	0
T13	506733	663	0	0
T14	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	221801	0	0
T1	5918	109	0	0
T2	60579	1161	0	0
T3	3399	34	0	0
T7	33872	58	0	0
T8	11847	12	0	0
T9	388320	15	0	0
T10	11555	161	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	222975	0	0
GntImpliesValid_A	441684311	222975	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	222975	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3237044	0	0
ReadyAndValidImplyGrant_A	441684311	222975	0	0
ReqAndReadyImplyGrant_A	441684311	222975	0	0
ReqImpliesValid_A	441684311	652498	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	222975	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	222975	0	0
T1	5918	95	0	0
T2	60579	666	0	0
T3	3399	49	0	0
T7	33872	86	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	174	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	222975	0	0
T1	5918	95	0	0
T2	60579	666	0	0
T3	3399	49	0	0
T7	33872	86	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	174	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	222975	0	0
T1	5918	95	0	0
T2	60579	666	0	0
T3	3399	49	0	0
T7	33872	86	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	174	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3237044	0	0
T1	5918	94	0	0
T2	60579	655	0	0
T3	3399	47	0	0
T7	33872	651	0	0
T8	11847	75	0	0
T9	388320	2270	0	0
T10	11555	163	0	0
T11	1750	14	0	0
T12	245032	1	0	0
T13	506733	3010	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	222975	0	0
T1	5918	95	0	0
T2	60579	666	0	0
T3	3399	49	0	0
T7	33872	86	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	174	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	222975	0	0
T1	5918	95	0	0
T2	60579	666	0	0
T3	3399	49	0	0
T7	33872	86	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	174	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	652498	0	0
T1	5918	97	0	0
T2	60579	681	0	0
T3	3399	52	0	0
T7	33872	94	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	186	0	0
T11	1750	15	0	0
T12	245032	0	0	0
T13	506733	215	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	222975	0	0
T1	5918	95	0	0
T2	60579	666	0	0
T3	3399	49	0	0
T7	33872	86	0	0
T8	11847	15	0	0
T9	388320	9	0	0
T10	11555	174	0	0
T11	1750	14	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	205725	0	0
GntImpliesValid_A	441684311	205725	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	205725	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3130681	0	0
ReadyAndValidImplyGrant_A	441684311	205725	0	0
ReqAndReadyImplyGrant_A	441684311	205725	0	0
ReqImpliesValid_A	441684311	540422	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	205725	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	205725	0	0
T1	5918	99	0	0
T2	60579	644	0	0
T3	3399	44	0	0
T7	33872	98	0	0
T8	11847	15	0	0
T9	388320	10	0	0
T10	11555	151	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	205725	0	0
T1	5918	99	0	0
T2	60579	644	0	0
T3	3399	44	0	0
T7	33872	98	0	0
T8	11847	15	0	0
T9	388320	10	0	0
T10	11555	151	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	205725	0	0
T1	5918	99	0	0
T2	60579	644	0	0
T3	3399	44	0	0
T7	33872	98	0	0
T8	11847	15	0	0
T9	388320	10	0	0
T10	11555	151	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3130681	0	0
T1	5918	93	0	0
T2	60579	624	0	0
T3	3399	44	0	0
T7	33872	723	0	0
T8	11847	91	0	0
T9	388320	3027	0	0
T10	11555	144	0	0
T11	1750	12	0	0
T12	245032	1	0	0
T13	506733	2934	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	205725	0	0
T1	5918	99	0	0
T2	60579	644	0	0
T3	3399	44	0	0
T7	33872	98	0	0
T8	11847	15	0	0
T9	388320	10	0	0
T10	11555	151	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	205725	0	0
T1	5918	99	0	0
T2	60579	644	0	0
T3	3399	44	0	0
T7	33872	98	0	0
T8	11847	15	0	0
T9	388320	10	0	0
T10	11555	151	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	540422	0	0
T1	5918	106	0	0
T2	60579	668	0	0
T3	3399	45	0	0
T7	33872	152	0	0
T8	11847	22	0	0
T9	388320	285	0	0
T10	11555	159	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	205725	0	0
T1	5918	99	0	0
T2	60579	644	0	0
T3	3399	44	0	0
T7	33872	98	0	0
T8	11847	15	0	0
T9	388320	10	0	0
T10	11555	151	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	15	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	210096	0	0
GntImpliesValid_A	441684311	210096	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	210096	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3203137	0	0
ReadyAndValidImplyGrant_A	441684311	210096	0	0
ReqAndReadyImplyGrant_A	441684311	210096	0	0
ReqImpliesValid_A	441684311	522940	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	210096	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	210096	0	0
T1	5918	102	0	0
T2	60579	645	0	0
T3	3399	44	0	0
T7	33872	67	0	0
T8	11847	11	0	0
T9	388320	15	0	0
T10	11555	163	0	0
T11	1750	12	0	0
T12	245032	501	0	0
T13	506733	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	210096	0	0
T1	5918	102	0	0
T2	60579	645	0	0
T3	3399	44	0	0
T7	33872	67	0	0
T8	11847	11	0	0
T9	388320	15	0	0
T10	11555	163	0	0
T11	1750	12	0	0
T12	245032	501	0	0
T13	506733	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	210096	0	0
T1	5918	102	0	0
T2	60579	645	0	0
T3	3399	44	0	0
T7	33872	67	0	0
T8	11847	11	0	0
T9	388320	15	0	0
T10	11555	163	0	0
T11	1750	12	0	0
T12	245032	501	0	0
T13	506733	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3203137	0	0
T1	5918	97	0	0
T2	60579	640	0	0
T3	3399	43	0	0
T7	33872	571	0	0
T8	11847	105	0	0
T9	388320	4371	0	0
T10	11555	156	0	0
T11	1750	13	0	0
T12	245032	1679	0	0
T13	506733	6990	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	210096	0	0
T1	5918	102	0	0
T2	60579	645	0	0
T3	3399	44	0	0
T7	33872	67	0	0
T8	11847	11	0	0
T9	388320	15	0	0
T10	11555	163	0	0
T11	1750	12	0	0
T12	245032	501	0	0
T13	506733	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	210096	0	0
T1	5918	102	0	0
T2	60579	645	0	0
T3	3399	44	0	0
T7	33872	67	0	0
T8	11847	11	0	0
T9	388320	15	0	0
T10	11555	163	0	0
T11	1750	12	0	0
T12	245032	501	0	0
T13	506733	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	522940	0	0
T1	5918	108	0	0
T2	60579	654	0	0
T3	3399	46	0	0
T7	33872	99	0	0
T8	11847	11	0	0
T9	388320	15	0	0
T10	11555	171	0	0
T11	1750	12	0	0
T12	245032	1220	0	0
T13	506733	377	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	210096	0	0
T1	5918	102	0	0
T2	60579	645	0	0
T3	3399	44	0	0
T7	33872	67	0	0
T8	11847	11	0	0
T9	388320	15	0	0
T10	11555	163	0	0
T11	1750	12	0	0
T12	245032	501	0	0
T13	506733	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	244138	0	0
GntImpliesValid_A	441684311	244138	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	244138	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3323838	0	0
ReadyAndValidImplyGrant_A	441684311	244138	0	0
ReqAndReadyImplyGrant_A	441684311	244138	0	0
ReqImpliesValid_A	441684311	627454	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	244138	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	244138	0	0
T1	5918	109	0	0
T2	60579	1089	0	0
T3	3399	60	0	0
T7	33872	67	0	0
T8	11847	17	0	0
T9	388320	5	0	0
T10	11555	165	0	0
T11	1750	8	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	244138	0	0
T1	5918	109	0	0
T2	60579	1089	0	0
T3	3399	60	0	0
T7	33872	67	0	0
T8	11847	17	0	0
T9	388320	5	0	0
T10	11555	165	0	0
T11	1750	8	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	244138	0	0
T1	5918	109	0	0
T2	60579	1089	0	0
T3	3399	60	0	0
T7	33872	67	0	0
T8	11847	17	0	0
T9	388320	5	0	0
T10	11555	165	0	0
T11	1750	8	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3323838	0	0
T1	5918	105	0	0
T2	60579	933	0	0
T3	3399	56	0	0
T7	33872	574	0	0
T8	11847	131	0	0
T9	388320	1791	0	0
T10	11555	153	0	0
T11	1750	9	0	0
T12	245032	1	0	0
T13	506733	2973	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	244138	0	0
T1	5918	109	0	0
T2	60579	1089	0	0
T3	3399	60	0	0
T7	33872	67	0	0
T8	11847	17	0	0
T9	388320	5	0	0
T10	11555	165	0	0
T11	1750	8	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	244138	0	0
T1	5918	109	0	0
T2	60579	1089	0	0
T3	3399	60	0	0
T7	33872	67	0	0
T8	11847	17	0	0
T9	388320	5	0	0
T10	11555	165	0	0
T11	1750	8	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	627454	0	0
T1	5918	114	0	0
T2	60579	1249	0	0
T3	3399	65	0	0
T7	33872	92	0	0
T8	11847	17	0	0
T9	388320	5	0	0
T10	11555	178	0	0
T11	1750	8	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	244138	0	0
T1	5918	109	0	0
T2	60579	1089	0	0
T3	3399	60	0	0
T7	33872	67	0	0
T8	11847	17	0	0
T9	388320	5	0	0
T10	11555	165	0	0
T11	1750	8	0	0
T12	245032	0	0	0
T13	506733	14	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	206463	0	0
GntImpliesValid_A	441684311	206463	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	206463	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3234905	0	0
ReadyAndValidImplyGrant_A	441684311	206463	0	0
ReqAndReadyImplyGrant_A	441684311	206463	0	0
ReqImpliesValid_A	441684311	523736	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	206463	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	206463	0	0
T1	5918	109	0	0
T2	60579	645	0	0
T3	3399	45	0	0
T7	33872	71	0	0
T8	11847	12	0	0
T9	388320	11	0	0
T10	11555	160	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	21	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	206463	0	0
T1	5918	109	0	0
T2	60579	645	0	0
T3	3399	45	0	0
T7	33872	71	0	0
T8	11847	12	0	0
T9	388320	11	0	0
T10	11555	160	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	21	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	206463	0	0
T1	5918	109	0	0
T2	60579	645	0	0
T3	3399	45	0	0
T7	33872	71	0	0
T8	11847	12	0	0
T9	388320	11	0	0
T10	11555	160	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	21	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3234905	0	0
T1	5918	104	0	0
T2	60579	637	0	0
T3	3399	42	0	0
T7	33872	490	0	0
T8	11847	93	0	0
T9	388320	3470	0	0
T10	11555	154	0	0
T11	1750	16	0	0
T12	245032	1	0	0
T13	506733	6399	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	206463	0	0
T1	5918	109	0	0
T2	60579	645	0	0
T3	3399	45	0	0
T7	33872	71	0	0
T8	11847	12	0	0
T9	388320	11	0	0
T10	11555	160	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	21	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	206463	0	0
T1	5918	109	0	0
T2	60579	645	0	0
T3	3399	45	0	0
T7	33872	71	0	0
T8	11847	12	0	0
T9	388320	11	0	0
T10	11555	160	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	21	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	523736	0	0
T1	5918	115	0	0
T2	60579	657	0	0
T3	3399	49	0	0
T7	33872	89	0	0
T8	11847	24	0	0
T9	388320	555	0	0
T10	11555	167	0	0
T11	1750	17	0	0
T12	245032	0	0	0
T13	506733	407	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	206463	0	0
T1	5918	109	0	0
T2	60579	645	0	0
T3	3399	45	0	0
T7	33872	71	0	0
T8	11847	12	0	0
T9	388320	11	0	0
T10	11555	160	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	21	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	214826	0	0
GntImpliesValid_A	441684311	214826	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	214826	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3265149	0	0
ReadyAndValidImplyGrant_A	441684311	214826	0	0
ReqAndReadyImplyGrant_A	441684311	214826	0	0
ReqImpliesValid_A	441684311	568063	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	214826	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	214826	0	0
T1	5918	105	0	0
T2	60579	630	0	0
T3	3399	31	0	0
T7	33872	95	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	214826	0	0
T1	5918	105	0	0
T2	60579	630	0	0
T3	3399	31	0	0
T7	33872	95	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	214826	0	0
T1	5918	105	0	0
T2	60579	630	0	0
T3	3399	31	0	0
T7	33872	95	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3265149	0	0
T1	5918	99	0	0
T2	60579	621	0	0
T3	3399	28	0	0
T7	33872	709	0	0
T8	11847	89	0	0
T9	388320	4204	0	0
T10	11555	154	0	0
T11	1750	16	0	0
T12	245032	1	0	0
T13	506733	3977	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	214826	0	0
T1	5918	105	0	0
T2	60579	630	0	0
T3	3399	31	0	0
T7	33872	95	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	214826	0	0
T1	5918	105	0	0
T2	60579	630	0	0
T3	3399	31	0	0
T7	33872	95	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	568063	0	0
T1	5918	112	0	0
T2	60579	643	0	0
T3	3399	35	0	0
T7	33872	118	0	0
T8	11847	15	0	0
T9	388320	12	0	0
T10	11555	161	0	0
T11	1750	17	0	0
T12	245032	0	0	0
T13	506733	163	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	214826	0	0
T1	5918	105	0	0
T2	60579	630	0	0
T3	3399	31	0	0
T7	33872	95	0	0
T8	11847	10	0	0
T9	388320	12	0	0
T10	11555	157	0	0
T11	1750	16	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	223170	0	0
GntImpliesValid_A	441684311	223170	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	223170	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3189870	0	0
ReadyAndValidImplyGrant_A	441684311	223170	0	0
ReqAndReadyImplyGrant_A	441684311	223170	0	0
ReqImpliesValid_A	441684311	557196	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	223170	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223170	0	0
T1	5918	92	0	0
T2	60579	1652	0	0
T3	3399	28	0	0
T7	33872	69	0	0
T8	11847	13	0	0
T9	388320	18	0	0
T10	11555	164	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223170	0	0
T1	5918	92	0	0
T2	60579	1652	0	0
T3	3399	28	0	0
T7	33872	69	0	0
T8	11847	13	0	0
T9	388320	18	0	0
T10	11555	164	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223170	0	0
T1	5918	92	0	0
T2	60579	1652	0	0
T3	3399	28	0	0
T7	33872	69	0	0
T8	11847	13	0	0
T9	388320	18	0	0
T10	11555	164	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3189870	0	0
T1	5918	86	0	0
T2	60579	736	0	0
T3	3399	26	0	0
T7	33872	469	0	0
T8	11847	102	0	0
T9	388320	5577	0	0
T10	11555	157	0	0
T11	1750	12	0	0
T12	245032	1	0	0
T13	506733	5083	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223170	0	0
T1	5918	92	0	0
T2	60579	1652	0	0
T3	3399	28	0	0
T7	33872	69	0	0
T8	11847	13	0	0
T9	388320	18	0	0
T10	11555	164	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223170	0	0
T1	5918	92	0	0
T2	60579	1652	0	0
T3	3399	28	0	0
T7	33872	69	0	0
T8	11847	13	0	0
T9	388320	18	0	0
T10	11555	164	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	557196	0	0
T1	5918	99	0	0
T2	60579	2572	0	0
T3	3399	31	0	0
T7	33872	82	0	0
T8	11847	13	0	0
T9	388320	59	0	0
T10	11555	172	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	223170	0	0
T1	5918	92	0	0
T2	60579	1652	0	0
T3	3399	28	0	0
T7	33872	69	0	0
T8	11847	13	0	0
T9	388320	18	0	0
T10	11555	164	0	0
T11	1750	11	0	0
T12	245032	0	0	0
T13	506733	13	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	216551	0	0
GntImpliesValid_A	441684311	216551	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	216551	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3235386	0	0
ReadyAndValidImplyGrant_A	441684311	216551	0	0
ReqAndReadyImplyGrant_A	441684311	216551	0	0
ReqImpliesValid_A	441684311	565320	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	216551	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216551	0	0
T1	5918	113	0	0
T2	60579	1190	0	0
T3	3399	41	0	0
T7	33872	72	0	0
T8	11847	7	0	0
T9	388320	10	0	0
T10	11555	184	0	0
T11	1750	7	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216551	0	0
T1	5918	113	0	0
T2	60579	1190	0	0
T3	3399	41	0	0
T7	33872	72	0	0
T8	11847	7	0	0
T9	388320	10	0	0
T10	11555	184	0	0
T11	1750	7	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216551	0	0
T1	5918	113	0	0
T2	60579	1190	0	0
T3	3399	41	0	0
T7	33872	72	0	0
T8	11847	7	0	0
T9	388320	10	0	0
T10	11555	184	0	0
T11	1750	7	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3235386	0	0
T1	5918	105	0	0
T2	60579	965	0	0
T3	3399	40	0	0
T7	33872	559	0	0
T8	11847	60	0	0
T9	388320	3801	0	0
T10	11555	179	0	0
T11	1750	7	0	0
T12	245032	1	0	0
T13	506733	7207	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216551	0	0
T1	5918	113	0	0
T2	60579	1190	0	0
T3	3399	41	0	0
T7	33872	72	0	0
T8	11847	7	0	0
T9	388320	10	0	0
T10	11555	184	0	0
T11	1750	7	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216551	0	0
T1	5918	113	0	0
T2	60579	1190	0	0
T3	3399	41	0	0
T7	33872	72	0	0
T8	11847	7	0	0
T9	388320	10	0	0
T10	11555	184	0	0
T11	1750	7	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	565320	0	0
T1	5918	122	0	0
T2	60579	1419	0	0
T3	3399	43	0	0
T7	33872	94	0	0
T8	11847	7	0	0
T9	388320	726	0	0
T10	11555	190	0	0
T11	1750	8	0	0
T12	245032	0	0	0
T13	506733	927	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	216551	0	0
T1	5918	113	0	0
T2	60579	1190	0	0
T3	3399	41	0	0
T7	33872	72	0	0
T8	11847	7	0	0
T9	388320	10	0	0
T10	11555	184	0	0
T11	1750	7	0	0
T12	245032	0	0	0
T13	506733	24	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	230260	0	0
GntImpliesValid_A	441684311	230260	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	230260	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	3202423	0	0
ReadyAndValidImplyGrant_A	441684311	230260	0	0
ReqAndReadyImplyGrant_A	441684311	230260	0	0
ReqImpliesValid_A	441684311	600494	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	0	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	230260	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230260	0	0
T1	5918	105	0	0
T2	60579	664	0	0
T3	3399	24	0	0
T7	33872	76	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	164	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230260	0	0
T1	5918	105	0	0
T2	60579	664	0	0
T3	3399	24	0	0
T7	33872	76	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	164	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230260	0	0
T1	5918	105	0	0
T2	60579	664	0	0
T3	3399	24	0	0
T7	33872	76	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	164	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	3202423	0	0
T1	5918	102	0	0
T2	60579	650	0	0
T3	3399	24	0	0
T7	33872	588	0	0
T8	11847	60	0	0
T9	388320	3458	0	0
T10	11555	157	0	0
T11	1750	9	0	0
T12	245032	1	0	0
T13	506733	3491	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230260	0	0
T1	5918	105	0	0
T2	60579	664	0	0
T3	3399	24	0	0
T7	33872	76	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	164	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230260	0	0
T1	5918	105	0	0
T2	60579	664	0	0
T3	3399	24	0	0
T7	33872	76	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	164	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	600494	0	0
T1	5918	109	0	0
T2	60579	682	0	0
T3	3399	25	0	0
T7	33872	82	0	0
T8	11847	7	0	0
T9	388320	544	0	0
T10	11555	172	0	0
T11	1750	10	0	0
T12	245032	0	0	0
T13	506733	325	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	230260	0	0
T1	5918	105	0	0
T2	60579	664	0	0
T3	3399	24	0	0
T7	33872	76	0	0
T8	11847	7	0	0
T9	388320	12	0	0
T10	11555	164	0	0
T11	1750	9	0	0
T12	245032	0	0	0
T13	506733	10	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	893540	0	0
GntImpliesValid_A	441684311	893540	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	893540	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	12408140	0	0
ReadyAndValidImplyGrant_A	441684311	893540	0	0
ReqAndReadyImplyGrant_A	441684311	893540	0	0
ReqImpliesValid_A	441684311	2404583	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	22921	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	893540	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	893540	0	0
T1	5918	383	0	0
T2	60579	3666	0	0
T3	3399	142	0	0
T7	33872	480	0	0
T8	11847	64	0	0
T9	388320	51	0	0
T10	11555	655	0	0
T11	1750	44	0	0
T12	245032	521	0	0
T13	506733	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	893540	0	0
T1	5918	383	0	0
T2	60579	3666	0	0
T3	3399	142	0	0
T7	33872	480	0	0
T8	11847	64	0	0
T9	388320	51	0	0
T10	11555	655	0	0
T11	1750	44	0	0
T12	245032	521	0	0
T13	506733	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	893540	0	0
T1	5918	383	0	0
T2	60579	3666	0	0
T3	3399	142	0	0
T7	33872	480	0	0
T8	11847	64	0	0
T9	388320	51	0	0
T10	11555	655	0	0
T11	1750	44	0	0
T12	245032	521	0	0
T13	506733	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	12408140	0	0
T1	5918	1	0	0
T2	60579	4	0	0
T3	3399	1	0	0
T7	33872	3031	0	0
T8	11847	413	0	0
T9	388320	15862	0	0
T10	11555	1	0	0
T11	1750	1	0	0
T12	245032	1649	0	0
T13	506733	14428	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	893540	0	0
T1	5918	383	0	0
T2	60579	3666	0	0
T3	3399	142	0	0
T7	33872	480	0	0
T8	11847	64	0	0
T9	388320	51	0	0
T10	11555	655	0	0
T11	1750	44	0	0
T12	245032	521	0	0
T13	506733	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	893540	0	0
T1	5918	383	0	0
T2	60579	3666	0	0
T3	3399	142	0	0
T7	33872	480	0	0
T8	11847	64	0	0
T9	388320	51	0	0
T10	11555	655	0	0
T11	1750	44	0	0
T12	245032	521	0	0
T13	506733	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	2404583	0	0
T1	5918	383	0	0
T2	60579	3666	0	0
T3	3399	142	0	0
T7	33872	1012	0	0
T8	11847	108	0	0
T9	388320	1022	0	0
T10	11555	655	0	0
T11	1750	44	0	0
T12	245032	658	0	0
T13	506733	911	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	22921	0	900
T1	5918	8	0	1
T2	60579	40	0	1
T3	3399	1	0	1
T4	0	14	0	0
T7	33872	1	0	1
T8	11847	0	0	1
T9	388320	0	0	1
T10	11555	8	0	1
T11	1750	0	0	1
T12	245032	0	0	1
T13	506733	0	0	1
T16	0	3	0	0
T18	0	58	0	0
T19	0	5	0	0
T21	0	10	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	893540	0	0
T1	5918	383	0	0
T2	60579	3666	0	0
T3	3399	142	0	0
T7	33872	480	0	0
T8	11847	64	0	0
T9	388320	51	0	0
T10	11555	655	0	0
T11	1750	44	0	0
T12	245032	521	0	0
T13	506733	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441684311	441557175	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441684311	894726	0	0
GntImpliesValid_A	441684311	894726	0	0
GrantKnown_A	441684311	441557175	0	0
IdxKnown_A	441684311	441557175	0	0
IndexIsCorrect_A	441684311	894726	0	0
LockArbDecision_A	441684311	0	0	0
NoReadyValidNoGrant_A	441684311	370654190	0	0
ReadyAndValidImplyGrant_A	441684311	894726	0	0
ReqAndReadyImplyGrant_A	441684311	894726	0	0
ReqImpliesValid_A	441684311	14129688	0	0
ReqStaysHighUntilGranted0_M	441684311	0	0	0
RoundRobin_A	441684311	35975	0	900
ValidKnown_A	441684311	441557175	0	0
gen_data_port_assertion.DataFlow_A	441684311	894726	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	894726	0	0
T1	5918	404	0	0
T2	60579	5050	0	0
T3	3399	152	0	0
T7	33872	395	0	0
T8	11847	55	0	0
T9	388320	52	0	0
T10	11555	687	0	0
T11	1750	43	0	0
T12	245032	500	0	0
T13	506733	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	894726	0	0
T1	5918	404	0	0
T2	60579	5050	0	0
T3	3399	152	0	0
T7	33872	395	0	0
T8	11847	55	0	0
T9	388320	52	0	0
T10	11555	687	0	0
T11	1750	43	0	0
T12	245032	500	0	0
T13	506733	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	894726	0	0
T1	5918	404	0	0
T2	60579	5050	0	0
T3	3399	152	0	0
T7	33872	395	0	0
T8	11847	55	0	0
T9	388320	52	0	0
T10	11555	687	0	0
T11	1750	43	0	0
T12	245032	500	0	0
T13	506733	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	370654190	0	0
T1	5918	1	0	0
T2	60579	1	0	0
T3	3399	1	0	0
T7	33872	26192	0	0
T8	11847	10189	0	0
T9	388320	367520	0	0
T10	11555	1	0	0
T11	1750	1	0	0
T12	245032	203956	0	0
T13	506733	481375	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	894726	0	0
T1	5918	404	0	0
T2	60579	5050	0	0
T3	3399	152	0	0
T7	33872	395	0	0
T8	11847	55	0	0
T9	388320	52	0	0
T10	11555	687	0	0
T11	1750	43	0	0
T12	245032	500	0	0
T13	506733	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	894726	0	0
T1	5918	404	0	0
T2	60579	5050	0	0
T3	3399	152	0	0
T7	33872	395	0	0
T8	11847	55	0	0
T9	388320	52	0	0
T10	11555	687	0	0
T11	1750	43	0	0
T12	245032	500	0	0
T13	506733	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	14129688	0	0
T1	5918	404	0	0
T2	60579	5050	0	0
T3	3399	152	0	0
T7	33872	2988	0	0
T8	11847	445	0	0
T9	388320	20065	0	0
T10	11555	687	0	0
T11	1750	43	0	0
T12	245032	2243	0	0
T13	506733	15967	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	35975	0	900
T1	5918	7	0	1
T2	60579	458	0	1
T3	3399	2	0	1
T7	33872	0	0	1
T8	11847	0	0	1
T9	388320	0	0	1
T10	11555	11	0	1
T11	1750	0	0	1
T12	245032	0	0	1
T13	506733	0	0	1
T15	0	1427	0	0
T16	0	5	0	0
T17	0	82	0	0
T18	0	17	0	0
T19	0	7	0	0
T20	0	84	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	441557175	0	0
T1	5918	5881	0	0
T2	60579	60530	0	0
T3	3399	3365	0	0
T7	33872	32900	0	0
T8	11847	11828	0	0
T9	388320	388293	0	0
T10	11555	11495	0	0
T11	1750	1723	0	0
T12	245032	245029	0	0
T13	506733	506694	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441684311	894726	0	0
T1	5918	404	0	0
T2	60579	5050	0	0
T3	3399	152	0	0
T7	33872	395	0	0
T8	11847	55	0	0
T9	388320	52	0	0
T10	11555	687	0	0
T11	1750	43	0	0
T12	245032	500	0	0
T13	506733	44	0	0