Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1505258	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238563

1

T1

576

T2

22

T3

942

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	591805	1			T1	1428		T2	55		T3	2207
values[0x0]	559125	1			T1	1438		T2	51		T3	2258
values[0x1]	592891	1			T1	1370		T2	48		T3	2203

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1162665	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

581156

1

T1

1408

T2

53

T3

2223

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27497	1			T1	58		T2	2		T3	95
valid_sources[0x01]	26514	1			T1	98		T2	3		T3	94
valid_sources[0x02]	27279	1			T1	65		T2	6		T3	31
valid_sources[0x03]	28033	1			T1	61		T3	183		T8	14
valid_sources[0x04]	26230	1			T1	71		T3	51		T8	12
valid_sources[0x05]	27928	1			T1	62		T2	4		T3	75
valid_sources[0x06]	26529	1			T1	79		T2	2		T3	85
valid_sources[0x07]	27218	1			T1	93		T2	3		T3	87
valid_sources[0x08]	27344	1			T1	49		T2	2		T3	38
valid_sources[0x09]	27691	1			T1	61		T2	3		T3	106
valid_sources[0x0a]	27431	1			T1	80		T2	2		T3	104
valid_sources[0x0b]	27308	1			T1	71		T2	2		T3	24
valid_sources[0x0c]	27899	1			T1	81		T2	3		T3	112
valid_sources[0x0d]	26695	1			T1	63		T2	4		T3	70
valid_sources[0x0e]	27645	1			T1	43		T3	75		T7	1
valid_sources[0x0f]	26922	1			T1	42		T2	5		T3	114
valid_sources[0x10]	26607	1			T1	70		T2	5		T3	100
valid_sources[0x11]	26228	1			T1	66		T2	3		T3	72
valid_sources[0x12]	27190	1			T1	45		T2	2		T3	211
valid_sources[0x13]	27427	1			T1	72		T2	2		T3	159
valid_sources[0x14]	26555	1			T1	66		T2	2		T3	56
valid_sources[0x15]	27790	1			T1	79		T2	1		T3	155
valid_sources[0x16]	26883	1			T1	83		T3	34		T8	12
valid_sources[0x17]	26759	1			T1	74		T2	1		T3	55
valid_sources[0x18]	27660	1			T1	83		T2	2		T3	60
valid_sources[0x19]	28198	1			T1	46		T2	6		T3	147
valid_sources[0x1a]	27605	1			T1	67		T3	250		T7	1
valid_sources[0x1b]	26927	1			T1	71		T2	1		T3	203
valid_sources[0x1c]	27426	1			T1	70		T2	1		T3	119
valid_sources[0x1d]	26855	1			T1	68		T2	3		T3	91
valid_sources[0x1e]	27846	1			T1	63		T2	1		T3	94
valid_sources[0x1f]	26888	1			T1	76		T2	1		T3	64
valid_sources[0x20]	26503	1			T1	75		T2	3		T3	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24958

1

T1

57

T2

1

T3

83

values[0x0]

all_enables

biggest_size

188325

1

T1

467

T2

19

T3

742

values[0x1]

all_enables

biggest_size

25280

1

T1

52

T2

2

T3

117

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1518499	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246388

1

T1

580

T2

19

T3

969

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	604333	1			T1	1459		T2	38		T3	2260
values[0x0]	555765	1			T1	1464		T2	44		T3	2239
values[0x1]	604789	1			T1	1487		T2	37		T3	2371

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1165594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

599293

1

T1

1441

T2

39

T3

2314

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28042	1			T1	85		T2	1		T3	110
valid_sources[0x01]	27654	1			T1	60		T2	1		T3	100
valid_sources[0x02]	27815	1			T1	69		T3	92		T7	2
valid_sources[0x03]	27128	1			T1	101		T3	135		T8	23
valid_sources[0x04]	27040	1			T1	55		T2	2		T3	79
valid_sources[0x05]	27829	1			T1	74		T2	5		T3	87
valid_sources[0x06]	28053	1			T1	91		T3	99		T8	16
valid_sources[0x07]	27518	1			T1	80		T2	1		T3	74
valid_sources[0x08]	27234	1			T1	74		T2	2		T3	83
valid_sources[0x09]	27600	1			T1	66		T3	89		T8	37
valid_sources[0x0a]	27732	1			T1	35		T2	3		T3	84
valid_sources[0x0b]	28249	1			T1	89		T2	5		T3	94
valid_sources[0x0c]	27905	1			T1	45		T2	2		T3	112
valid_sources[0x0d]	27298	1			T1	72		T2	4		T3	84
valid_sources[0x0e]	27709	1			T1	64		T2	3		T3	75
valid_sources[0x0f]	27593	1			T1	49		T2	1		T3	85
valid_sources[0x10]	27970	1			T1	80		T2	1		T3	83
valid_sources[0x11]	27414	1			T1	72		T2	1		T3	79
valid_sources[0x12]	27462	1			T1	73		T2	3		T3	139
valid_sources[0x13]	27433	1			T1	103		T2	1		T3	152
valid_sources[0x14]	27395	1			T1	76		T2	5		T3	82
valid_sources[0x15]	27214	1			T1	68		T2	1		T3	109
valid_sources[0x16]	26806	1			T1	40		T2	1		T3	90
valid_sources[0x17]	27708	1			T1	85		T2	3		T3	102
valid_sources[0x18]	28251	1			T1	68		T2	1		T3	92
valid_sources[0x19]	27180	1			T1	76		T2	2		T3	98
valid_sources[0x1a]	27884	1			T1	63		T2	1		T3	170
valid_sources[0x1b]	28084	1			T1	51		T2	3		T3	138
valid_sources[0x1c]	28086	1			T1	80		T2	1		T3	109
valid_sources[0x1d]	27533	1			T1	59		T2	2		T3	119
valid_sources[0x1e]	27912	1			T1	49		T2	4		T3	95
valid_sources[0x1f]	27264	1			T1	79		T2	1		T3	106
valid_sources[0x20]	26787	1			T1	69		T2	5		T3	70

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26175

1

T1

55

T2

4

T3

97

values[0x0]

all_enables

biggest_size

193967

1

T1

470

T2

12

T3

772

values[0x1]

all_enables

biggest_size

26246

1

T1

55

T2

3

T3

100

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1513572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

240646

1

T1

626

T2

18

T3

958

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	595100	1			T1	1574		T2	43		T3	2293
values[0x0]	563273	1			T1	1450		T2	42		T3	2236
values[0x1]	595845	1			T1	1540		T2	44		T3	2253

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1169432	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

584786

1

T1

1506

T2

41

T3

2262

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27148	1			T1	64		T3	126		T7	2
valid_sources[0x01]	27306	1			T1	66		T3	81		T7	2
valid_sources[0x02]	27624	1			T1	93		T3	84		T7	2
valid_sources[0x03]	27393	1			T1	55		T2	5		T3	136
valid_sources[0x04]	28224	1			T1	76		T2	1		T3	66
valid_sources[0x05]	28173	1			T1	77		T3	101		T8	1
valid_sources[0x06]	27363	1			T1	64		T2	2		T3	101
valid_sources[0x07]	27585	1			T1	91		T3	48		T8	24
valid_sources[0x08]	27026	1			T1	65		T2	3		T3	77
valid_sources[0x09]	27351	1			T1	77		T3	71		T7	1
valid_sources[0x0a]	27783	1			T1	65		T3	78		T8	23
valid_sources[0x0b]	27697	1			T1	72		T2	9		T3	85
valid_sources[0x0c]	28042	1			T1	73		T3	124		T8	35
valid_sources[0x0d]	26569	1			T1	71		T3	104		T7	1
valid_sources[0x0e]	27879	1			T1	66		T3	96		T7	3
valid_sources[0x0f]	27186	1			T1	53		T3	110		T7	1
valid_sources[0x10]	27733	1			T1	70		T2	1		T3	84
valid_sources[0x11]	27291	1			T1	73		T3	100		T8	24
valid_sources[0x12]	27420	1			T1	78		T3	127		T7	2
valid_sources[0x13]	27378	1			T1	95		T3	166		T7	1
valid_sources[0x14]	26521	1			T1	83		T3	102		T8	4
valid_sources[0x15]	26931	1			T1	77		T2	9		T3	95
valid_sources[0x16]	26720	1			T1	62		T3	96		T7	2
valid_sources[0x17]	27669	1			T1	75		T2	8		T3	98
valid_sources[0x18]	27093	1			T1	76		T3	87		T7	1
valid_sources[0x19]	26926	1			T1	75		T3	96		T7	1
valid_sources[0x1a]	26994	1			T1	76		T3	173		T7	2
valid_sources[0x1b]	27401	1			T1	72		T3	155		T7	1
valid_sources[0x1c]	26635	1			T1	58		T3	99		T7	1
valid_sources[0x1d]	27758	1			T1	62		T2	5		T3	96
valid_sources[0x1e]	27201	1			T1	70		T3	113		T8	34
valid_sources[0x1f]	27242	1			T1	63		T2	6		T3	86
valid_sources[0x20]	28218	1			T1	77		T2	9		T3	76

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25461

1

T1

73

T2

1

T3

88

values[0x0]

all_enables

biggest_size

190199

1

T1

497

T2

12

T3

767

values[0x1]

all_enables

biggest_size

24986

1

T1

56

T2

5

T3

103