Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21576	21576	0	0
GntImpliesReady_A	2147483647	7797164	0	0
GntImpliesValid_A	2147483647	7797164	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7797164	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	447117693	0	0
ReadyAndValidImplyGrant_A	2147483647	7797164	0	0
ReqAndReadyImplyGrant_A	2147483647	7797164	0	0
ReqImpliesValid_A	2147483647	33845583	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	56196	0	21576
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7797164	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3054720	3053928	0	0
T2	39000	38616	0	0
T3	5081160	5079216	0	0
T7	588504	586920	0	0
T8	840480	812304	0	0
T9	482832	480504	0	0
T10	246960	246024	0	0
T11	164664	162792	0	0
T12	286944	285312	0	0
T13	6077592	6076536	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21576	21576	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7797164	0	0
T1	1909200	13206	0	0
T2	39000	401	0	0
T3	5081160	17855	0	0
T7	588504	1728	0	0
T8	840480	3098	0	0
T9	482832	9698	0	0
T10	246960	452	0	0
T11	164664	2263	0	0
T12	286944	473	0	0
T13	6077592	508	0	0
T14	26118	583	0	0
T15	0	190	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7797164	0	0
T1	1909200	13206	0	0
T2	39000	401	0	0
T3	5081160	17855	0	0
T7	588504	1728	0	0
T8	840480	3098	0	0
T9	482832	9698	0	0
T10	246960	452	0	0
T11	164664	2263	0	0
T12	286944	473	0	0
T13	6077592	508	0	0
T14	26118	583	0	0
T15	0	190	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3054720	3053928	0	0
T2	39000	38616	0	0
T3	5081160	5079216	0	0
T7	588504	586920	0	0
T8	840480	812304	0	0
T9	482832	480504	0	0
T10	246960	246024	0	0
T11	164664	162792	0	0
T12	286944	285312	0	0
T13	6077592	6076536	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3054720	3053928	0	0
T2	39000	38616	0	0
T3	5081160	5079216	0	0
T7	588504	586920	0	0
T8	840480	812304	0	0
T9	482832	480504	0	0
T10	246960	246024	0	0
T11	164664	162792	0	0
T12	286944	285312	0	0
T13	6077592	6076536	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7797164	0	0
T1	1909200	13206	0	0
T2	39000	401	0	0
T3	5081160	17855	0	0
T7	588504	1728	0	0
T8	840480	3098	0	0
T9	482832	9698	0	0
T10	246960	452	0	0
T11	164664	2263	0	0
T12	286944	473	0	0
T13	6077592	508	0	0
T14	26118	583	0	0
T15	0	190	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	447117693	0	0
T1	2927440	143279	0	0
T2	39000	468	0	0
T3	5081160	331888	0	0
T7	588504	33412	0	0
T8	840480	51565	0	0
T9	482832	962	0	0
T10	246960	12180	0	0
T11	164664	3798	0	0
T12	286944	13994	0	0
T13	6077592	212637	0	0
T14	2902	316	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7797164	0	0
T1	1909200	13206	0	0
T2	39000	401	0	0
T3	5081160	17855	0	0
T7	588504	1728	0	0
T8	840480	3098	0	0
T9	482832	9698	0	0
T10	246960	452	0	0
T11	164664	2263	0	0
T12	286944	473	0	0
T13	6077592	508	0	0
T14	26118	583	0	0
T15	0	190	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7797164	0	0
T1	1909200	13206	0	0
T2	39000	401	0	0
T3	5081160	17855	0	0
T7	588504	1728	0	0
T8	840480	3098	0	0
T9	482832	9698	0	0
T10	246960	452	0	0
T11	164664	2263	0	0
T12	286944	473	0	0
T13	6077592	508	0	0
T14	26118	583	0	0
T15	0	190	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33845583	0	0
T1	1909200	100910	0	0
T2	39000	441	0	0
T3	5081160	38535	0	0
T7	588504	3542	0	0
T8	840480	8347	0	0
T9	482832	20939	0	0
T10	246960	888	0	0
T11	164664	2679	0	0
T12	286944	1022	0	0
T13	6077592	810	0	0
T14	26118	636	0	0
T15	0	248	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	56196	0	21576
T1	127280	25	0	1
T2	1625	0	0	1
T3	423430	4	0	2
T4	0	15	0	0
T7	49042	0	0	2
T8	70040	1	0	2
T9	40236	1289	0	2
T10	20580	0	0	2
T11	13722	6	0	2
T12	23912	0	0	2
T13	506466	0	0	2
T14	2902	3	0	1
T16	0	1	0	0
T17	0	3	0	0
T18	0	10	0	0
T19	0	11	0	0
T20	0	22	0	0
T21	0	8	0	0
T22	0	11	0	0
T23	0	7	0	0
T24	0	39	0	0
T25	0	86	0	0
T26	9860	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3054720	3053928	0	0
T2	39000	38616	0	0
T3	5081160	5079216	0	0
T7	588504	586920	0	0
T8	840480	812304	0	0
T9	482832	480504	0	0
T10	246960	246024	0	0
T11	164664	162792	0	0
T12	286944	285312	0	0
T13	6077592	6076536	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7797164	0	0
T1	1909200	13206	0	0
T2	39000	401	0	0
T3	5081160	17855	0	0
T7	588504	1728	0	0
T8	840480	3098	0	0
T9	482832	9698	0	0
T10	246960	452	0	0
T11	164664	2263	0	0
T12	286944	473	0	0
T13	6077592	508	0	0
T14	26118	583	0	0
T15	0	190	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	875035	0	0
GntImpliesValid_A	416917799	875035	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	875035	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	11333351	0	0
ReadyAndValidImplyGrant_A	416917799	875035	0	0
ReqAndReadyImplyGrant_A	416917799	875035	0	0
ReqImpliesValid_A	416917799	2370713	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	875035	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	875035	0	0
T1	127280	965	0	0
T2	1625	48	0	0
T3	211715	1961	0	0
T7	24521	204	0	0
T8	35020	405	0	0
T9	20118	1310	0	0
T10	10290	41	0	0
T11	6861	244	0	0
T12	11956	40	0	0
T13	253233	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	875035	0	0
T1	127280	965	0	0
T2	1625	48	0	0
T3	211715	1961	0	0
T7	24521	204	0	0
T8	35020	405	0	0
T9	20118	1310	0	0
T10	10290	41	0	0
T11	6861	244	0	0
T12	11956	40	0	0
T13	253233	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	875035	0	0
T1	127280	965	0	0
T2	1625	48	0	0
T3	211715	1961	0	0
T7	24521	204	0	0
T8	35020	405	0	0
T9	20118	1310	0	0
T10	10290	41	0	0
T11	6861	244	0	0
T12	11956	40	0	0
T13	253233	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	11333351	0	0
T1	127280	6612	0	0
T2	1625	34	0	0
T3	211715	13998	0	0
T7	24521	1528	0	0
T8	35020	3016	0	0
T9	20118	379	0	0
T10	10290	276	0	0
T11	6861	205	0	0
T12	11956	291	0	0
T13	253233	281	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	875035	0	0
T1	127280	965	0	0
T2	1625	48	0	0
T3	211715	1961	0	0
T7	24521	204	0	0
T8	35020	405	0	0
T9	20118	1310	0	0
T10	10290	41	0	0
T11	6861	244	0	0
T12	11956	40	0	0
T13	253233	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	875035	0	0
T1	127280	965	0	0
T2	1625	48	0	0
T3	211715	1961	0	0
T7	24521	204	0	0
T8	35020	405	0	0
T9	20118	1310	0	0
T10	10290	41	0	0
T11	6861	244	0	0
T12	11956	40	0	0
T13	253233	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2370713	0	0
T1	127280	1537	0	0
T2	1625	63	0	0
T3	211715	3137	0	0
T7	24521	316	0	0
T8	35020	643	0	0
T9	20118	2242	0	0
T10	10290	47	0	0
T11	6861	284	0	0
T12	11956	55	0	0
T13	253233	96	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	875035	0	0
T1	127280	965	0	0
T2	1625	48	0	0
T3	211715	1961	0	0
T7	24521	204	0	0
T8	35020	405	0	0
T9	20118	1310	0	0
T10	10290	41	0	0
T11	6861	244	0	0
T12	11956	40	0	0
T13	253233	67	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	864650	0	0
GntImpliesValid_A	416917799	864650	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	864650	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	11258966	0	0
ReadyAndValidImplyGrant_A	416917799	864650	0	0
ReqAndReadyImplyGrant_A	416917799	864650	0	0
ReqImpliesValid_A	416917799	2418049	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	864650	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	864650	0	0
T1	127280	1682	0	0
T2	1625	35	0	0
T3	211715	2050	0	0
T7	24521	176	0	0
T8	35020	426	0	0
T9	20118	584	0	0
T10	10290	43	0	0
T11	6861	258	0	0
T12	11956	45	0	0
T13	253233	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	864650	0	0
T1	127280	1682	0	0
T2	1625	35	0	0
T3	211715	2050	0	0
T7	24521	176	0	0
T8	35020	426	0	0
T9	20118	584	0	0
T10	10290	43	0	0
T11	6861	258	0	0
T12	11956	45	0	0
T13	253233	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	864650	0	0
T1	127280	1682	0	0
T2	1625	35	0	0
T3	211715	2050	0	0
T7	24521	176	0	0
T8	35020	426	0	0
T9	20118	584	0	0
T10	10290	43	0	0
T11	6861	258	0	0
T12	11956	45	0	0
T13	253233	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	11258966	0	0
T1	127280	8088	0	0
T2	1625	30	0	0
T3	211715	14766	0	0
T7	24521	1171	0	0
T8	35020	3008	0	0
T9	20118	404	0	0
T10	10290	320	0	0
T11	6861	203	0	0
T12	11956	321	0	0
T13	253233	294	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	864650	0	0
T1	127280	1682	0	0
T2	1625	35	0	0
T3	211715	2050	0	0
T7	24521	176	0	0
T8	35020	426	0	0
T9	20118	584	0	0
T10	10290	43	0	0
T11	6861	258	0	0
T12	11956	45	0	0
T13	253233	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	864650	0	0
T1	127280	1682	0	0
T2	1625	35	0	0
T3	211715	2050	0	0
T7	24521	176	0	0
T8	35020	426	0	0
T9	20118	584	0	0
T10	10290	43	0	0
T11	6861	258	0	0
T12	11956	45	0	0
T13	253233	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2418049	0	0
T1	127280	8312	0	0
T2	1625	41	0	0
T3	211715	3216	0	0
T7	24521	237	0	0
T8	35020	710	0	0
T9	20118	765	0	0
T10	10290	58	0	0
T11	6861	314	0	0
T12	11956	54	0	0
T13	253233	87	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	864650	0	0
T1	127280	1682	0	0
T2	1625	35	0	0
T3	211715	2050	0	0
T7	24521	176	0	0
T8	35020	426	0	0
T9	20118	584	0	0
T10	10290	43	0	0
T11	6861	258	0	0
T12	11956	45	0	0
T13	253233	67	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	218209	0	0
GntImpliesValid_A	416917799	218209	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	218209	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2891453	0	0
ReadyAndValidImplyGrant_A	416917799	218209	0	0
ReqAndReadyImplyGrant_A	416917799	218209	0	0
ReqImpliesValid_A	416917799	612079	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	218209	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218209	0	0
T2	1625	17	0	0
T3	211715	502	0	0
T7	24521	42	0	0
T8	35020	376	0	0
T9	20118	414	0	0
T10	10290	12	0	0
T11	6861	57	0	0
T12	11956	15	0	0
T13	253233	8	0	0
T14	2902	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218209	0	0
T2	1625	17	0	0
T3	211715	502	0	0
T7	24521	42	0	0
T8	35020	376	0	0
T9	20118	414	0	0
T10	10290	12	0	0
T11	6861	57	0	0
T12	11956	15	0	0
T13	253233	8	0	0
T14	2902	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218209	0	0
T2	1625	17	0	0
T3	211715	502	0	0
T7	24521	42	0	0
T8	35020	376	0	0
T9	20118	414	0	0
T10	10290	12	0	0
T11	6861	57	0	0
T12	11956	15	0	0
T13	253233	8	0	0
T14	2902	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2891453	0	0
T1	127280	1	0	0
T2	1625	17	0	0
T3	211715	3895	0	0
T7	24521	266	0	0
T8	35020	1971	0	0
T9	20118	2	0	0
T10	10290	91	0	0
T11	6861	53	0	0
T12	11956	123	0	0
T13	253233	35	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218209	0	0
T2	1625	17	0	0
T3	211715	502	0	0
T7	24521	42	0	0
T8	35020	376	0	0
T9	20118	414	0	0
T10	10290	12	0	0
T11	6861	57	0	0
T12	11956	15	0	0
T13	253233	8	0	0
T14	2902	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218209	0	0
T2	1625	17	0	0
T3	211715	502	0	0
T7	24521	42	0	0
T8	35020	376	0	0
T9	20118	414	0	0
T10	10290	12	0	0
T11	6861	57	0	0
T12	11956	15	0	0
T13	253233	8	0	0
T14	2902	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	612079	0	0
T2	1625	18	0	0
T3	211715	564	0	0
T7	24521	54	0	0
T8	35020	1914	0	0
T9	20118	827	0	0
T10	10290	12	0	0
T11	6861	62	0	0
T12	11956	15	0	0
T13	253233	8	0	0
T14	2902	49	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218209	0	0
T2	1625	17	0	0
T3	211715	502	0	0
T7	24521	42	0	0
T8	35020	376	0	0
T9	20118	414	0	0
T10	10290	12	0	0
T11	6861	57	0	0
T12	11956	15	0	0
T13	253233	8	0	0
T14	2902	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	207468	0	0
GntImpliesValid_A	416917799	207468	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	207468	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2807931	0	0
ReadyAndValidImplyGrant_A	416917799	207468	0	0
ReqAndReadyImplyGrant_A	416917799	207468	0	0
ReqImpliesValid_A	416917799	589120	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	207468	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207468	0	0
T1	127280	482	0	0
T2	1625	11	0	0
T3	211715	498	0	0
T7	24521	45	0	0
T8	35020	58	0	0
T9	20118	950	0	0
T10	10290	13	0	0
T11	6861	64	0	0
T12	11956	15	0	0
T13	253233	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207468	0	0
T1	127280	482	0	0
T2	1625	11	0	0
T3	211715	498	0	0
T7	24521	45	0	0
T8	35020	58	0	0
T9	20118	950	0	0
T10	10290	13	0	0
T11	6861	64	0	0
T12	11956	15	0	0
T13	253233	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207468	0	0
T1	127280	482	0	0
T2	1625	11	0	0
T3	211715	498	0	0
T7	24521	45	0	0
T8	35020	58	0	0
T9	20118	950	0	0
T10	10290	13	0	0
T11	6861	64	0	0
T12	11956	15	0	0
T13	253233	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2807931	0	0
T1	127280	386	0	0
T2	1625	11	0	0
T3	211715	3883	0	0
T7	24521	330	0	0
T8	35020	474	0	0
T9	20118	6	0	0
T10	10290	94	0	0
T11	6861	60	0	0
T12	11956	117	0	0
T13	253233	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207468	0	0
T1	127280	482	0	0
T2	1625	11	0	0
T3	211715	498	0	0
T7	24521	45	0	0
T8	35020	58	0	0
T9	20118	950	0	0
T10	10290	13	0	0
T11	6861	64	0	0
T12	11956	15	0	0
T13	253233	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207468	0	0
T1	127280	482	0	0
T2	1625	11	0	0
T3	211715	498	0	0
T7	24521	45	0	0
T8	35020	58	0	0
T9	20118	950	0	0
T10	10290	13	0	0
T11	6861	64	0	0
T12	11956	15	0	0
T13	253233	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	589120	0	0
T1	127280	5121	0	0
T2	1625	12	0	0
T3	211715	579	0	0
T7	24521	49	0	0
T8	35020	68	0	0
T9	20118	1895	0	0
T10	10290	32	0	0
T11	6861	69	0	0
T12	11956	15	0	0
T13	253233	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207468	0	0
T1	127280	482	0	0
T2	1625	11	0	0
T3	211715	498	0	0
T7	24521	45	0	0
T8	35020	58	0	0
T9	20118	950	0	0
T10	10290	13	0	0
T11	6861	64	0	0
T12	11956	15	0	0
T13	253233	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	218063	0	0
GntImpliesValid_A	416917799	218063	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	218063	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	4845950	0	0
ReadyAndValidImplyGrant_A	416917799	218063	0	0
ReqAndReadyImplyGrant_A	416917799	218063	0	0
ReqImpliesValid_A	416917799	1214152	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	218063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218063	0	0
T1	127280	903	0	0
T2	1625	12	0	0
T3	211715	498	0	0
T7	24521	58	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	17	0	0
T11	6861	72	0	0
T12	11956	20	0	0
T13	253233	8	0	0
T14	0	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218063	0	0
T1	127280	903	0	0
T2	1625	12	0	0
T3	211715	498	0	0
T7	24521	58	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	17	0	0
T11	6861	72	0	0
T12	11956	20	0	0
T13	253233	8	0	0
T14	0	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218063	0	0
T1	127280	903	0	0
T2	1625	12	0	0
T3	211715	498	0	0
T7	24521	58	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	17	0	0
T11	6861	72	0	0
T12	11956	20	0	0
T13	253233	8	0	0
T14	0	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	4845950	0	0
T1	127280	1548	0	0
T2	1625	83	0	0
T3	211715	9275	0	0
T7	24521	555	0	0
T8	35020	1658	0	0
T9	20118	0	0	0
T10	10290	122	0	0
T11	6861	980	0	0
T12	11956	258	0	0
T13	253233	48	0	0
T14	0	105	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218063	0	0
T1	127280	903	0	0
T2	1625	12	0	0
T3	211715	498	0	0
T7	24521	58	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	17	0	0
T11	6861	72	0	0
T12	11956	20	0	0
T13	253233	8	0	0
T14	0	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218063	0	0
T1	127280	903	0	0
T2	1625	12	0	0
T3	211715	498	0	0
T7	24521	58	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	17	0	0
T11	6861	72	0	0
T12	11956	20	0	0
T13	253233	8	0	0
T14	0	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	1214152	0	0
T1	127280	8294	0	0
T2	1625	18	0	0
T3	211715	888	0	0
T7	24521	77	0	0
T8	35020	90	0	0
T9	20118	0	0	0
T10	10290	17	0	0
T11	6861	194	0	0
T12	11956	20	0	0
T13	253233	27	0	0
T14	0	37	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	218063	0	0
T1	127280	903	0	0
T2	1625	12	0	0
T3	211715	498	0	0
T7	24521	58	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	17	0	0
T11	6861	72	0	0
T12	11956	20	0	0
T13	253233	8	0	0
T14	0	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	214812	0	0
GntImpliesValid_A	416917799	214812	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	214812	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	4872245	0	0
ReadyAndValidImplyGrant_A	416917799	214812	0	0
ReqAndReadyImplyGrant_A	416917799	214812	0	0
ReqImpliesValid_A	416917799	1377400	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	214812	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	214812	0	0
T1	127280	371	0	0
T2	1625	14	0	0
T3	211715	478	0	0
T7	24521	38	0	0
T8	35020	61	0	0
T9	20118	537	0	0
T10	10290	16	0	0
T11	6861	56	0	0
T12	11956	17	0	0
T13	253233	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	214812	0	0
T1	127280	371	0	0
T2	1625	14	0	0
T3	211715	478	0	0
T7	24521	38	0	0
T8	35020	61	0	0
T9	20118	537	0	0
T10	10290	16	0	0
T11	6861	56	0	0
T12	11956	17	0	0
T13	253233	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	214812	0	0
T1	127280	371	0	0
T2	1625	14	0	0
T3	211715	478	0	0
T7	24521	38	0	0
T8	35020	61	0	0
T9	20118	537	0	0
T10	10290	16	0	0
T11	6861	56	0	0
T12	11956	17	0	0
T13	253233	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	4872245	0	0
T1	127280	295	0	0
T2	1625	49	0	0
T3	211715	28819	0	0
T7	24521	351	0	0
T8	35020	698	0	0
T9	20118	20	0	0
T10	10290	146	0	0
T11	6861	528	0	0
T12	11956	250	0	0
T13	253233	77	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	214812	0	0
T1	127280	371	0	0
T2	1625	14	0	0
T3	211715	478	0	0
T7	24521	38	0	0
T8	35020	61	0	0
T9	20118	537	0	0
T10	10290	16	0	0
T11	6861	56	0	0
T12	11956	17	0	0
T13	253233	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	214812	0	0
T1	127280	371	0	0
T2	1625	14	0	0
T3	211715	478	0	0
T7	24521	38	0	0
T8	35020	61	0	0
T9	20118	537	0	0
T10	10290	16	0	0
T11	6861	56	0	0
T12	11956	17	0	0
T13	253233	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	1377400	0	0
T1	127280	7299	0	0
T2	1625	14	0	0
T3	211715	2555	0	0
T7	24521	53	0	0
T8	35020	86	0	0
T9	20118	4483	0	0
T10	10290	16	0	0
T11	6861	112	0	0
T12	11956	17	0	0
T13	253233	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	214812	0	0
T1	127280	371	0	0
T2	1625	14	0	0
T3	211715	478	0	0
T7	24521	38	0	0
T8	35020	61	0	0
T9	20118	537	0	0
T10	10290	16	0	0
T11	6861	56	0	0
T12	11956	17	0	0
T13	253233	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	215109	0	0
GntImpliesValid_A	416917799	215109	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	215109	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	4613655	0	0
ReadyAndValidImplyGrant_A	416917799	215109	0	0
ReqAndReadyImplyGrant_A	416917799	215109	0	0
ReqImpliesValid_A	416917799	1128255	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	215109	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	215109	0	0
T2	1625	3	0	0
T3	211715	496	0	0
T7	24521	54	0	0
T8	35020	50	0	0
T9	20118	476	0	0
T10	10290	15	0	0
T11	6861	71	0	0
T12	11956	13	0	0
T13	253233	12	0	0
T14	2902	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	215109	0	0
T2	1625	3	0	0
T3	211715	496	0	0
T7	24521	54	0	0
T8	35020	50	0	0
T9	20118	476	0	0
T10	10290	15	0	0
T11	6861	71	0	0
T12	11956	13	0	0
T13	253233	12	0	0
T14	2902	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	215109	0	0
T2	1625	3	0	0
T3	211715	496	0	0
T7	24521	54	0	0
T8	35020	50	0	0
T9	20118	476	0	0
T10	10290	15	0	0
T11	6861	71	0	0
T12	11956	13	0	0
T13	253233	12	0	0
T14	2902	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	4613655	0	0
T2	1625	14	0	0
T3	211715	9661	0	0
T7	24521	1359	0	0
T8	35020	2211	0	0
T9	20118	65	0	0
T10	10290	213	0	0
T11	6861	355	0	0
T12	11956	173	0	0
T13	253233	107	0	0
T14	2902	96	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	215109	0	0
T2	1625	3	0	0
T3	211715	496	0	0
T7	24521	54	0	0
T8	35020	50	0	0
T9	20118	476	0	0
T10	10290	15	0	0
T11	6861	71	0	0
T12	11956	13	0	0
T13	253233	12	0	0
T14	2902	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	215109	0	0
T2	1625	3	0	0
T3	211715	496	0	0
T7	24521	54	0	0
T8	35020	50	0	0
T9	20118	476	0	0
T10	10290	15	0	0
T11	6861	71	0	0
T12	11956	13	0	0
T13	253233	12	0	0
T14	2902	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	1128255	0	0
T2	1625	3	0	0
T3	211715	865	0	0
T7	24521	137	0	0
T8	35020	198	0	0
T9	20118	3371	0	0
T10	10290	15	0	0
T11	6861	114	0	0
T12	11956	23	0	0
T13	253233	21	0	0
T14	2902	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	215109	0	0
T2	1625	3	0	0
T3	211715	496	0	0
T7	24521	54	0	0
T8	35020	50	0	0
T9	20118	476	0	0
T10	10290	15	0	0
T11	6861	71	0	0
T12	11956	13	0	0
T13	253233	12	0	0
T14	2902	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	210349	0	0
GntImpliesValid_A	416917799	210349	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	210349	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	4896056	0	0
ReadyAndValidImplyGrant_A	416917799	210349	0	0
ReqAndReadyImplyGrant_A	416917799	210349	0	0
ReqImpliesValid_A	416917799	1140049	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	210349	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210349	0	0
T1	127280	346	0	0
T2	1625	12	0	0
T3	211715	480	0	0
T7	24521	50	0	0
T8	35020	53	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	61	0	0
T12	11956	16	0	0
T13	253233	15	0	0
T14	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210349	0	0
T1	127280	346	0	0
T2	1625	12	0	0
T3	211715	480	0	0
T7	24521	50	0	0
T8	35020	53	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	61	0	0
T12	11956	16	0	0
T13	253233	15	0	0
T14	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210349	0	0
T1	127280	346	0	0
T2	1625	12	0	0
T3	211715	480	0	0
T7	24521	50	0	0
T8	35020	53	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	61	0	0
T12	11956	16	0	0
T13	253233	15	0	0
T14	0	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	4896056	0	0
T1	127280	551	0	0
T2	1625	59	0	0
T3	211715	7193	0	0
T7	24521	475	0	0
T8	35020	601	0	0
T9	20118	0	0	0
T10	10290	163	0	0
T11	6861	515	0	0
T12	11956	418	0	0
T13	253233	134	0	0
T14	0	115	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210349	0	0
T1	127280	346	0	0
T2	1625	12	0	0
T3	211715	480	0	0
T7	24521	50	0	0
T8	35020	53	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	61	0	0
T12	11956	16	0	0
T13	253233	15	0	0
T14	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210349	0	0
T1	127280	346	0	0
T2	1625	12	0	0
T3	211715	480	0	0
T7	24521	50	0	0
T8	35020	53	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	61	0	0
T12	11956	16	0	0
T13	253233	15	0	0
T14	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	1140049	0	0
T1	127280	5011	0	0
T2	1625	16	0	0
T3	211715	846	0	0
T7	24521	58	0	0
T8	35020	70	0	0
T9	20118	0	0	0
T10	10290	28	0	0
T11	6861	114	0	0
T12	11956	64	0	0
T13	253233	15	0	0
T14	0	60	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210349	0	0
T1	127280	346	0	0
T2	1625	12	0	0
T3	211715	480	0	0
T7	24521	50	0	0
T8	35020	53	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	61	0	0
T12	11956	16	0	0
T13	253233	15	0	0
T14	0	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	226502	0	0
GntImpliesValid_A	416917799	226502	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	226502	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2856925	0	0
ReadyAndValidImplyGrant_A	416917799	226502	0	0
ReqAndReadyImplyGrant_A	416917799	226502	0	0
ReqImpliesValid_A	416917799	664359	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	226502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	226502	0	0
T1	127280	484	0	0
T2	1625	11	0	0
T3	211715	495	0	0
T7	24521	52	0	0
T8	35020	39	0	0
T9	20118	0	0	0
T10	10290	9	0	0
T11	6861	63	0	0
T12	11956	12	0	0
T13	253233	19	0	0
T14	0	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	226502	0	0
T1	127280	484	0	0
T2	1625	11	0	0
T3	211715	495	0	0
T7	24521	52	0	0
T8	35020	39	0	0
T9	20118	0	0	0
T10	10290	9	0	0
T11	6861	63	0	0
T12	11956	12	0	0
T13	253233	19	0	0
T14	0	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	226502	0	0
T1	127280	484	0	0
T2	1625	11	0	0
T3	211715	495	0	0
T7	24521	52	0	0
T8	35020	39	0	0
T9	20118	0	0	0
T10	10290	9	0	0
T11	6861	63	0	0
T12	11956	12	0	0
T13	253233	19	0	0
T14	0	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2856925	0	0
T1	127280	1013	0	0
T2	1625	11	0	0
T3	211715	3891	0	0
T7	24521	435	0	0
T8	35020	334	0	0
T9	20118	1	0	0
T10	10290	50	0	0
T11	6861	59	0	0
T12	11956	109	0	0
T13	253233	71	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	226502	0	0
T1	127280	484	0	0
T2	1625	11	0	0
T3	211715	495	0	0
T7	24521	52	0	0
T8	35020	39	0	0
T9	20118	0	0	0
T10	10290	9	0	0
T11	6861	63	0	0
T12	11956	12	0	0
T13	253233	19	0	0
T14	0	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	226502	0	0
T1	127280	484	0	0
T2	1625	11	0	0
T3	211715	495	0	0
T7	24521	52	0	0
T8	35020	39	0	0
T9	20118	0	0	0
T10	10290	9	0	0
T11	6861	63	0	0
T12	11956	12	0	0
T13	253233	19	0	0
T14	0	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	664359	0	0
T1	127280	4569	0	0
T2	1625	12	0	0
T3	211715	583	0	0
T7	24521	74	0	0
T8	35020	39	0	0
T9	20118	0	0	0
T10	10290	9	0	0
T11	6861	68	0	0
T12	11956	13	0	0
T13	253233	22	0	0
T14	0	35	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	226502	0	0
T1	127280	484	0	0
T2	1625	11	0	0
T3	211715	495	0	0
T7	24521	52	0	0
T8	35020	39	0	0
T9	20118	0	0	0
T10	10290	9	0	0
T11	6861	63	0	0
T12	11956	12	0	0
T13	253233	19	0	0
T14	0	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	210736	0	0
GntImpliesValid_A	416917799	210736	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	210736	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2811494	0	0
ReadyAndValidImplyGrant_A	416917799	210736	0	0
ReqAndReadyImplyGrant_A	416917799	210736	0	0
ReqImpliesValid_A	416917799	552698	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	210736	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210736	0	0
T2	1625	12	0	0
T3	211715	459	0	0
T7	24521	54	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	19	0	0
T11	6861	58	0	0
T12	11956	20	0	0
T13	253233	13	0	0
T14	2902	33	0	0
T15	0	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210736	0	0
T2	1625	12	0	0
T3	211715	459	0	0
T7	24521	54	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	19	0	0
T11	6861	58	0	0
T12	11956	20	0	0
T13	253233	13	0	0
T14	2902	33	0	0
T15	0	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210736	0	0
T2	1625	12	0	0
T3	211715	459	0	0
T7	24521	54	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	19	0	0
T11	6861	58	0	0
T12	11956	20	0	0
T13	253233	13	0	0
T14	2902	33	0	0
T15	0	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2811494	0	0
T1	127280	1	0	0
T2	1625	13	0	0
T3	211715	3500	0	0
T7	24521	377	0	0
T8	35020	338	0	0
T9	20118	1	0	0
T10	10290	131	0	0
T11	6861	56	0	0
T12	11956	99	0	0
T13	253233	61	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210736	0	0
T2	1625	12	0	0
T3	211715	459	0	0
T7	24521	54	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	19	0	0
T11	6861	58	0	0
T12	11956	20	0	0
T13	253233	13	0	0
T14	2902	33	0	0
T15	0	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210736	0	0
T2	1625	12	0	0
T3	211715	459	0	0
T7	24521	54	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	19	0	0
T11	6861	58	0	0
T12	11956	20	0	0
T13	253233	13	0	0
T14	2902	33	0	0
T15	0	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	552698	0	0
T2	1625	12	0	0
T3	211715	554	0	0
T7	24521	91	0	0
T8	35020	49	0	0
T9	20118	0	0	0
T10	10290	23	0	0
T11	6861	61	0	0
T12	11956	52	0	0
T13	253233	13	0	0
T14	2902	34	0	0
T15	0	36	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210736	0	0
T2	1625	12	0	0
T3	211715	459	0	0
T7	24521	54	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	19	0	0
T11	6861	58	0	0
T12	11956	20	0	0
T13	253233	13	0	0
T14	2902	33	0	0
T15	0	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	210342	0	0
GntImpliesValid_A	416917799	210342	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	210342	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2784153	0	0
ReadyAndValidImplyGrant_A	416917799	210342	0	0
ReqAndReadyImplyGrant_A	416917799	210342	0	0
ReqImpliesValid_A	416917799	584405	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	210342	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210342	0	0
T2	1625	18	0	0
T3	211715	500	0	0
T7	24521	43	0	0
T8	35020	55	0	0
T9	20118	521	0	0
T10	10290	10	0	0
T11	6861	63	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	2902	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210342	0	0
T2	1625	18	0	0
T3	211715	500	0	0
T7	24521	43	0	0
T8	35020	55	0	0
T9	20118	521	0	0
T10	10290	10	0	0
T11	6861	63	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	2902	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210342	0	0
T2	1625	18	0	0
T3	211715	500	0	0
T7	24521	43	0	0
T8	35020	55	0	0
T9	20118	521	0	0
T10	10290	10	0	0
T11	6861	63	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	2902	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2784153	0	0
T1	127280	1	0	0
T2	1625	17	0	0
T3	211715	3676	0	0
T7	24521	321	0	0
T8	35020	364	0	0
T9	20118	2	0	0
T10	10290	64	0	0
T11	6861	63	0	0
T12	11956	98	0	0
T13	253233	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210342	0	0
T2	1625	18	0	0
T3	211715	500	0	0
T7	24521	43	0	0
T8	35020	55	0	0
T9	20118	521	0	0
T10	10290	10	0	0
T11	6861	63	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	2902	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210342	0	0
T2	1625	18	0	0
T3	211715	500	0	0
T7	24521	43	0	0
T8	35020	55	0	0
T9	20118	521	0	0
T10	10290	10	0	0
T11	6861	63	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	2902	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	584405	0	0
T2	1625	20	0	0
T3	211715	589	0	0
T7	24521	48	0	0
T8	35020	106	0	0
T9	20118	1041	0	0
T10	10290	16	0	0
T11	6861	64	0	0
T12	11956	24	0	0
T13	253233	9	0	0
T14	2902	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	210342	0	0
T2	1625	18	0	0
T3	211715	500	0	0
T7	24521	43	0	0
T8	35020	55	0	0
T9	20118	521	0	0
T10	10290	10	0	0
T11	6861	63	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	2902	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	224584	0	0
GntImpliesValid_A	416917799	224584	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	224584	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2819079	0	0
ReadyAndValidImplyGrant_A	416917799	224584	0	0
ReqAndReadyImplyGrant_A	416917799	224584	0	0
ReqImpliesValid_A	416917799	637279	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	224584	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	224584	0	0
T1	127280	1553	0	0
T2	1625	13	0	0
T3	211715	473	0	0
T7	24521	47	0	0
T8	35020	59	0	0
T9	20118	518	0	0
T10	10290	23	0	0
T11	6861	60	0	0
T12	11956	16	0	0
T13	253233	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	224584	0	0
T1	127280	1553	0	0
T2	1625	13	0	0
T3	211715	473	0	0
T7	24521	47	0	0
T8	35020	59	0	0
T9	20118	518	0	0
T10	10290	23	0	0
T11	6861	60	0	0
T12	11956	16	0	0
T13	253233	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	224584	0	0
T1	127280	1553	0	0
T2	1625	13	0	0
T3	211715	473	0	0
T7	24521	47	0	0
T8	35020	59	0	0
T9	20118	518	0	0
T10	10290	23	0	0
T11	6861	60	0	0
T12	11956	16	0	0
T13	253233	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2819079	0	0
T1	127280	1981	0	0
T2	1625	13	0	0
T3	211715	3645	0	0
T7	24521	328	0	0
T8	35020	486	0	0
T9	20118	3	0	0
T10	10290	159	0	0
T11	6861	56	0	0
T12	11956	147	0	0
T13	253233	78	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	224584	0	0
T1	127280	1553	0	0
T2	1625	13	0	0
T3	211715	473	0	0
T7	24521	47	0	0
T8	35020	59	0	0
T9	20118	518	0	0
T10	10290	23	0	0
T11	6861	60	0	0
T12	11956	16	0	0
T13	253233	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	224584	0	0
T1	127280	1553	0	0
T2	1625	13	0	0
T3	211715	473	0	0
T7	24521	47	0	0
T8	35020	59	0	0
T9	20118	518	0	0
T10	10290	23	0	0
T11	6861	60	0	0
T12	11956	16	0	0
T13	253233	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	637279	0	0
T1	127280	15558	0	0
T2	1625	14	0	0
T3	211715	608	0	0
T7	24521	60	0	0
T8	35020	65	0	0
T9	20118	1034	0	0
T10	10290	53	0	0
T11	6861	65	0	0
T12	11956	16	0	0
T13	253233	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	224584	0	0
T1	127280	1553	0	0
T2	1625	13	0	0
T3	211715	473	0	0
T7	24521	47	0	0
T8	35020	59	0	0
T9	20118	518	0	0
T10	10290	23	0	0
T11	6861	60	0	0
T12	11956	16	0	0
T13	253233	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	205892	0	0
GntImpliesValid_A	416917799	205892	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	205892	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2768667	0	0
ReadyAndValidImplyGrant_A	416917799	205892	0	0
ReqAndReadyImplyGrant_A	416917799	205892	0	0
ReqImpliesValid_A	416917799	538169	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	205892	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	205892	0	0
T2	1625	14	0	0
T3	211715	489	0	0
T7	24521	54	0	0
T8	35020	51	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	76	0	0
T12	11956	11	0	0
T13	253233	10	0	0
T14	2902	28	0	0
T15	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	205892	0	0
T2	1625	14	0	0
T3	211715	489	0	0
T7	24521	54	0	0
T8	35020	51	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	76	0	0
T12	11956	11	0	0
T13	253233	10	0	0
T14	2902	28	0	0
T15	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	205892	0	0
T2	1625	14	0	0
T3	211715	489	0	0
T7	24521	54	0	0
T8	35020	51	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	76	0	0
T12	11956	11	0	0
T13	253233	10	0	0
T14	2902	28	0	0
T15	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2768667	0	0
T1	127280	1	0	0
T2	1625	14	0	0
T3	211715	3584	0	0
T7	24521	382	0	0
T8	35020	358	0	0
T9	20118	1	0	0
T10	10290	125	0	0
T11	6861	75	0	0
T12	11956	106	0	0
T13	253233	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	205892	0	0
T2	1625	14	0	0
T3	211715	489	0	0
T7	24521	54	0	0
T8	35020	51	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	76	0	0
T12	11956	11	0	0
T13	253233	10	0	0
T14	2902	28	0	0
T15	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	205892	0	0
T2	1625	14	0	0
T3	211715	489	0	0
T7	24521	54	0	0
T8	35020	51	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	76	0	0
T12	11956	11	0	0
T13	253233	10	0	0
T14	2902	28	0	0
T15	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	538169	0	0
T2	1625	15	0	0
T3	211715	602	0	0
T7	24521	72	0	0
T8	35020	51	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	78	0	0
T12	11956	11	0	0
T13	253233	10	0	0
T14	2902	28	0	0
T15	0	34	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	205892	0	0
T2	1625	14	0	0
T3	211715	489	0	0
T7	24521	54	0	0
T8	35020	51	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	76	0	0
T12	11956	11	0	0
T13	253233	10	0	0
T14	2902	28	0	0
T15	0	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	221506	0	0
GntImpliesValid_A	416917799	221506	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	221506	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2871886	0	0
ReadyAndValidImplyGrant_A	416917799	221506	0	0
ReqAndReadyImplyGrant_A	416917799	221506	0	0
ReqImpliesValid_A	416917799	610002	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	221506	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221506	0	0
T1	127280	1603	0	0
T2	1625	14	0	0
T3	211715	490	0	0
T7	24521	56	0	0
T8	35020	297	0	0
T9	20118	0	0	0
T10	10290	7	0	0
T11	6861	51	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	0	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221506	0	0
T1	127280	1603	0	0
T2	1625	14	0	0
T3	211715	490	0	0
T7	24521	56	0	0
T8	35020	297	0	0
T9	20118	0	0	0
T10	10290	7	0	0
T11	6861	51	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	0	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221506	0	0
T1	127280	1603	0	0
T2	1625	14	0	0
T3	211715	490	0	0
T7	24521	56	0	0
T8	35020	297	0	0
T9	20118	0	0	0
T10	10290	7	0	0
T11	6861	51	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	0	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2871886	0	0
T1	127280	2093	0	0
T2	1625	15	0	0
T3	211715	3719	0	0
T7	24521	383	0	0
T8	35020	2139	0	0
T9	20118	1	0	0
T10	10290	58	0	0
T11	6861	50	0	0
T12	11956	97	0	0
T13	253233	51	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221506	0	0
T1	127280	1603	0	0
T2	1625	14	0	0
T3	211715	490	0	0
T7	24521	56	0	0
T8	35020	297	0	0
T9	20118	0	0	0
T10	10290	7	0	0
T11	6861	51	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	0	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221506	0	0
T1	127280	1603	0	0
T2	1625	14	0	0
T3	211715	490	0	0
T7	24521	56	0	0
T8	35020	297	0	0
T9	20118	0	0	0
T10	10290	7	0	0
T11	6861	51	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	0	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	610002	0	0
T1	127280	16115	0	0
T2	1625	14	0	0
T3	211715	590	0	0
T7	24521	91	0	0
T8	35020	597	0	0
T9	20118	0	0	0
T10	10290	8	0	0
T11	6861	53	0	0
T12	11956	16	0	0
T13	253233	9	0	0
T14	0	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221506	0	0
T1	127280	1603	0	0
T2	1625	14	0	0
T3	211715	490	0	0
T7	24521	56	0	0
T8	35020	297	0	0
T9	20118	0	0	0
T10	10290	7	0	0
T11	6861	51	0	0
T12	11956	15	0	0
T13	253233	9	0	0
T14	0	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	221787	0	0
GntImpliesValid_A	416917799	221787	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	221787	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2859657	0	0
ReadyAndValidImplyGrant_A	416917799	221787	0	0
ReqAndReadyImplyGrant_A	416917799	221787	0	0
ReqImpliesValid_A	416917799	620645	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	221787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221787	0	0
T1	127280	547	0	0
T2	1625	8	0	0
T3	211715	510	0	0
T7	24521	47	0	0
T8	35020	31	0	0
T9	20118	0	0	0
T10	10290	11	0	0
T11	6861	66	0	0
T12	11956	10	0	0
T13	253233	18	0	0
T14	0	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221787	0	0
T1	127280	547	0	0
T2	1625	8	0	0
T3	211715	510	0	0
T7	24521	47	0	0
T8	35020	31	0	0
T9	20118	0	0	0
T10	10290	11	0	0
T11	6861	66	0	0
T12	11956	10	0	0
T13	253233	18	0	0
T14	0	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221787	0	0
T1	127280	547	0	0
T2	1625	8	0	0
T3	211715	510	0	0
T7	24521	47	0	0
T8	35020	31	0	0
T9	20118	0	0	0
T10	10290	11	0	0
T11	6861	66	0	0
T12	11956	10	0	0
T13	253233	18	0	0
T14	0	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2859657	0	0
T1	127280	1394	0	0
T2	1625	9	0	0
T3	211715	3855	0	0
T7	24521	311	0	0
T8	35020	234	0	0
T9	20118	1	0	0
T10	10290	57	0	0
T11	6861	66	0	0
T12	11956	79	0	0
T13	253233	71	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221787	0	0
T1	127280	547	0	0
T2	1625	8	0	0
T3	211715	510	0	0
T7	24521	47	0	0
T8	35020	31	0	0
T9	20118	0	0	0
T10	10290	11	0	0
T11	6861	66	0	0
T12	11956	10	0	0
T13	253233	18	0	0
T14	0	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221787	0	0
T1	127280	547	0	0
T2	1625	8	0	0
T3	211715	510	0	0
T7	24521	47	0	0
T8	35020	31	0	0
T9	20118	0	0	0
T10	10290	11	0	0
T11	6861	66	0	0
T12	11956	10	0	0
T13	253233	18	0	0
T14	0	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	620645	0	0
T1	127280	2094	0	0
T2	1625	8	0	0
T3	211715	622	0	0
T7	24521	65	0	0
T8	35020	31	0	0
T9	20118	0	0	0
T10	10290	11	0	0
T11	6861	67	0	0
T12	11956	13	0	0
T13	253233	18	0	0
T14	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	221787	0	0
T1	127280	547	0	0
T2	1625	8	0	0
T3	211715	510	0	0
T7	24521	47	0	0
T8	35020	31	0	0
T9	20118	0	0	0
T10	10290	11	0	0
T11	6861	66	0	0
T12	11956	10	0	0
T13	253233	18	0	0
T14	0	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T11
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	222569	0	0
GntImpliesValid_A	416917799	222569	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	222569	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2830737	0	0
ReadyAndValidImplyGrant_A	416917799	222569	0	0
ReqAndReadyImplyGrant_A	416917799	222569	0	0
ReqImpliesValid_A	416917799	601142	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	222569	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	222569	0	0
T2	1625	13	0	0
T3	211715	505	0	0
T7	24521	38	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	10	0	0
T11	6861	84	0	0
T12	11956	10	0	0
T13	253233	14	0	0
T14	2902	38	0	0
T15	0	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	222569	0	0
T2	1625	13	0	0
T3	211715	505	0	0
T7	24521	38	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	10	0	0
T11	6861	84	0	0
T12	11956	10	0	0
T13	253233	14	0	0
T14	2902	38	0	0
T15	0	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	222569	0	0
T2	1625	13	0	0
T3	211715	505	0	0
T7	24521	38	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	10	0	0
T11	6861	84	0	0
T12	11956	10	0	0
T13	253233	14	0	0
T14	2902	38	0	0
T15	0	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2830737	0	0
T1	127280	1	0	0
T2	1625	14	0	0
T3	211715	3890	0	0
T7	24521	320	0	0
T8	35020	302	0	0
T9	20118	1	0	0
T10	10290	74	0	0
T11	6861	84	0	0
T12	11956	91	0	0
T13	253233	58	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	222569	0	0
T2	1625	13	0	0
T3	211715	505	0	0
T7	24521	38	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	10	0	0
T11	6861	84	0	0
T12	11956	10	0	0
T13	253233	14	0	0
T14	2902	38	0	0
T15	0	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	222569	0	0
T2	1625	13	0	0
T3	211715	505	0	0
T7	24521	38	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	10	0	0
T11	6861	84	0	0
T12	11956	10	0	0
T13	253233	14	0	0
T14	2902	38	0	0
T15	0	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	601142	0	0
T2	1625	13	0	0
T3	211715	634	0	0
T7	24521	41	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	10	0	0
T11	6861	85	0	0
T12	11956	21	0	0
T13	253233	19	0	0
T14	2902	38	0	0
T15	0	59	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	222569	0	0
T2	1625	13	0	0
T3	211715	505	0	0
T7	24521	38	0	0
T8	35020	41	0	0
T9	20118	0	0	0
T10	10290	10	0	0
T11	6861	84	0	0
T12	11956	10	0	0
T13	253233	14	0	0
T14	2902	38	0	0
T15	0	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	228032	0	0
GntImpliesValid_A	416917799	228032	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	228032	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2881922	0	0
ReadyAndValidImplyGrant_A	416917799	228032	0	0
ReqAndReadyImplyGrant_A	416917799	228032	0	0
ReqImpliesValid_A	416917799	535614	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	228032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	228032	0	0
T2	1625	10	0	0
T3	211715	551	0	0
T7	24521	74	0	0
T8	35020	57	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	106	0	0
T12	11956	12	0	0
T13	253233	16	0	0
T14	2902	67	0	0
T15	0	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	228032	0	0
T2	1625	10	0	0
T3	211715	551	0	0
T7	24521	74	0	0
T8	35020	57	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	106	0	0
T12	11956	12	0	0
T13	253233	16	0	0
T14	2902	67	0	0
T15	0	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	228032	0	0
T2	1625	10	0	0
T3	211715	551	0	0
T7	24521	74	0	0
T8	35020	57	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	106	0	0
T12	11956	12	0	0
T13	253233	16	0	0
T14	2902	67	0	0
T15	0	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2881922	0	0
T1	127280	1	0	0
T2	1625	10	0	0
T3	211715	4148	0	0
T7	24521	545	0	0
T8	35020	537	0	0
T9	20118	1	0	0
T10	10290	117	0	0
T11	6861	105	0	0
T12	11956	75	0	0
T13	253233	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	228032	0	0
T2	1625	10	0	0
T3	211715	551	0	0
T7	24521	74	0	0
T8	35020	57	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	106	0	0
T12	11956	12	0	0
T13	253233	16	0	0
T14	2902	67	0	0
T15	0	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	228032	0	0
T2	1625	10	0	0
T3	211715	551	0	0
T7	24521	74	0	0
T8	35020	57	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	106	0	0
T12	11956	12	0	0
T13	253233	16	0	0
T14	2902	67	0	0
T15	0	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	535614	0	0
T2	1625	11	0	0
T3	211715	667	0	0
T7	24521	114	0	0
T8	35020	62	0	0
T9	20118	0	0	0
T10	10290	38	0	0
T11	6861	108	0	0
T12	11956	12	0	0
T13	253233	24	0	0
T14	2902	72	0	0
T15	0	60	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	228032	0	0
T2	1625	10	0	0
T3	211715	551	0	0
T7	24521	74	0	0
T8	35020	57	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	106	0	0
T12	11956	12	0	0
T13	253233	16	0	0
T14	2902	67	0	0
T15	0	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	216180	0	0
GntImpliesValid_A	416917799	216180	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	216180	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2871717	0	0
ReadyAndValidImplyGrant_A	416917799	216180	0	0
ReqAndReadyImplyGrant_A	416917799	216180	0	0
ReqImpliesValid_A	416917799	571518	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	216180	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	216180	0	0
T1	127280	568	0	0
T2	1625	10	0	0
T3	211715	509	0	0
T7	24521	36	0	0
T8	35020	58	0	0
T9	20118	471	0	0
T10	10290	13	0	0
T11	6861	63	0	0
T12	11956	8	0	0
T13	253233	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	216180	0	0
T1	127280	568	0	0
T2	1625	10	0	0
T3	211715	509	0	0
T7	24521	36	0	0
T8	35020	58	0	0
T9	20118	471	0	0
T10	10290	13	0	0
T11	6861	63	0	0
T12	11956	8	0	0
T13	253233	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	216180	0	0
T1	127280	568	0	0
T2	1625	10	0	0
T3	211715	509	0	0
T7	24521	36	0	0
T8	35020	58	0	0
T9	20118	471	0	0
T10	10290	13	0	0
T11	6861	63	0	0
T12	11956	8	0	0
T13	253233	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2871717	0	0
T1	127280	1453	0	0
T2	1625	11	0	0
T3	211715	3804	0	0
T7	24521	249	0	0
T8	35020	450	0	0
T9	20118	4	0	0
T10	10290	98	0	0
T11	6861	62	0	0
T12	11956	59	0	0
T13	253233	88	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	216180	0	0
T1	127280	568	0	0
T2	1625	10	0	0
T3	211715	509	0	0
T7	24521	36	0	0
T8	35020	58	0	0
T9	20118	471	0	0
T10	10290	13	0	0
T11	6861	63	0	0
T12	11956	8	0	0
T13	253233	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	216180	0	0
T1	127280	568	0	0
T2	1625	10	0	0
T3	211715	509	0	0
T7	24521	36	0	0
T8	35020	58	0	0
T9	20118	471	0	0
T10	10290	13	0	0
T11	6861	63	0	0
T12	11956	8	0	0
T13	253233	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	571518	0	0
T1	127280	2379	0	0
T2	1625	10	0	0
T3	211715	627	0	0
T7	24521	36	0	0
T8	35020	62	0	0
T9	20118	939	0	0
T10	10290	18	0	0
T11	6861	65	0	0
T12	11956	8	0	0
T13	253233	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	216180	0	0
T1	127280	568	0	0
T2	1625	10	0	0
T3	211715	509	0	0
T7	24521	36	0	0
T8	35020	58	0	0
T9	20118	471	0	0
T10	10290	13	0	0
T11	6861	63	0	0
T12	11956	8	0	0
T13	253233	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	207004	0	0
GntImpliesValid_A	416917799	207004	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	207004	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2797542	0	0
ReadyAndValidImplyGrant_A	416917799	207004	0	0
ReqAndReadyImplyGrant_A	416917799	207004	0	0
ReqImpliesValid_A	416917799	554892	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	207004	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207004	0	0
T1	127280	492	0	0
T2	1625	5	0	0
T3	211715	467	0	0
T7	24521	51	0	0
T8	35020	37	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	52	0	0
T12	11956	20	0	0
T13	253233	14	0	0
T14	0	29	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207004	0	0
T1	127280	492	0	0
T2	1625	5	0	0
T3	211715	467	0	0
T7	24521	51	0	0
T8	35020	37	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	52	0	0
T12	11956	20	0	0
T13	253233	14	0	0
T14	0	29	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207004	0	0
T1	127280	492	0	0
T2	1625	5	0	0
T3	211715	467	0	0
T7	24521	51	0	0
T8	35020	37	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	52	0	0
T12	11956	20	0	0
T13	253233	14	0	0
T14	0	29	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2797542	0	0
T1	127280	296	0	0
T2	1625	6	0	0
T3	211715	3644	0	0
T7	24521	364	0	0
T8	35020	281	0	0
T9	20118	1	0	0
T10	10290	106	0	0
T11	6861	48	0	0
T12	11956	143	0	0
T13	253233	68	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207004	0	0
T1	127280	492	0	0
T2	1625	5	0	0
T3	211715	467	0	0
T7	24521	51	0	0
T8	35020	37	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	52	0	0
T12	11956	20	0	0
T13	253233	14	0	0
T14	0	29	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207004	0	0
T1	127280	492	0	0
T2	1625	5	0	0
T3	211715	467	0	0
T7	24521	51	0	0
T8	35020	37	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	52	0	0
T12	11956	20	0	0
T13	253233	14	0	0
T14	0	29	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	554892	0	0
T1	127280	5561	0	0
T2	1625	5	0	0
T3	211715	538	0	0
T7	24521	61	0	0
T8	35020	39	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	57	0	0
T12	11956	41	0	0
T13	253233	17	0	0
T14	0	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	207004	0	0
T1	127280	492	0	0
T2	1625	5	0	0
T3	211715	467	0	0
T7	24521	51	0	0
T8	35020	37	0	0
T9	20118	0	0	0
T10	10290	16	0	0
T11	6861	52	0	0
T12	11956	20	0	0
T13	253233	14	0	0
T14	0	29	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	201035	0	0
GntImpliesValid_A	416917799	201035	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	201035	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2840290	0	0
ReadyAndValidImplyGrant_A	416917799	201035	0	0
ReqAndReadyImplyGrant_A	416917799	201035	0	0
ReqImpliesValid_A	416917799	534914	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	201035	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	201035	0	0
T2	1625	10	0	0
T3	211715	521	0	0
T7	24521	46	0	0
T8	35020	44	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	59	0	0
T12	11956	14	0	0
T13	253233	8	0	0
T14	2902	28	0	0
T15	0	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	201035	0	0
T2	1625	10	0	0
T3	211715	521	0	0
T7	24521	46	0	0
T8	35020	44	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	59	0	0
T12	11956	14	0	0
T13	253233	8	0	0
T14	2902	28	0	0
T15	0	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	201035	0	0
T2	1625	10	0	0
T3	211715	521	0	0
T7	24521	46	0	0
T8	35020	44	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	59	0	0
T12	11956	14	0	0
T13	253233	8	0	0
T14	2902	28	0	0
T15	0	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2840290	0	0
T1	127280	1	0	0
T2	1625	11	0	0
T3	211715	4228	0	0
T7	24521	301	0	0
T8	35020	333	0	0
T9	20118	1	0	0
T10	10290	127	0	0
T11	6861	58	0	0
T12	11956	98	0	0
T13	253233	33	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	201035	0	0
T2	1625	10	0	0
T3	211715	521	0	0
T7	24521	46	0	0
T8	35020	44	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	59	0	0
T12	11956	14	0	0
T13	253233	8	0	0
T14	2902	28	0	0
T15	0	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	201035	0	0
T2	1625	10	0	0
T3	211715	521	0	0
T7	24521	46	0	0
T8	35020	44	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	59	0	0
T12	11956	14	0	0
T13	253233	8	0	0
T14	2902	28	0	0
T15	0	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	534914	0	0
T2	1625	10	0	0
T3	211715	569	0	0
T7	24521	54	0	0
T8	35020	55	0	0
T9	20118	0	0	0
T10	10290	22	0	0
T11	6861	61	0	0
T12	11956	22	0	0
T13	253233	14	0	0
T14	2902	28	0	0
T15	0	59	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	201035	0	0
T2	1625	10	0	0
T3	211715	521	0	0
T7	24521	46	0	0
T8	35020	44	0	0
T9	20118	0	0	0
T10	10290	14	0	0
T11	6861	59	0	0
T12	11956	14	0	0
T13	253233	8	0	0
T14	2902	28	0	0
T15	0	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	211488	0	0
GntImpliesValid_A	416917799	211488	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	211488	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2789291	0	0
ReadyAndValidImplyGrant_A	416917799	211488	0	0
ReqAndReadyImplyGrant_A	416917799	211488	0	0
ReqImpliesValid_A	416917799	571184	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	211488	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	211488	0	0
T1	127280	560	0	0
T2	1625	14	0	0
T3	211715	487	0	0
T7	24521	51	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	53	0	0
T12	11956	12	0	0
T13	253233	9	0	0
T14	0	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	211488	0	0
T1	127280	560	0	0
T2	1625	14	0	0
T3	211715	487	0	0
T7	24521	51	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	53	0	0
T12	11956	12	0	0
T13	253233	9	0	0
T14	0	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	211488	0	0
T1	127280	560	0	0
T2	1625	14	0	0
T3	211715	487	0	0
T7	24521	51	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	53	0	0
T12	11956	12	0	0
T13	253233	9	0	0
T14	0	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2789291	0	0
T1	127280	1414	0	0
T2	1625	14	0	0
T3	211715	3775	0	0
T7	24521	421	0	0
T8	35020	367	0	0
T9	20118	1	0	0
T10	10290	85	0	0
T11	6861	52	0	0
T12	11956	88	0	0
T13	253233	23	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	211488	0	0
T1	127280	560	0	0
T2	1625	14	0	0
T3	211715	487	0	0
T7	24521	51	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	53	0	0
T12	11956	12	0	0
T13	253233	9	0	0
T14	0	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	211488	0	0
T1	127280	560	0	0
T2	1625	14	0	0
T3	211715	487	0	0
T7	24521	51	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	53	0	0
T12	11956	12	0	0
T13	253233	9	0	0
T14	0	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	571184	0	0
T1	127280	2150	0	0
T2	1625	15	0	0
T3	211715	604	0	0
T7	24521	60	0	0
T8	35020	66	0	0
T9	20118	0	0	0
T10	10290	28	0	0
T11	6861	55	0	0
T12	11956	12	0	0
T13	253233	9	0	0
T14	0	36	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	211488	0	0
T1	127280	560	0	0
T2	1625	14	0	0
T3	211715	487	0	0
T7	24521	51	0	0
T8	35020	54	0	0
T9	20118	0	0	0
T10	10290	13	0	0
T11	6861	53	0	0
T12	11956	12	0	0
T13	253233	9	0	0
T14	0	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	223918	0	0
GntImpliesValid_A	416917799	223918	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	223918	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	2851002	0	0
ReadyAndValidImplyGrant_A	416917799	223918	0	0
ReqAndReadyImplyGrant_A	416917799	223918	0	0
ReqImpliesValid_A	416917799	630040	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	0	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	223918	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	223918	0	0
T2	1625	10	0	0
T3	211715	490	0	0
T7	24521	45	0	0
T8	35020	45	0	0
T9	20118	489	0	0
T10	10290	19	0	0
T11	6861	65	0	0
T12	11956	17	0	0
T13	253233	7	0	0
T14	2902	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	223918	0	0
T2	1625	10	0	0
T3	211715	490	0	0
T7	24521	45	0	0
T8	35020	45	0	0
T9	20118	489	0	0
T10	10290	19	0	0
T11	6861	65	0	0
T12	11956	17	0	0
T13	253233	7	0	0
T14	2902	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	223918	0	0
T2	1625	10	0	0
T3	211715	490	0	0
T7	24521	45	0	0
T8	35020	45	0	0
T9	20118	489	0	0
T10	10290	19	0	0
T11	6861	65	0	0
T12	11956	17	0	0
T13	253233	7	0	0
T14	2902	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2851002	0	0
T1	127280	1	0	0
T2	1625	11	0	0
T3	211715	3801	0	0
T7	24521	317	0	0
T8	35020	353	0	0
T9	20118	65	0	0
T10	10290	138	0	0
T11	6861	63	0	0
T12	11956	123	0	0
T13	253233	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	223918	0	0
T2	1625	10	0	0
T3	211715	490	0	0
T7	24521	45	0	0
T8	35020	45	0	0
T9	20118	489	0	0
T10	10290	19	0	0
T11	6861	65	0	0
T12	11956	17	0	0
T13	253233	7	0	0
T14	2902	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	223918	0	0
T2	1625	10	0	0
T3	211715	490	0	0
T7	24521	45	0	0
T8	35020	45	0	0
T9	20118	489	0	0
T10	10290	19	0	0
T11	6861	65	0	0
T12	11956	17	0	0
T13	253233	7	0	0
T14	2902	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	630040	0	0
T2	1625	10	0	0
T3	211715	573	0	0
T7	24521	58	0	0
T8	35020	48	0	0
T9	20118	914	0	0
T10	10290	24	0	0
T11	6861	68	0	0
T12	11956	29	0	0
T13	253233	7	0	0
T14	2902	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	223918	0	0
T2	1625	10	0	0
T3	211715	490	0	0
T7	24521	45	0	0
T8	35020	45	0	0
T9	20118	489	0	0
T10	10290	19	0	0
T11	6861	65	0	0
T12	11956	17	0	0
T13	253233	7	0	0
T14	2902	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	878487	0	0
GntImpliesValid_A	416917799	878487	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	878487	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	10626528	0	0
ReadyAndValidImplyGrant_A	416917799	878487	0	0
ReqAndReadyImplyGrant_A	416917799	878487	0	0
ReqImpliesValid_A	416917799	2294813	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	21808	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	878487	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	878487	0	0
T1	127280	1729	0	0
T2	1625	41	0	0
T3	211715	1993	0	0
T7	24521	196	0	0
T8	35020	374	0	0
T9	20118	1298	0	0
T10	10290	50	0	0
T11	6861	250	0	0
T12	11956	49	0	0
T13	253233	68	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	878487	0	0
T1	127280	1729	0	0
T2	1625	41	0	0
T3	211715	1993	0	0
T7	24521	196	0	0
T8	35020	374	0	0
T9	20118	1298	0	0
T10	10290	50	0	0
T11	6861	250	0	0
T12	11956	49	0	0
T13	253233	68	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	878487	0	0
T1	127280	1729	0	0
T2	1625	41	0	0
T3	211715	1993	0	0
T7	24521	196	0	0
T8	35020	374	0	0
T9	20118	1298	0	0
T10	10290	50	0	0
T11	6861	250	0	0
T12	11956	49	0	0
T13	253233	68	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	10626528	0	0
T1	127280	7046	0	0
T2	1625	1	0	0
T3	211715	13291	0	0
T7	24521	1266	0	0
T8	35020	2488	0	0
T9	20118	1	0	0
T10	10290	309	0	0
T11	6861	1	0	0
T12	11956	272	0	0
T13	253233	235	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	878487	0	0
T1	127280	1729	0	0
T2	1625	41	0	0
T3	211715	1993	0	0
T7	24521	196	0	0
T8	35020	374	0	0
T9	20118	1298	0	0
T10	10290	50	0	0
T11	6861	250	0	0
T12	11956	49	0	0
T13	253233	68	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	878487	0	0
T1	127280	1729	0	0
T2	1625	41	0	0
T3	211715	1993	0	0
T7	24521	196	0	0
T8	35020	374	0	0
T9	20118	1298	0	0
T10	10290	50	0	0
T11	6861	250	0	0
T12	11956	49	0	0
T13	253233	68	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	2294813	0	0
T1	127280	9506	0	0
T2	1625	41	0	0
T3	211715	2923	0	0
T7	24521	291	0	0
T8	35020	692	0	0
T9	20118	1298	0	0
T10	10290	60	0	0
T11	6861	250	0	0
T12	11956	80	0	0
T13	253233	75	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	21808	0	899
T1	127280	25	0	1
T2	1625	0	0	1
T3	211715	0	0	1
T7	24521	0	0	1
T8	35020	0	0	1
T9	20118	292	0	1
T10	10290	0	0	1
T11	6861	3	0	1
T12	11956	0	0	1
T13	253233	0	0	1
T14	0	3	0	0
T19	0	4	0	0
T21	0	8	0	0
T22	0	11	0	0
T23	0	7	0	0
T24	0	39	0	0
T25	0	86	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	878487	0	0
T1	127280	1729	0	0
T2	1625	41	0	0
T3	211715	1993	0	0
T7	24521	196	0	0
T8	35020	374	0	0
T9	20118	1298	0	0
T10	10290	50	0	0
T11	6861	250	0	0
T12	11956	49	0	0
T13	253233	68	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416917799	416790397	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	416917799	863407	0	0
GntImpliesValid_A	416917799	863407	0	0
GrantKnown_A	416917799	416790397	0	0
IdxKnown_A	416917799	416790397	0	0
IndexIsCorrect_A	416917799	863407	0	0
LockArbDecision_A	416917799	0	0	0
NoReadyValidNoGrant_A	416917799	349337196	0	0
ReadyAndValidImplyGrant_A	416917799	863407	0	0
ReqAndReadyImplyGrant_A	416917799	863407	0	0
ReqImpliesValid_A	416917799	12494092	0	0
ReqStaysHighUntilGranted0_M	416917799	0	0	0
RoundRobin_A	416917799	34388	0	899
ValidKnown_A	416917799	416790397	0	0
gen_data_port_assertion.DataFlow_A	416917799	863407	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	863407	0	0
T1	127280	921	0	0
T2	1625	46	0	0
T3	211715	1953	0	0
T7	24521	171	0	0
T8	35020	332	0	0
T9	20118	2130	0	0
T10	10290	38	0	0
T11	6861	211	0	0
T12	11956	51	0	0
T13	253233	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	863407	0	0
T1	127280	921	0	0
T2	1625	46	0	0
T3	211715	1953	0	0
T7	24521	171	0	0
T8	35020	332	0	0
T9	20118	2130	0	0
T10	10290	38	0	0
T11	6861	211	0	0
T12	11956	51	0	0
T13	253233	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	863407	0	0
T1	127280	921	0	0
T2	1625	46	0	0
T3	211715	1953	0	0
T7	24521	171	0	0
T8	35020	332	0	0
T9	20118	2130	0	0
T10	10290	38	0	0
T11	6861	211	0	0
T12	11956	51	0	0
T13	253233	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	349337196	0	0
T1	127280	109101	0	0
T2	1625	1	0	0
T3	211715	173947	0	0
T7	24521	21057	0	0
T8	35020	28564	0	0
T9	20118	1	0	0
T10	10290	9057	0	0
T11	6861	1	0	0
T12	11956	10359	0	0
T13	253233	210632	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	863407	0	0
T1	127280	921	0	0
T2	1625	46	0	0
T3	211715	1953	0	0
T7	24521	171	0	0
T8	35020	332	0	0
T9	20118	2130	0	0
T10	10290	38	0	0
T11	6861	211	0	0
T12	11956	51	0	0
T13	253233	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	863407	0	0
T1	127280	921	0	0
T2	1625	46	0	0
T3	211715	1953	0	0
T7	24521	171	0	0
T8	35020	332	0	0
T9	20118	2130	0	0
T10	10290	38	0	0
T11	6861	211	0	0
T12	11956	51	0	0
T13	253233	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	12494092	0	0
T1	127280	7404	0	0
T2	1625	46	0	0
T3	211715	14602	0	0
T7	24521	1345	0	0
T8	35020	2565	0	0
T9	20118	2130	0	0
T10	10290	313	0	0
T11	6861	211	0	0
T12	11956	389	0	0
T13	253233	237	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	34388	0	899
T3	211715	4	0	1
T4	0	15	0	0
T7	24521	0	0	1
T8	35020	1	0	1
T9	20118	997	0	1
T10	10290	0	0	1
T11	6861	3	0	1
T12	11956	0	0	1
T13	253233	0	0	1
T14	2902	0	0	1
T16	0	1	0	0
T17	0	3	0	0
T18	0	10	0	0
T19	0	7	0	0
T20	0	22	0	0
T26	9860	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	416790397	0	0
T1	127280	127247	0	0
T2	1625	1609	0	0
T3	211715	211634	0	0
T7	24521	24455	0	0
T8	35020	33846	0	0
T9	20118	20021	0	0
T10	10290	10251	0	0
T11	6861	6783	0	0
T12	11956	11888	0	0
T13	253233	253189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416917799	863407	0	0
T1	127280	921	0	0
T2	1625	46	0	0
T3	211715	1953	0	0
T7	24521	171	0	0
T8	35020	332	0	0
T9	20118	2130	0	0
T10	10290	38	0	0
T11	6861	211	0	0
T12	11956	51	0	0
T13	253233	62	0	0