Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1543776	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246328

1

T1

5

T2

203

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	608222	1			T1	38		T2	564		T3	56
values[0x0]	574526	1			T1	7		T2	496		T3	47
values[0x1]	607356	1			T1	37		T2	541		T3	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1192982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

597122

1

T1

26

T2

511

T3

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28563	1			T1	4		T2	21		T3	4
valid_sources[0x01]	28437	1			T2	23		T3	2		T7	46
valid_sources[0x02]	28079	1			T1	1		T2	21		T3	3
valid_sources[0x03]	28533	1			T2	23		T3	3		T7	25
valid_sources[0x04]	27590	1			T1	1		T2	32		T3	2
valid_sources[0x05]	26720	1			T1	1		T2	25		T3	2
valid_sources[0x06]	29497	1			T1	2		T2	23		T3	6
valid_sources[0x07]	27925	1			T1	2		T2	29		T3	1
valid_sources[0x08]	28495	1			T2	30		T3	2		T7	92
valid_sources[0x09]	28928	1			T1	3		T2	28		T3	2
valid_sources[0x0a]	27974	1			T1	4		T2	24		T3	1
valid_sources[0x0b]	28647	1			T1	2		T2	13		T3	2
valid_sources[0x0c]	27263	1			T2	29		T3	2		T7	37
valid_sources[0x0d]	27265	1			T1	1		T2	27		T3	2
valid_sources[0x0e]	28346	1			T2	20		T3	2		T7	16
valid_sources[0x0f]	26987	1			T1	1		T2	30		T3	2
valid_sources[0x10]	28401	1			T1	1		T2	35		T3	5
valid_sources[0x11]	27870	1			T2	22		T3	1		T7	19
valid_sources[0x12]	29219	1			T1	1		T2	17		T3	3
valid_sources[0x13]	27319	1			T2	26		T3	1		T7	28
valid_sources[0x14]	28547	1			T1	1		T2	23		T3	2
valid_sources[0x15]	28237	1			T1	1		T2	29		T3	2
valid_sources[0x16]	27808	1			T1	2		T2	20		T3	6
valid_sources[0x17]	27357	1			T1	1		T2	28		T3	3
valid_sources[0x18]	28155	1			T1	2		T2	20		T3	5
valid_sources[0x19]	27682	1			T1	2		T2	17		T3	1
valid_sources[0x1a]	28359	1			T1	1		T2	18		T3	2
valid_sources[0x1b]	28407	1			T1	2		T2	29		T3	6
valid_sources[0x1c]	28090	1			T1	1		T2	26		T3	2
valid_sources[0x1d]	27970	1			T1	2		T2	21		T3	3
valid_sources[0x1e]	27649	1			T1	3		T2	22		T3	3
valid_sources[0x1f]	27328	1			T1	2		T2	20		T7	22
valid_sources[0x20]	27308	1			T1	2		T2	17		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26224

1

T1

3

T2

18

T3

1

values[0x0]

all_enables

biggest_size

194117

1

T1

1

T2

160

T3

14

values[0x1]

all_enables

biggest_size

25987

1

T1

1

T2

25

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1562903	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253561

1

T1

7

T2

239

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	622233	1			T1	37		T2	532		T3	42
values[0x0]	571955	1			T1	6		T2	497		T3	30
values[0x1]	622276	1			T1	27		T2	542		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1199905	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

616559

1

T1

24

T2

559

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27905	1			T2	19		T7	44		T8	28
valid_sources[0x01]	28818	1			T1	1		T2	14		T7	24
valid_sources[0x02]	28752	1			T2	27		T7	31		T8	32
valid_sources[0x03]	28540	1			T1	1		T2	18		T7	33
valid_sources[0x04]	28786	1			T1	1		T2	18		T3	1
valid_sources[0x05]	27757	1			T2	31		T7	36		T8	27
valid_sources[0x06]	28340	1			T1	2		T2	28		T7	31
valid_sources[0x07]	28485	1			T2	38		T7	29		T8	40
valid_sources[0x08]	28500	1			T1	2		T2	14		T7	37
valid_sources[0x09]	28660	1			T2	30		T3	6		T7	27
valid_sources[0x0a]	29206	1			T1	2		T2	16		T3	6
valid_sources[0x0b]	28368	1			T2	47		T7	23		T8	21
valid_sources[0x0c]	27735	1			T2	17		T7	35		T8	35
valid_sources[0x0d]	28161	1			T2	10		T7	44		T8	15
valid_sources[0x0e]	29896	1			T2	17		T7	35		T8	25
valid_sources[0x0f]	28296	1			T1	1		T2	25		T3	12
valid_sources[0x10]	28087	1			T2	23		T7	31		T8	25
valid_sources[0x11]	27832	1			T1	1		T2	26		T7	35
valid_sources[0x12]	28696	1			T2	12		T3	1		T7	35
valid_sources[0x13]	29127	1			T1	1		T2	22		T7	36
valid_sources[0x14]	28327	1			T1	2		T2	23		T3	1
valid_sources[0x15]	27435	1			T1	1		T2	17		T7	28
valid_sources[0x16]	28568	1			T1	1		T2	27		T3	2
valid_sources[0x17]	28196	1			T1	4		T2	35		T3	3
valid_sources[0x18]	28430	1			T2	32		T7	31		T8	22
valid_sources[0x19]	27655	1			T2	32		T7	40		T8	27
valid_sources[0x1a]	27599	1			T1	2		T2	32		T3	1
valid_sources[0x1b]	28971	1			T1	1		T2	19		T3	8
valid_sources[0x1c]	29227	1			T2	26		T3	5		T7	28
valid_sources[0x1d]	28053	1			T1	3		T2	27		T7	36
valid_sources[0x1e]	28233	1			T1	1		T2	13		T7	33
valid_sources[0x1f]	27834	1			T1	1		T2	17		T3	4
valid_sources[0x20]	27965	1			T2	36		T3	13		T7	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26754

1

T1

3

T2

31

T3

4

values[0x0]

all_enables

biggest_size

200092

1

T1

2

T2

189

T3

10

values[0x1]

all_enables

biggest_size

26715

1

T1

2

T2

19

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1557860	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247833

1

T1

16

T2

188

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	613721	1			T1	41		T2	513		T3	58
values[0x0]	579129	1			T1	11		T2	470		T3	53
values[0x1]	612843	1			T1	39		T2	516		T3	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1202477	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

603216

1

T1

41

T2

496

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27424	1			T1	3		T2	5		T3	6
valid_sources[0x01]	28031	1			T1	1		T2	28		T3	14
valid_sources[0x02]	28119	1			T1	1		T2	25		T3	3
valid_sources[0x03]	28482	1			T1	3		T3	8		T7	44
valid_sources[0x04]	27902	1			T1	1		T2	15		T7	27
valid_sources[0x05]	27632	1			T1	1		T2	75		T7	36
valid_sources[0x06]	28452	1			T2	15		T3	3		T7	43
valid_sources[0x07]	27941	1			T1	2		T2	13		T3	8
valid_sources[0x08]	28553	1			T2	34		T3	4		T7	26
valid_sources[0x09]	27526	1			T1	2		T2	96		T7	38
valid_sources[0x0a]	29016	1			T1	1		T2	19		T3	12
valid_sources[0x0b]	27743	1			T1	2		T2	19		T3	1
valid_sources[0x0c]	28012	1			T1	2		T2	40		T3	1
valid_sources[0x0d]	27410	1			T1	1		T2	25		T3	2
valid_sources[0x0e]	28318	1			T1	2		T2	3		T3	2
valid_sources[0x0f]	28108	1			T1	1		T2	4		T7	36
valid_sources[0x10]	27500	1			T1	2		T2	24		T3	2
valid_sources[0x11]	28673	1			T1	1		T3	3		T7	31
valid_sources[0x12]	28161	1			T2	6		T7	35		T8	27
valid_sources[0x13]	27603	1			T2	36		T3	2		T7	25
valid_sources[0x14]	27768	1			T1	1		T2	63		T7	34
valid_sources[0x15]	28104	1			T1	2		T2	9		T7	41
valid_sources[0x16]	27423	1			T7	32		T8	29		T9	11
valid_sources[0x17]	27530	1			T2	6		T3	2		T7	40
valid_sources[0x18]	27693	1			T2	43		T3	4		T7	51
valid_sources[0x19]	28080	1			T1	2		T2	5		T3	6
valid_sources[0x1a]	27734	1			T1	2		T2	15		T3	1
valid_sources[0x1b]	28206	1			T1	1		T2	72		T3	3
valid_sources[0x1c]	28708	1			T1	3		T2	12		T3	2
valid_sources[0x1d]	28227	1			T1	4		T2	54		T3	3
valid_sources[0x1e]	28513	1			T1	1		T2	18		T7	36
valid_sources[0x1f]	28003	1			T1	1		T2	25		T7	28
valid_sources[0x20]	28260	1			T1	1		T2	52		T7	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26115

1

T1

9

T2

15

T3

2

values[0x0]

all_enables

biggest_size

195585

1

T1

4

T2

157

T3

13

values[0x1]

all_enables

biggest_size

26133

1

T1

3

T2

16

T7

39