Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8022837	0	0
GntImpliesValid_A	2147483647	8022837	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8022837	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	440352281	0	0
ReadyAndValidImplyGrant_A	2147483647	8022837	0	0
ReqAndReadyImplyGrant_A	2147483647	8022837	0	0
ReqImpliesValid_A	2147483647	33740387	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	45676	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8022837	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1321920	1320456	0	0
T2	225024	222816	0	0
T3	6866016	6865224	0	0
T7	5948544	5948424	0	0
T8	301632	300264	0	0
T9	128808	127920	0	0
T10	7999104	7999032	0	0
T11	6510168	6509760	0	0
T12	52320	50640	0	0
T13	39648	39120	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8022837	0	0
T1	1321920	5455	0	0
T2	225024	4671	0	0
T3	6866016	411	0	0
T7	5948544	6623	0	0
T8	301632	5180	0	0
T9	128808	2853	0	0
T10	7999104	7500	0	0
T11	6510168	449	0	0
T12	52320	380	0	0
T13	39648	385	0	0
T14	0	146	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8022837	0	0
T1	1321920	5455	0	0
T2	225024	4671	0	0
T3	6866016	411	0	0
T7	5948544	6623	0	0
T8	301632	5180	0	0
T9	128808	2853	0	0
T10	7999104	7500	0	0
T11	6510168	449	0	0
T12	52320	380	0	0
T13	39648	385	0	0
T14	0	146	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1321920	1320456	0	0
T2	225024	222816	0	0
T3	6866016	6865224	0	0
T7	5948544	5948424	0	0
T8	301632	300264	0	0
T9	128808	127920	0	0
T10	7999104	7999032	0	0
T11	6510168	6509760	0	0
T12	52320	50640	0	0
T13	39648	39120	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1321920	1320456	0	0
T2	225024	222816	0	0
T3	6866016	6865224	0	0
T7	5948544	5948424	0	0
T8	301632	300264	0	0
T9	128808	127920	0	0
T10	7999104	7999032	0	0
T11	6510168	6509760	0	0
T12	52320	50640	0	0
T13	39648	39120	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8022837	0	0
T1	1321920	5455	0	0
T2	225024	4671	0	0
T3	6866016	411	0	0
T7	5948544	6623	0	0
T8	301632	5180	0	0
T9	128808	2853	0	0
T10	7999104	7500	0	0
T11	6510168	449	0	0
T12	52320	380	0	0
T13	39648	385	0	0
T14	0	146	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	440352281	0	0
T1	1321920	87971	0	0
T2	225024	6453	0	0
T3	6866016	240004	0	0
T7	5948544	2227633	0	0
T8	301632	747	0	0
T9	128808	3789	0	0
T10	7999104	2565392	0	0
T11	6510168	227742	0	0
T12	52320	619	0	0
T13	39648	455	0	0
T14	0	382	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8022837	0	0
T1	1321920	5455	0	0
T2	225024	4671	0	0
T3	6866016	411	0	0
T7	5948544	6623	0	0
T8	301632	5180	0	0
T9	128808	2853	0	0
T10	7999104	7500	0	0
T11	6510168	449	0	0
T12	52320	380	0	0
T13	39648	385	0	0
T14	0	146	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8022837	0	0
T1	1321920	5455	0	0
T2	225024	4671	0	0
T3	6866016	411	0	0
T7	5948544	6623	0	0
T8	301632	5180	0	0
T9	128808	2853	0	0
T10	7999104	7500	0	0
T11	6510168	449	0	0
T12	52320	380	0	0
T13	39648	385	0	0
T14	0	146	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33740387	0	0
T1	1321920	13826	0	0
T2	225024	5600	0	0
T3	6866016	724	0	0
T7	5948544	409906	0	0
T8	301632	13697	0	0
T9	128808	3279	0	0
T10	7999104	454666	0	0
T11	6510168	695	0	0
T12	52320	442	0	0
T13	39648	430	0	0
T14	0	210	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45676	0	21600
T2	18752	13	0	2
T3	572168	0	0	2
T4	0	13	0	0
T5	0	1	0	0
T7	495712	0	0	2
T8	25136	0	0	2
T9	10734	5	0	2
T10	666592	1	0	2
T11	542514	0	0	2
T12	4360	0	0	2
T13	3304	0	0	2
T14	224976	0	0	2
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	25	0	0
T19	0	38	0	0
T20	0	6	0	0
T21	0	407	0	0
T22	0	1	0	0
T23	0	16	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1321920	1320456	0	0
T2	225024	222816	0	0
T3	6866016	6865224	0	0
T7	5948544	5948424	0	0
T8	301632	300264	0	0
T9	128808	127920	0	0
T10	7999104	7999032	0	0
T11	6510168	6509760	0	0
T12	52320	50640	0	0
T13	39648	39120	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8022837	0	0
T1	1321920	5455	0	0
T2	225024	4671	0	0
T3	6866016	411	0	0
T7	5948544	6623	0	0
T8	301632	5180	0	0
T9	128808	2853	0	0
T10	7999104	7500	0	0
T11	6510168	449	0	0
T12	52320	380	0	0
T13	39648	385	0	0
T14	0	146	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	890751	0	0
GntImpliesValid_A	405947867	890751	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	890751	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	11673866	0	0
ReadyAndValidImplyGrant_A	405947867	890751	0	0
ReqAndReadyImplyGrant_A	405947867	890751	0	0
ReqImpliesValid_A	405947867	2390378	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	890751	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	890751	0	0
T1	55080	630	0	0
T2	9376	499	0	0
T3	286084	31	0	0
T7	247856	750	0	0
T8	12568	348	0	0
T9	5367	325	0	0
T10	333296	824	0	0
T11	271257	71	0	0
T12	2180	48	0	0
T13	1652	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	890751	0	0
T1	55080	630	0	0
T2	9376	499	0	0
T3	286084	31	0	0
T7	247856	750	0	0
T8	12568	348	0	0
T9	5367	325	0	0
T10	333296	824	0	0
T11	271257	71	0	0
T12	2180	48	0	0
T13	1652	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	890751	0	0
T1	55080	630	0	0
T2	9376	499	0	0
T3	286084	31	0	0
T7	247856	750	0	0
T8	12568	348	0	0
T9	5367	325	0	0
T10	333296	824	0	0
T11	271257	71	0	0
T12	2180	48	0	0
T13	1652	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	11673866	0	0
T1	55080	4648	0	0
T2	9376	357	0	0
T3	286084	134	0	0
T7	247856	245043	0	0
T8	12568	263	0	0
T9	5367	240	0	0
T10	333296	273590	0	0
T11	271257	307	0	0
T12	2180	39	0	0
T13	1652	36	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	890751	0	0
T1	55080	630	0	0
T2	9376	499	0	0
T3	286084	31	0	0
T7	247856	750	0	0
T8	12568	348	0	0
T9	5367	325	0	0
T10	333296	824	0	0
T11	271257	71	0	0
T12	2180	48	0	0
T13	1652	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	890751	0	0
T1	55080	630	0	0
T2	9376	499	0	0
T3	286084	31	0	0
T7	247856	750	0	0
T8	12568	348	0	0
T9	5367	325	0	0
T10	333296	824	0	0
T11	271257	71	0	0
T12	2180	48	0	0
T13	1652	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2390378	0	0
T1	55080	1237	0	0
T2	9376	642	0	0
T3	286084	35	0	0
T7	247856	31894	0	0
T8	12568	434	0	0
T9	5367	411	0	0
T10	333296	27157	0	0
T11	271257	103	0	0
T12	2180	58	0	0
T13	1652	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	890751	0	0
T1	55080	630	0	0
T2	9376	499	0	0
T3	286084	31	0	0
T7	247856	750	0	0
T8	12568	348	0	0
T9	5367	325	0	0
T10	333296	824	0	0
T11	271257	71	0	0
T12	2180	48	0	0
T13	1652	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	894834	0	0
GntImpliesValid_A	405947867	894834	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	894834	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	11835951	0	0
ReadyAndValidImplyGrant_A	405947867	894834	0	0
ReqAndReadyImplyGrant_A	405947867	894834	0	0
ReqImpliesValid_A	405947867	2454059	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	894834	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	894834	0	0
T1	55080	605	0	0
T2	9376	523	0	0
T3	286084	31	0	0
T7	247856	742	0	0
T8	12568	1143	0	0
T9	5367	298	0	0
T10	333296	828	0	0
T11	271257	49	0	0
T12	2180	38	0	0
T13	1652	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	894834	0	0
T1	55080	605	0	0
T2	9376	523	0	0
T3	286084	31	0	0
T7	247856	742	0	0
T8	12568	1143	0	0
T9	5367	298	0	0
T10	333296	828	0	0
T11	271257	49	0	0
T12	2180	38	0	0
T13	1652	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	894834	0	0
T1	55080	605	0	0
T2	9376	523	0	0
T3	286084	31	0	0
T7	247856	742	0	0
T8	12568	1143	0	0
T9	5367	298	0	0
T10	333296	828	0	0
T11	271257	49	0	0
T12	2180	38	0	0
T13	1652	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	11835951	0	0
T1	55080	4229	0	0
T2	9376	380	0	0
T3	286084	136	0	0
T7	247856	211620	0	0
T8	12568	266	0	0
T9	5367	240	0	0
T10	333296	280081	0	0
T11	271257	239	0	0
T12	2180	32	0	0
T13	1652	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	894834	0	0
T1	55080	605	0	0
T2	9376	523	0	0
T3	286084	31	0	0
T7	247856	742	0	0
T8	12568	1143	0	0
T9	5367	298	0	0
T10	333296	828	0	0
T11	271257	49	0	0
T12	2180	38	0	0
T13	1652	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	894834	0	0
T1	55080	605	0	0
T2	9376	523	0	0
T3	286084	31	0	0
T7	247856	742	0	0
T8	12568	1143	0	0
T9	5367	298	0	0
T10	333296	828	0	0
T11	271257	49	0	0
T12	2180	38	0	0
T13	1652	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2454059	0	0
T1	55080	1021	0	0
T2	9376	667	0	0
T3	286084	47	0	0
T7	247856	24371	0	0
T8	12568	2021	0	0
T9	5367	357	0	0
T10	333296	24762	0	0
T11	271257	67	0	0
T12	2180	45	0	0
T13	1652	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	894834	0	0
T1	55080	605	0	0
T2	9376	523	0	0
T3	286084	31	0	0
T7	247856	742	0	0
T8	12568	1143	0	0
T9	5367	298	0	0
T10	333296	828	0	0
T11	271257	49	0	0
T12	2180	38	0	0
T13	1652	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	221655	0	0
GntImpliesValid_A	405947867	221655	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	221655	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2926734	0	0
ReadyAndValidImplyGrant_A	405947867	221655	0	0
ReqAndReadyImplyGrant_A	405947867	221655	0	0
ReqImpliesValid_A	405947867	568757	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	221655	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221655	0	0
T1	55080	145	0	0
T2	9376	153	0	0
T3	286084	8	0	0
T7	247856	189	0	0
T8	12568	0	0	0
T9	5367	74	0	0
T10	333296	189	0	0
T11	271257	12	0	0
T12	2180	9	0	0
T13	1652	12	0	0
T14	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221655	0	0
T1	55080	145	0	0
T2	9376	153	0	0
T3	286084	8	0	0
T7	247856	189	0	0
T8	12568	0	0	0
T9	5367	74	0	0
T10	333296	189	0	0
T11	271257	12	0	0
T12	2180	9	0	0
T13	1652	12	0	0
T14	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221655	0	0
T1	55080	145	0	0
T2	9376	153	0	0
T3	286084	8	0	0
T7	247856	189	0	0
T8	12568	0	0	0
T9	5367	74	0	0
T10	333296	189	0	0
T11	271257	12	0	0
T12	2180	9	0	0
T13	1652	12	0	0
T14	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2926734	0	0
T1	55080	1030	0	0
T2	9376	146	0	0
T3	286084	35	0	0
T7	247856	62872	0	0
T8	12568	1	0	0
T9	5367	71	0	0
T10	333296	62863	0	0
T11	271257	61	0	0
T12	2180	10	0	0
T13	1652	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221655	0	0
T1	55080	145	0	0
T2	9376	153	0	0
T3	286084	8	0	0
T7	247856	189	0	0
T8	12568	0	0	0
T9	5367	74	0	0
T10	333296	189	0	0
T11	271257	12	0	0
T12	2180	9	0	0
T13	1652	12	0	0
T14	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221655	0	0
T1	55080	145	0	0
T2	9376	153	0	0
T3	286084	8	0	0
T7	247856	189	0	0
T8	12568	0	0	0
T9	5367	74	0	0
T10	333296	189	0	0
T11	271257	12	0	0
T12	2180	9	0	0
T13	1652	12	0	0
T14	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	568757	0	0
T1	55080	204	0	0
T2	9376	161	0	0
T3	286084	8	0	0
T7	247856	4531	0	0
T8	12568	0	0	0
T9	5367	78	0	0
T10	333296	2516	0	0
T11	271257	17	0	0
T12	2180	9	0	0
T13	1652	13	0	0
T14	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221655	0	0
T1	55080	145	0	0
T2	9376	153	0	0
T3	286084	8	0	0
T7	247856	189	0	0
T8	12568	0	0	0
T9	5367	74	0	0
T10	333296	189	0	0
T11	271257	12	0	0
T12	2180	9	0	0
T13	1652	12	0	0
T14	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	220409	0	0
GntImpliesValid_A	405947867	220409	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	220409	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2942884	0	0
ReadyAndValidImplyGrant_A	405947867	220409	0	0
ReqAndReadyImplyGrant_A	405947867	220409	0	0
ReqImpliesValid_A	405947867	560925	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	220409	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220409	0	0
T1	55080	127	0	0
T2	9376	115	0	0
T3	286084	16	0	0
T7	247856	217	0	0
T8	12568	0	0	0
T9	5367	91	0	0
T10	333296	198	0	0
T11	271257	9	0	0
T12	2180	18	0	0
T13	1652	9	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220409	0	0
T1	55080	127	0	0
T2	9376	115	0	0
T3	286084	16	0	0
T7	247856	217	0	0
T8	12568	0	0	0
T9	5367	91	0	0
T10	333296	198	0	0
T11	271257	9	0	0
T12	2180	18	0	0
T13	1652	9	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220409	0	0
T1	55080	127	0	0
T2	9376	115	0	0
T3	286084	16	0	0
T7	247856	217	0	0
T8	12568	0	0	0
T9	5367	91	0	0
T10	333296	198	0	0
T11	271257	9	0	0
T12	2180	18	0	0
T13	1652	9	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2942884	0	0
T1	55080	798	0	0
T2	9376	113	0	0
T3	286084	63	0	0
T7	247856	70077	0	0
T8	12568	1	0	0
T9	5367	81	0	0
T10	333296	63864	0	0
T11	271257	35	0	0
T12	2180	16	0	0
T13	1652	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220409	0	0
T1	55080	127	0	0
T2	9376	115	0	0
T3	286084	16	0	0
T7	247856	217	0	0
T8	12568	0	0	0
T9	5367	91	0	0
T10	333296	198	0	0
T11	271257	9	0	0
T12	2180	18	0	0
T13	1652	9	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220409	0	0
T1	55080	127	0	0
T2	9376	115	0	0
T3	286084	16	0	0
T7	247856	217	0	0
T8	12568	0	0	0
T9	5367	91	0	0
T10	333296	198	0	0
T11	271257	9	0	0
T12	2180	18	0	0
T13	1652	9	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	560925	0	0
T1	55080	187	0	0
T2	9376	118	0	0
T3	286084	16	0	0
T7	247856	4814	0	0
T8	12568	0	0	0
T9	5367	102	0	0
T10	333296	3539	0	0
T11	271257	10	0	0
T12	2180	21	0	0
T13	1652	9	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220409	0	0
T1	55080	127	0	0
T2	9376	115	0	0
T3	286084	16	0	0
T7	247856	217	0	0
T8	12568	0	0	0
T9	5367	91	0	0
T10	333296	198	0	0
T11	271257	9	0	0
T12	2180	18	0	0
T13	1652	9	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	221226	0	0
GntImpliesValid_A	405947867	221226	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	221226	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	4846094	0	0
ReadyAndValidImplyGrant_A	405947867	221226	0	0
ReqAndReadyImplyGrant_A	405947867	221226	0	0
ReqImpliesValid_A	405947867	1254142	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	221226	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221226	0	0
T1	55080	137	0	0
T2	9376	137	0	0
T3	286084	15	0	0
T7	247856	171	0	0
T8	12568	551	0	0
T9	5367	70	0	0
T10	333296	219	0	0
T11	271257	17	0	0
T12	2180	15	0	0
T13	1652	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221226	0	0
T1	55080	137	0	0
T2	9376	137	0	0
T3	286084	15	0	0
T7	247856	171	0	0
T8	12568	551	0	0
T9	5367	70	0	0
T10	333296	219	0	0
T11	271257	17	0	0
T12	2180	15	0	0
T13	1652	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221226	0	0
T1	55080	137	0	0
T2	9376	137	0	0
T3	286084	15	0	0
T7	247856	171	0	0
T8	12568	551	0	0
T9	5367	70	0	0
T10	333296	219	0	0
T11	271257	17	0	0
T12	2180	15	0	0
T13	1652	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	4846094	0	0
T1	55080	1574	0	0
T2	9376	696	0	0
T3	286084	158	0	0
T7	247856	48295	0	0
T8	12568	48	0	0
T9	5367	771	0	0
T10	333296	160507	0	0
T11	271257	102	0	0
T12	2180	160	0	0
T13	1652	68	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221226	0	0
T1	55080	137	0	0
T2	9376	137	0	0
T3	286084	15	0	0
T7	247856	171	0	0
T8	12568	551	0	0
T9	5367	70	0	0
T10	333296	219	0	0
T11	271257	17	0	0
T12	2180	15	0	0
T13	1652	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221226	0	0
T1	55080	137	0	0
T2	9376	137	0	0
T3	286084	15	0	0
T7	247856	171	0	0
T8	12568	551	0	0
T9	5367	70	0	0
T10	333296	219	0	0
T11	271257	17	0	0
T12	2180	15	0	0
T13	1652	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	1254142	0	0
T1	55080	210	0	0
T2	9376	263	0	0
T3	286084	31	0	0
T7	247856	1614	0	0
T8	12568	3713	0	0
T9	5367	119	0	0
T10	333296	11638	0	0
T11	271257	23	0	0
T12	2180	15	0	0
T13	1652	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	221226	0	0
T1	55080	137	0	0
T2	9376	137	0	0
T3	286084	15	0	0
T7	247856	171	0	0
T8	12568	551	0	0
T9	5367	70	0	0
T10	333296	219	0	0
T11	271257	17	0	0
T12	2180	15	0	0
T13	1652	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	218617	0	0
GntImpliesValid_A	405947867	218617	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	218617	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	4298079	0	0
ReadyAndValidImplyGrant_A	405947867	218617	0	0
ReqAndReadyImplyGrant_A	405947867	218617	0	0
ReqImpliesValid_A	405947867	1056453	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	218617	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218617	0	0
T1	55080	165	0	0
T2	9376	132	0	0
T3	286084	17	0	0
T7	247856	177	0	0
T8	12568	0	0	0
T9	5367	83	0	0
T10	333296	225	0	0
T11	271257	15	0	0
T12	2180	13	0	0
T13	1652	10	0	0
T14	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218617	0	0
T1	55080	165	0	0
T2	9376	132	0	0
T3	286084	17	0	0
T7	247856	177	0	0
T8	12568	0	0	0
T9	5367	83	0	0
T10	333296	225	0	0
T11	271257	15	0	0
T12	2180	13	0	0
T13	1652	10	0	0
T14	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218617	0	0
T1	55080	165	0	0
T2	9376	132	0	0
T3	286084	17	0	0
T7	247856	177	0	0
T8	12568	0	0	0
T9	5367	83	0	0
T10	333296	225	0	0
T11	271257	15	0	0
T12	2180	13	0	0
T13	1652	10	0	0
T14	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	4298079	0	0
T1	55080	1766	0	0
T2	9376	880	0	0
T3	286084	212	0	0
T7	247856	70946	0	0
T8	12568	0	0	0
T9	5367	549	0	0
T10	333296	75826	0	0
T11	271257	76	0	0
T12	2180	117	0	0
T13	1652	45	0	0
T14	0	71	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218617	0	0
T1	55080	165	0	0
T2	9376	132	0	0
T3	286084	17	0	0
T7	247856	177	0	0
T8	12568	0	0	0
T9	5367	83	0	0
T10	333296	225	0	0
T11	271257	15	0	0
T12	2180	13	0	0
T13	1652	10	0	0
T14	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218617	0	0
T1	55080	165	0	0
T2	9376	132	0	0
T3	286084	17	0	0
T7	247856	177	0	0
T8	12568	0	0	0
T9	5367	83	0	0
T10	333296	225	0	0
T11	271257	15	0	0
T12	2180	13	0	0
T13	1652	10	0	0
T14	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	1056453	0	0
T1	55080	237	0	0
T2	9376	223	0	0
T3	286084	64	0	0
T7	247856	3597	0	0
T8	12568	0	0	0
T9	5367	164	0	0
T10	333296	4267	0	0
T11	271257	21	0	0
T12	2180	21	0	0
T13	1652	21	0	0
T14	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218617	0	0
T1	55080	165	0	0
T2	9376	132	0	0
T3	286084	17	0	0
T7	247856	177	0	0
T8	12568	0	0	0
T9	5367	83	0	0
T10	333296	225	0	0
T11	271257	15	0	0
T12	2180	13	0	0
T13	1652	10	0	0
T14	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	218178	0	0
GntImpliesValid_A	405947867	218178	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	218178	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	5158258	0	0
ReadyAndValidImplyGrant_A	405947867	218178	0	0
ReqAndReadyImplyGrant_A	405947867	218178	0	0
ReqImpliesValid_A	405947867	1140044	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	218178	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218178	0	0
T1	55080	144	0	0
T2	9376	128	0	0
T3	286084	15	0	0
T7	247856	175	0	0
T8	12568	449	0	0
T9	5367	74	0	0
T10	333296	219	0	0
T11	271257	10	0	0
T12	2180	13	0	0
T13	1652	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218178	0	0
T1	55080	144	0	0
T2	9376	128	0	0
T3	286084	15	0	0
T7	247856	175	0	0
T8	12568	449	0	0
T9	5367	74	0	0
T10	333296	219	0	0
T11	271257	10	0	0
T12	2180	13	0	0
T13	1652	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218178	0	0
T1	55080	144	0	0
T2	9376	128	0	0
T3	286084	15	0	0
T7	247856	175	0	0
T8	12568	449	0	0
T9	5367	74	0	0
T10	333296	219	0	0
T11	271257	10	0	0
T12	2180	13	0	0
T13	1652	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	5158258	0	0
T1	55080	7438	0	0
T2	9376	1279	0	0
T3	286084	140	0	0
T7	247856	160759	0	0
T8	12568	56	0	0
T9	5367	389	0	0
T10	333296	36781	0	0
T11	271257	46	0	0
T12	2180	70	0	0
T13	1652	44	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218178	0	0
T1	55080	144	0	0
T2	9376	128	0	0
T3	286084	15	0	0
T7	247856	175	0	0
T8	12568	449	0	0
T9	5367	74	0	0
T10	333296	219	0	0
T11	271257	10	0	0
T12	2180	13	0	0
T13	1652	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218178	0	0
T1	55080	144	0	0
T2	9376	128	0	0
T3	286084	15	0	0
T7	247856	175	0	0
T8	12568	449	0	0
T9	5367	74	0	0
T10	333296	219	0	0
T11	271257	10	0	0
T12	2180	13	0	0
T13	1652	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	1140044	0	0
T1	55080	1307	0	0
T2	9376	326	0	0
T3	286084	35	0	0
T7	247856	16426	0	0
T8	12568	3010	0	0
T9	5367	97	0	0
T10	333296	2495	0	0
T11	271257	10	0	0
T12	2180	31	0	0
T13	1652	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218178	0	0
T1	55080	144	0	0
T2	9376	128	0	0
T3	286084	15	0	0
T7	247856	175	0	0
T8	12568	449	0	0
T9	5367	74	0	0
T10	333296	219	0	0
T11	271257	10	0	0
T12	2180	13	0	0
T13	1652	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	231404	0	0
GntImpliesValid_A	405947867	231404	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	231404	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	5151431	0	0
ReadyAndValidImplyGrant_A	405947867	231404	0	0
ReqAndReadyImplyGrant_A	405947867	231404	0	0
ReqImpliesValid_A	405947867	1322823	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	231404	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	231404	0	0
T1	55080	161	0	0
T2	9376	124	0	0
T3	286084	11	0	0
T7	247856	191	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	227	0	0
T11	271257	3	0	0
T12	2180	9	0	0
T13	1652	11	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	231404	0	0
T1	55080	161	0	0
T2	9376	124	0	0
T3	286084	11	0	0
T7	247856	191	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	227	0	0
T11	271257	3	0	0
T12	2180	9	0	0
T13	1652	11	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	231404	0	0
T1	55080	161	0	0
T2	9376	124	0	0
T3	286084	11	0	0
T7	247856	191	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	227	0	0
T11	271257	3	0	0
T12	2180	9	0	0
T13	1652	11	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	5151431	0	0
T1	55080	1708	0	0
T2	9376	838	0	0
T3	286084	78	0	0
T7	247856	116044	0	0
T8	12568	0	0	0
T9	5367	404	0	0
T10	333296	90895	0	0
T11	271257	32	0	0
T12	2180	38	0	0
T13	1652	47	0	0
T14	0	311	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	231404	0	0
T1	55080	161	0	0
T2	9376	124	0	0
T3	286084	11	0	0
T7	247856	191	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	227	0	0
T11	271257	3	0	0
T12	2180	9	0	0
T13	1652	11	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	231404	0	0
T1	55080	161	0	0
T2	9376	124	0	0
T3	286084	11	0	0
T7	247856	191	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	227	0	0
T11	271257	3	0	0
T12	2180	9	0	0
T13	1652	11	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	1322823	0	0
T1	55080	261	0	0
T2	9376	251	0	0
T3	286084	11	0	0
T7	247856	4971	0	0
T8	12568	0	0	0
T9	5367	125	0	0
T10	333296	4977	0	0
T11	271257	3	0	0
T12	2180	20	0	0
T13	1652	13	0	0
T14	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	231404	0	0
T1	55080	161	0	0
T2	9376	124	0	0
T3	286084	11	0	0
T7	247856	191	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	227	0	0
T11	271257	3	0	0
T12	2180	9	0	0
T13	1652	11	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	220019	0	0
GntImpliesValid_A	405947867	220019	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	220019	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2895570	0	0
ReadyAndValidImplyGrant_A	405947867	220019	0	0
ReqAndReadyImplyGrant_A	405947867	220019	0	0
ReqImpliesValid_A	405947867	549210	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	220019	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220019	0	0
T1	55080	144	0	0
T2	9376	133	0	0
T3	286084	10	0	0
T7	247856	184	0	0
T8	12568	0	0	0
T9	5367	60	0	0
T10	333296	206	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	6	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220019	0	0
T1	55080	144	0	0
T2	9376	133	0	0
T3	286084	10	0	0
T7	247856	184	0	0
T8	12568	0	0	0
T9	5367	60	0	0
T10	333296	206	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	6	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220019	0	0
T1	55080	144	0	0
T2	9376	133	0	0
T3	286084	10	0	0
T7	247856	184	0	0
T8	12568	0	0	0
T9	5367	60	0	0
T10	333296	206	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	6	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2895570	0	0
T1	55080	1094	0	0
T2	9376	130	0	0
T3	286084	44	0	0
T7	247856	55984	0	0
T8	12568	1	0	0
T9	5367	60	0	0
T10	333296	63672	0	0
T11	271257	56	0	0
T12	2180	9	0	0
T13	1652	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220019	0	0
T1	55080	144	0	0
T2	9376	133	0	0
T3	286084	10	0	0
T7	247856	184	0	0
T8	12568	0	0	0
T9	5367	60	0	0
T10	333296	206	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	6	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220019	0	0
T1	55080	144	0	0
T2	9376	133	0	0
T3	286084	10	0	0
T7	247856	184	0	0
T8	12568	0	0	0
T9	5367	60	0	0
T10	333296	206	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	6	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	549210	0	0
T1	55080	233	0	0
T2	9376	137	0	0
T3	286084	13	0	0
T7	247856	6227	0	0
T8	12568	0	0	0
T9	5367	61	0	0
T10	333296	1899	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	7	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220019	0	0
T1	55080	144	0	0
T2	9376	133	0	0
T3	286084	10	0	0
T7	247856	184	0	0
T8	12568	0	0	0
T9	5367	60	0	0
T10	333296	206	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	6	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	226047	0	0
GntImpliesValid_A	405947867	226047	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	226047	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2910664	0	0
ReadyAndValidImplyGrant_A	405947867	226047	0	0
ReqAndReadyImplyGrant_A	405947867	226047	0	0
ReqImpliesValid_A	405947867	546145	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	226047	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226047	0	0
T1	55080	147	0	0
T2	9376	142	0	0
T3	286084	15	0	0
T7	247856	160	0	0
T8	12568	456	0	0
T9	5367	111	0	0
T10	333296	217	0	0
T11	271257	9	0	0
T12	2180	12	0	0
T13	1652	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226047	0	0
T1	55080	147	0	0
T2	9376	142	0	0
T3	286084	15	0	0
T7	247856	160	0	0
T8	12568	456	0	0
T9	5367	111	0	0
T10	333296	217	0	0
T11	271257	9	0	0
T12	2180	12	0	0
T13	1652	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226047	0	0
T1	55080	147	0	0
T2	9376	142	0	0
T3	286084	15	0	0
T7	247856	160	0	0
T8	12568	456	0	0
T9	5367	111	0	0
T10	333296	217	0	0
T11	271257	9	0	0
T12	2180	12	0	0
T13	1652	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2910664	0	0
T1	55080	1131	0	0
T2	9376	139	0	0
T3	286084	61	0	0
T7	247856	54071	0	0
T8	12568	2	0	0
T9	5367	105	0	0
T10	333296	72817	0	0
T11	271257	46	0	0
T12	2180	13	0	0
T13	1652	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226047	0	0
T1	55080	147	0	0
T2	9376	142	0	0
T3	286084	15	0	0
T7	247856	160	0	0
T8	12568	456	0	0
T9	5367	111	0	0
T10	333296	217	0	0
T11	271257	9	0	0
T12	2180	12	0	0
T13	1652	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226047	0	0
T1	55080	147	0	0
T2	9376	142	0	0
T3	286084	15	0	0
T7	247856	160	0	0
T8	12568	456	0	0
T9	5367	111	0	0
T10	333296	217	0	0
T11	271257	9	0	0
T12	2180	12	0	0
T13	1652	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	546145	0	0
T1	55080	187	0	0
T2	9376	146	0	0
T3	286084	18	0	0
T7	247856	2641	0	0
T8	12568	911	0	0
T9	5367	118	0	0
T10	333296	4516	0	0
T11	271257	9	0	0
T12	2180	12	0	0
T13	1652	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226047	0	0
T1	55080	147	0	0
T2	9376	142	0	0
T3	286084	15	0	0
T7	247856	160	0	0
T8	12568	456	0	0
T9	5367	111	0	0
T10	333296	217	0	0
T11	271257	9	0	0
T12	2180	12	0	0
T13	1652	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	220670	0	0
GntImpliesValid_A	405947867	220670	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	220670	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	3004482	0	0
ReadyAndValidImplyGrant_A	405947867	220670	0	0
ReqAndReadyImplyGrant_A	405947867	220670	0	0
ReqImpliesValid_A	405947867	592044	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	220670	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220670	0	0
T1	55080	139	0	0
T2	9376	138	0	0
T3	286084	10	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	88	0	0
T10	333296	209	0	0
T11	271257	10	0	0
T12	2180	6	0	0
T13	1652	13	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220670	0	0
T1	55080	139	0	0
T2	9376	138	0	0
T3	286084	10	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	88	0	0
T10	333296	209	0	0
T11	271257	10	0	0
T12	2180	6	0	0
T13	1652	13	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220670	0	0
T1	55080	139	0	0
T2	9376	138	0	0
T3	286084	10	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	88	0	0
T10	333296	209	0	0
T11	271257	10	0	0
T12	2180	6	0	0
T13	1652	13	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	3004482	0	0
T1	55080	1033	0	0
T2	9376	126	0	0
T3	286084	39	0	0
T7	247856	54474	0	0
T8	12568	1	0	0
T9	5367	85	0	0
T10	333296	69148	0	0
T11	271257	40	0	0
T12	2180	7	0	0
T13	1652	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220670	0	0
T1	55080	139	0	0
T2	9376	138	0	0
T3	286084	10	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	88	0	0
T10	333296	209	0	0
T11	271257	10	0	0
T12	2180	6	0	0
T13	1652	13	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220670	0	0
T1	55080	139	0	0
T2	9376	138	0	0
T3	286084	10	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	88	0	0
T10	333296	209	0	0
T11	271257	10	0	0
T12	2180	6	0	0
T13	1652	13	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	592044	0	0
T1	55080	202	0	0
T2	9376	151	0	0
T3	286084	18	0	0
T7	247856	2147	0	0
T8	12568	0	0	0
T9	5367	92	0	0
T10	333296	4298	0	0
T11	271257	10	0	0
T12	2180	6	0	0
T13	1652	13	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	220670	0	0
T1	55080	139	0	0
T2	9376	138	0	0
T3	286084	10	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	88	0	0
T10	333296	209	0	0
T11	271257	10	0	0
T12	2180	6	0	0
T13	1652	13	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	223841	0	0
GntImpliesValid_A	405947867	223841	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	223841	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2951839	0	0
ReadyAndValidImplyGrant_A	405947867	223841	0	0
ReqAndReadyImplyGrant_A	405947867	223841	0	0
ReqImpliesValid_A	405947867	603872	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	223841	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223841	0	0
T1	55080	157	0	0
T2	9376	161	0	0
T3	286084	18	0	0
T7	247856	198	0	0
T8	12568	0	0	0
T9	5367	70	0	0
T10	333296	213	0	0
T11	271257	11	0	0
T12	2180	8	0	0
T13	1652	14	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223841	0	0
T1	55080	157	0	0
T2	9376	161	0	0
T3	286084	18	0	0
T7	247856	198	0	0
T8	12568	0	0	0
T9	5367	70	0	0
T10	333296	213	0	0
T11	271257	11	0	0
T12	2180	8	0	0
T13	1652	14	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223841	0	0
T1	55080	157	0	0
T2	9376	161	0	0
T3	286084	18	0	0
T7	247856	198	0	0
T8	12568	0	0	0
T9	5367	70	0	0
T10	333296	213	0	0
T11	271257	11	0	0
T12	2180	8	0	0
T13	1652	14	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2951839	0	0
T1	55080	1193	0	0
T2	9376	155	0	0
T3	286084	70	0	0
T7	247856	63197	0	0
T8	12568	1	0	0
T9	5367	70	0	0
T10	333296	71233	0	0
T11	271257	39	0	0
T12	2180	9	0	0
T13	1652	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223841	0	0
T1	55080	157	0	0
T2	9376	161	0	0
T3	286084	18	0	0
T7	247856	198	0	0
T8	12568	0	0	0
T9	5367	70	0	0
T10	333296	213	0	0
T11	271257	11	0	0
T12	2180	8	0	0
T13	1652	14	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223841	0	0
T1	55080	157	0	0
T2	9376	161	0	0
T3	286084	18	0	0
T7	247856	198	0	0
T8	12568	0	0	0
T9	5367	70	0	0
T10	333296	213	0	0
T11	271257	11	0	0
T12	2180	8	0	0
T13	1652	14	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	603872	0	0
T1	55080	197	0	0
T2	9376	168	0	0
T3	286084	22	0	0
T7	247856	5842	0	0
T8	12568	0	0	0
T9	5367	71	0	0
T10	333296	6355	0	0
T11	271257	11	0	0
T12	2180	8	0	0
T13	1652	14	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223841	0	0
T1	55080	157	0	0
T2	9376	161	0	0
T3	286084	18	0	0
T7	247856	198	0	0
T8	12568	0	0	0
T9	5367	70	0	0
T10	333296	213	0	0
T11	271257	11	0	0
T12	2180	8	0	0
T13	1652	14	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	223676	0	0
GntImpliesValid_A	405947867	223676	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	223676	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2896298	0	0
ReadyAndValidImplyGrant_A	405947867	223676	0	0
ReqAndReadyImplyGrant_A	405947867	223676	0	0
ReqImpliesValid_A	405947867	536391	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	223676	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223676	0	0
T1	55080	174	0	0
T2	9376	133	0	0
T3	286084	9	0	0
T7	247856	194	0	0
T8	12568	0	0	0
T9	5367	73	0	0
T10	333296	203	0	0
T11	271257	12	0	0
T12	2180	4	0	0
T13	1652	6	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223676	0	0
T1	55080	174	0	0
T2	9376	133	0	0
T3	286084	9	0	0
T7	247856	194	0	0
T8	12568	0	0	0
T9	5367	73	0	0
T10	333296	203	0	0
T11	271257	12	0	0
T12	2180	4	0	0
T13	1652	6	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223676	0	0
T1	55080	174	0	0
T2	9376	133	0	0
T3	286084	9	0	0
T7	247856	194	0	0
T8	12568	0	0	0
T9	5367	73	0	0
T10	333296	203	0	0
T11	271257	12	0	0
T12	2180	4	0	0
T13	1652	6	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2896298	0	0
T1	55080	1218	0	0
T2	9376	127	0	0
T3	286084	35	0	0
T7	247856	64205	0	0
T8	12568	1	0	0
T9	5367	65	0	0
T10	333296	69300	0	0
T11	271257	52	0	0
T12	2180	5	0	0
T13	1652	7	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223676	0	0
T1	55080	174	0	0
T2	9376	133	0	0
T3	286084	9	0	0
T7	247856	194	0	0
T8	12568	0	0	0
T9	5367	73	0	0
T10	333296	203	0	0
T11	271257	12	0	0
T12	2180	4	0	0
T13	1652	6	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223676	0	0
T1	55080	174	0	0
T2	9376	133	0	0
T3	286084	9	0	0
T7	247856	194	0	0
T8	12568	0	0	0
T9	5367	73	0	0
T10	333296	203	0	0
T11	271257	12	0	0
T12	2180	4	0	0
T13	1652	6	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	536391	0	0
T1	55080	273	0	0
T2	9376	140	0	0
T3	286084	9	0	0
T7	247856	2832	0	0
T8	12568	0	0	0
T9	5367	82	0	0
T10	333296	3426	0	0
T11	271257	15	0	0
T12	2180	4	0	0
T13	1652	6	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	223676	0	0
T1	55080	174	0	0
T2	9376	133	0	0
T3	286084	9	0	0
T7	247856	194	0	0
T8	12568	0	0	0
T9	5367	73	0	0
T10	333296	203	0	0
T11	271257	12	0	0
T12	2180	4	0	0
T13	1652	6	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	218162	0	0
GntImpliesValid_A	405947867	218162	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	218162	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2868697	0	0
ReadyAndValidImplyGrant_A	405947867	218162	0	0
ReqAndReadyImplyGrant_A	405947867	218162	0	0
ReqImpliesValid_A	405947867	524624	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	218162	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218162	0	0
T1	55080	164	0	0
T2	9376	130	0	0
T3	286084	11	0	0
T7	247856	182	0	0
T8	12568	0	0	0
T9	5367	81	0	0
T10	333296	194	0	0
T11	271257	10	0	0
T12	2180	9	0	0
T13	1652	8	0	0
T14	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218162	0	0
T1	55080	164	0	0
T2	9376	130	0	0
T3	286084	11	0	0
T7	247856	182	0	0
T8	12568	0	0	0
T9	5367	81	0	0
T10	333296	194	0	0
T11	271257	10	0	0
T12	2180	9	0	0
T13	1652	8	0	0
T14	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218162	0	0
T1	55080	164	0	0
T2	9376	130	0	0
T3	286084	11	0	0
T7	247856	182	0	0
T8	12568	0	0	0
T9	5367	81	0	0
T10	333296	194	0	0
T11	271257	10	0	0
T12	2180	9	0	0
T13	1652	8	0	0
T14	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2868697	0	0
T1	55080	1210	0	0
T2	9376	127	0	0
T3	286084	67	0	0
T7	247856	62406	0	0
T8	12568	1	0	0
T9	5367	76	0	0
T10	333296	58527	0	0
T11	271257	53	0	0
T12	2180	9	0	0
T13	1652	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218162	0	0
T1	55080	164	0	0
T2	9376	130	0	0
T3	286084	11	0	0
T7	247856	182	0	0
T8	12568	0	0	0
T9	5367	81	0	0
T10	333296	194	0	0
T11	271257	10	0	0
T12	2180	9	0	0
T13	1652	8	0	0
T14	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218162	0	0
T1	55080	164	0	0
T2	9376	130	0	0
T3	286084	11	0	0
T7	247856	182	0	0
T8	12568	0	0	0
T9	5367	81	0	0
T10	333296	194	0	0
T11	271257	10	0	0
T12	2180	9	0	0
T13	1652	8	0	0
T14	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	524624	0	0
T1	55080	197	0	0
T2	9376	134	0	0
T3	286084	12	0	0
T7	247856	3582	0	0
T8	12568	0	0	0
T9	5367	87	0	0
T10	333296	3391	0	0
T11	271257	14	0	0
T12	2180	10	0	0
T13	1652	8	0	0
T14	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	218162	0	0
T1	55080	164	0	0
T2	9376	130	0	0
T3	286084	11	0	0
T7	247856	182	0	0
T8	12568	0	0	0
T9	5367	81	0	0
T10	333296	194	0	0
T11	271257	10	0	0
T12	2180	9	0	0
T13	1652	8	0	0
T14	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	208309	0	0
GntImpliesValid_A	405947867	208309	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	208309	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2887387	0	0
ReadyAndValidImplyGrant_A	405947867	208309	0	0
ReqAndReadyImplyGrant_A	405947867	208309	0	0
ReqImpliesValid_A	405947867	511515	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	208309	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	208309	0	0
T1	55080	150	0	0
T2	9376	132	0	0
T3	286084	18	0	0
T7	247856	180	0	0
T8	12568	532	0	0
T9	5367	70	0	0
T10	333296	191	0	0
T11	271257	17	0	0
T12	2180	11	0	0
T13	1652	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	208309	0	0
T1	55080	150	0	0
T2	9376	132	0	0
T3	286084	18	0	0
T7	247856	180	0	0
T8	12568	532	0	0
T9	5367	70	0	0
T10	333296	191	0	0
T11	271257	17	0	0
T12	2180	11	0	0
T13	1652	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	208309	0	0
T1	55080	150	0	0
T2	9376	132	0	0
T3	286084	18	0	0
T7	247856	180	0	0
T8	12568	532	0	0
T9	5367	70	0	0
T10	333296	191	0	0
T11	271257	17	0	0
T12	2180	11	0	0
T13	1652	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2887387	0	0
T1	55080	985	0	0
T2	9376	126	0	0
T3	286084	57	0	0
T7	247856	61747	0	0
T8	12568	2	0	0
T9	5367	68	0	0
T10	333296	52786	0	0
T11	271257	57	0	0
T12	2180	12	0	0
T13	1652	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	208309	0	0
T1	55080	150	0	0
T2	9376	132	0	0
T3	286084	18	0	0
T7	247856	180	0	0
T8	12568	532	0	0
T9	5367	70	0	0
T10	333296	191	0	0
T11	271257	17	0	0
T12	2180	11	0	0
T13	1652	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	208309	0	0
T1	55080	150	0	0
T2	9376	132	0	0
T3	286084	18	0	0
T7	247856	180	0	0
T8	12568	532	0	0
T9	5367	70	0	0
T10	333296	191	0	0
T11	271257	17	0	0
T12	2180	11	0	0
T13	1652	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	511515	0	0
T1	55080	332	0	0
T2	9376	139	0	0
T3	286084	20	0	0
T7	247856	2119	0	0
T8	12568	1063	0	0
T9	5367	73	0	0
T10	333296	3214	0	0
T11	271257	17	0	0
T12	2180	11	0	0
T13	1652	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	208309	0	0
T1	55080	150	0	0
T2	9376	132	0	0
T3	286084	18	0	0
T7	247856	180	0	0
T8	12568	532	0	0
T9	5367	70	0	0
T10	333296	191	0	0
T11	271257	17	0	0
T12	2180	11	0	0
T13	1652	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	226893	0	0
GntImpliesValid_A	405947867	226893	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	226893	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2960056	0	0
ReadyAndValidImplyGrant_A	405947867	226893	0	0
ReqAndReadyImplyGrant_A	405947867	226893	0	0
ReqImpliesValid_A	405947867	600607	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	226893	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226893	0	0
T1	55080	188	0	0
T2	9376	125	0	0
T3	286084	13	0	0
T7	247856	186	0	0
T8	12568	0	0	0
T9	5367	84	0	0
T10	333296	226	0	0
T11	271257	10	0	0
T12	2180	11	0	0
T13	1652	13	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226893	0	0
T1	55080	188	0	0
T2	9376	125	0	0
T3	286084	13	0	0
T7	247856	186	0	0
T8	12568	0	0	0
T9	5367	84	0	0
T10	333296	226	0	0
T11	271257	10	0	0
T12	2180	11	0	0
T13	1652	13	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226893	0	0
T1	55080	188	0	0
T2	9376	125	0	0
T3	286084	13	0	0
T7	247856	186	0	0
T8	12568	0	0	0
T9	5367	84	0	0
T10	333296	226	0	0
T11	271257	10	0	0
T12	2180	11	0	0
T13	1652	13	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2960056	0	0
T1	55080	1429	0	0
T2	9376	118	0	0
T3	286084	63	0	0
T7	247856	63953	0	0
T8	12568	1	0	0
T9	5367	78	0	0
T10	333296	75502	0	0
T11	271257	53	0	0
T12	2180	12	0	0
T13	1652	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226893	0	0
T1	55080	188	0	0
T2	9376	125	0	0
T3	286084	13	0	0
T7	247856	186	0	0
T8	12568	0	0	0
T9	5367	84	0	0
T10	333296	226	0	0
T11	271257	10	0	0
T12	2180	11	0	0
T13	1652	13	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226893	0	0
T1	55080	188	0	0
T2	9376	125	0	0
T3	286084	13	0	0
T7	247856	186	0	0
T8	12568	0	0	0
T9	5367	84	0	0
T10	333296	226	0	0
T11	271257	10	0	0
T12	2180	11	0	0
T13	1652	13	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	600607	0	0
T1	55080	262	0	0
T2	9376	133	0	0
T3	286084	20	0	0
T7	247856	4034	0	0
T8	12568	0	0	0
T9	5367	91	0	0
T10	333296	2023	0	0
T11	271257	10	0	0
T12	2180	11	0	0
T13	1652	14	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	226893	0	0
T1	55080	188	0	0
T2	9376	125	0	0
T3	286084	13	0	0
T7	247856	186	0	0
T8	12568	0	0	0
T9	5367	84	0	0
T10	333296	226	0	0
T11	271257	10	0	0
T12	2180	11	0	0
T13	1652	13	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	236458	0	0
GntImpliesValid_A	405947867	236458	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	236458	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2977850	0	0
ReadyAndValidImplyGrant_A	405947867	236458	0	0
ReqAndReadyImplyGrant_A	405947867	236458	0	0
ReqImpliesValid_A	405947867	562953	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	236458	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	236458	0	0
T1	55080	134	0	0
T2	9376	116	0	0
T3	286084	15	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	89	0	0
T10	333296	232	0	0
T11	271257	15	0	0
T12	2180	16	0	0
T13	1652	11	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	236458	0	0
T1	55080	134	0	0
T2	9376	116	0	0
T3	286084	15	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	89	0	0
T10	333296	232	0	0
T11	271257	15	0	0
T12	2180	16	0	0
T13	1652	11	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	236458	0	0
T1	55080	134	0	0
T2	9376	116	0	0
T3	286084	15	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	89	0	0
T10	333296	232	0	0
T11	271257	15	0	0
T12	2180	16	0	0
T13	1652	11	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2977850	0	0
T1	55080	930	0	0
T2	9376	110	0	0
T3	286084	51	0	0
T7	247856	60964	0	0
T8	12568	1	0	0
T9	5367	87	0	0
T10	333296	78043	0	0
T11	271257	60	0	0
T12	2180	16	0	0
T13	1652	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	236458	0	0
T1	55080	134	0	0
T2	9376	116	0	0
T3	286084	15	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	89	0	0
T10	333296	232	0	0
T11	271257	15	0	0
T12	2180	16	0	0
T13	1652	11	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	236458	0	0
T1	55080	134	0	0
T2	9376	116	0	0
T3	286084	15	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	89	0	0
T10	333296	232	0	0
T11	271257	15	0	0
T12	2180	16	0	0
T13	1652	11	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	562953	0	0
T1	55080	184	0	0
T2	9376	123	0	0
T3	286084	18	0	0
T7	247856	3109	0	0
T8	12568	0	0	0
T9	5367	92	0	0
T10	333296	2953	0	0
T11	271257	19	0	0
T12	2180	17	0	0
T13	1652	11	0	0
T14	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	236458	0	0
T1	55080	134	0	0
T2	9376	116	0	0
T3	286084	15	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	89	0	0
T10	333296	232	0	0
T11	271257	15	0	0
T12	2180	16	0	0
T13	1652	11	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	214914	0	0
GntImpliesValid_A	405947867	214914	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	214914	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2850631	0	0
ReadyAndValidImplyGrant_A	405947867	214914	0	0
ReqAndReadyImplyGrant_A	405947867	214914	0	0
ReqImpliesValid_A	405947867	521782	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	214914	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	214914	0	0
T1	55080	152	0	0
T2	9376	130	0	0
T3	286084	14	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	78	0	0
T10	333296	206	0	0
T11	271257	9	0	0
T12	2180	5	0	0
T13	1652	11	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	214914	0	0
T1	55080	152	0	0
T2	9376	130	0	0
T3	286084	14	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	78	0	0
T10	333296	206	0	0
T11	271257	9	0	0
T12	2180	5	0	0
T13	1652	11	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	214914	0	0
T1	55080	152	0	0
T2	9376	130	0	0
T3	286084	14	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	78	0	0
T10	333296	206	0	0
T11	271257	9	0	0
T12	2180	5	0	0
T13	1652	11	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2850631	0	0
T1	55080	1102	0	0
T2	9376	123	0	0
T3	286084	60	0	0
T7	247856	50369	0	0
T8	12568	1	0	0
T9	5367	74	0	0
T10	333296	75712	0	0
T11	271257	41	0	0
T12	2180	6	0	0
T13	1652	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	214914	0	0
T1	55080	152	0	0
T2	9376	130	0	0
T3	286084	14	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	78	0	0
T10	333296	206	0	0
T11	271257	9	0	0
T12	2180	5	0	0
T13	1652	11	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	214914	0	0
T1	55080	152	0	0
T2	9376	130	0	0
T3	286084	14	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	78	0	0
T10	333296	206	0	0
T11	271257	9	0	0
T12	2180	5	0	0
T13	1652	11	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	521782	0	0
T1	55080	192	0	0
T2	9376	138	0	0
T3	286084	14	0	0
T7	247856	1652	0	0
T8	12568	0	0	0
T9	5367	83	0	0
T10	333296	6741	0	0
T11	271257	9	0	0
T12	2180	5	0	0
T13	1652	11	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	214914	0	0
T1	55080	152	0	0
T2	9376	130	0	0
T3	286084	14	0	0
T7	247856	171	0	0
T8	12568	0	0	0
T9	5367	78	0	0
T10	333296	206	0	0
T11	271257	9	0	0
T12	2180	5	0	0
T13	1652	11	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	222543	0	0
GntImpliesValid_A	405947867	222543	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	222543	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2945529	0	0
ReadyAndValidImplyGrant_A	405947867	222543	0	0
ReqAndReadyImplyGrant_A	405947867	222543	0	0
ReqImpliesValid_A	405947867	553250	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	222543	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	222543	0	0
T1	55080	137	0	0
T2	9376	121	0	0
T3	286084	16	0	0
T7	247856	205	0	0
T8	12568	0	0	0
T9	5367	67	0	0
T10	333296	205	0	0
T11	271257	16	0	0
T12	2180	14	0	0
T13	1652	14	0	0
T14	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	222543	0	0
T1	55080	137	0	0
T2	9376	121	0	0
T3	286084	16	0	0
T7	247856	205	0	0
T8	12568	0	0	0
T9	5367	67	0	0
T10	333296	205	0	0
T11	271257	16	0	0
T12	2180	14	0	0
T13	1652	14	0	0
T14	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	222543	0	0
T1	55080	137	0	0
T2	9376	121	0	0
T3	286084	16	0	0
T7	247856	205	0	0
T8	12568	0	0	0
T9	5367	67	0	0
T10	333296	205	0	0
T11	271257	16	0	0
T12	2180	14	0	0
T13	1652	14	0	0
T14	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2945529	0	0
T1	55080	1025	0	0
T2	9376	118	0	0
T3	286084	68	0	0
T7	247856	65290	0	0
T8	12568	1	0	0
T9	5367	65	0	0
T10	333296	68556	0	0
T11	271257	66	0	0
T12	2180	13	0	0
T13	1652	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	222543	0	0
T1	55080	137	0	0
T2	9376	121	0	0
T3	286084	16	0	0
T7	247856	205	0	0
T8	12568	0	0	0
T9	5367	67	0	0
T10	333296	205	0	0
T11	271257	16	0	0
T12	2180	14	0	0
T13	1652	14	0	0
T14	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	222543	0	0
T1	55080	137	0	0
T2	9376	121	0	0
T3	286084	16	0	0
T7	247856	205	0	0
T8	12568	0	0	0
T9	5367	67	0	0
T10	333296	205	0	0
T11	271257	16	0	0
T12	2180	14	0	0
T13	1652	14	0	0
T14	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	553250	0	0
T1	55080	168	0	0
T2	9376	125	0	0
T3	286084	17	0	0
T7	247856	3745	0	0
T8	12568	0	0	0
T9	5367	70	0	0
T10	333296	2562	0	0
T11	271257	18	0	0
T12	2180	16	0	0
T13	1652	15	0	0
T14	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	222543	0	0
T1	55080	137	0	0
T2	9376	121	0	0
T3	286084	16	0	0
T7	247856	205	0	0
T8	12568	0	0	0
T9	5367	67	0	0
T10	333296	205	0	0
T11	271257	16	0	0
T12	2180	14	0	0
T13	1652	14	0	0
T14	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	219249	0	0
GntImpliesValid_A	405947867	219249	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	219249	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2891861	0	0
ReadyAndValidImplyGrant_A	405947867	219249	0	0
ReqAndReadyImplyGrant_A	405947867	219249	0	0
ReqImpliesValid_A	405947867	552843	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	219249	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	219249	0	0
T1	55080	140	0	0
T2	9376	121	0	0
T3	286084	17	0	0
T7	247856	187	0	0
T8	12568	469	0	0
T9	5367	74	0	0
T10	333296	210	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	219249	0	0
T1	55080	140	0	0
T2	9376	121	0	0
T3	286084	17	0	0
T7	247856	187	0	0
T8	12568	469	0	0
T9	5367	74	0	0
T10	333296	210	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	219249	0	0
T1	55080	140	0	0
T2	9376	121	0	0
T3	286084	17	0	0
T7	247856	187	0	0
T8	12568	469	0	0
T9	5367	74	0	0
T10	333296	210	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2891861	0	0
T1	55080	996	0	0
T2	9376	119	0	0
T3	286084	59	0	0
T7	247856	61603	0	0
T8	12568	4	0	0
T9	5367	71	0	0
T10	333296	64317	0	0
T11	271257	73	0	0
T12	2180	8	0	0
T13	1652	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	219249	0	0
T1	55080	140	0	0
T2	9376	121	0	0
T3	286084	17	0	0
T7	247856	187	0	0
T8	12568	469	0	0
T9	5367	74	0	0
T10	333296	210	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	219249	0	0
T1	55080	140	0	0
T2	9376	121	0	0
T3	286084	17	0	0
T7	247856	187	0	0
T8	12568	469	0	0
T9	5367	74	0	0
T10	333296	210	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	552843	0	0
T1	55080	190	0	0
T2	9376	124	0	0
T3	286084	24	0	0
T7	247856	4255	0	0
T8	12568	935	0	0
T9	5367	78	0	0
T10	333296	5882	0	0
T11	271257	13	0	0
T12	2180	9	0	0
T13	1652	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	219249	0	0
T1	55080	140	0	0
T2	9376	121	0	0
T3	286084	17	0	0
T7	247856	187	0	0
T8	12568	469	0	0
T9	5367	74	0	0
T10	333296	210	0	0
T11	271257	13	0	0
T12	2180	8	0	0
T13	1652	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	228770	0	0
GntImpliesValid_A	405947867	228770	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	228770	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2905272	0	0
ReadyAndValidImplyGrant_A	405947867	228770	0	0
ReqAndReadyImplyGrant_A	405947867	228770	0	0
ReqImpliesValid_A	405947867	590985	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	228770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	228770	0	0
T1	55080	159	0	0
T2	9376	134	0	0
T3	286084	10	0	0
T7	247856	164	0	0
T8	12568	469	0	0
T9	5367	71	0	0
T10	333296	211	0	0
T11	271257	9	0	0
T12	2180	7	0	0
T13	1652	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	228770	0	0
T1	55080	159	0	0
T2	9376	134	0	0
T3	286084	10	0	0
T7	247856	164	0	0
T8	12568	469	0	0
T9	5367	71	0	0
T10	333296	211	0	0
T11	271257	9	0	0
T12	2180	7	0	0
T13	1652	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	228770	0	0
T1	55080	159	0	0
T2	9376	134	0	0
T3	286084	10	0	0
T7	247856	164	0	0
T8	12568	469	0	0
T9	5367	71	0	0
T10	333296	211	0	0
T11	271257	9	0	0
T12	2180	7	0	0
T13	1652	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2905272	0	0
T1	55080	991	0	0
T2	9376	125	0	0
T3	286084	49	0	0
T7	247856	52899	0	0
T8	12568	92	0	0
T9	5367	66	0	0
T10	333296	72447	0	0
T11	271257	50	0	0
T12	2180	8	0	0
T13	1652	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	228770	0	0
T1	55080	159	0	0
T2	9376	134	0	0
T3	286084	10	0	0
T7	247856	164	0	0
T8	12568	469	0	0
T9	5367	71	0	0
T10	333296	211	0	0
T11	271257	9	0	0
T12	2180	7	0	0
T13	1652	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	228770	0	0
T1	55080	159	0	0
T2	9376	134	0	0
T3	286084	10	0	0
T7	247856	164	0	0
T8	12568	469	0	0
T9	5367	71	0	0
T10	333296	211	0	0
T11	271257	9	0	0
T12	2180	7	0	0
T13	1652	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	590985	0	0
T1	55080	299	0	0
T2	9376	144	0	0
T3	286084	14	0	0
T7	247856	3952	0	0
T8	12568	847	0	0
T9	5367	77	0	0
T10	333296	4079	0	0
T11	271257	9	0	0
T12	2180	7	0	0
T13	1652	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	228770	0	0
T1	55080	159	0	0
T2	9376	134	0	0
T3	286084	10	0	0
T7	247856	164	0	0
T8	12568	469	0	0
T9	5367	71	0	0
T10	333296	211	0	0
T11	271257	9	0	0
T12	2180	7	0	0
T13	1652	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	232798	0	0
GntImpliesValid_A	405947867	232798	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	232798	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	2909694	0	0
ReadyAndValidImplyGrant_A	405947867	232798	0	0
ReqAndReadyImplyGrant_A	405947867	232798	0	0
ReqImpliesValid_A	405947867	586816	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	0	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	232798	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	232798	0	0
T1	55080	141	0	0
T2	9376	121	0	0
T3	286084	11	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	207	0	0
T11	271257	20	0	0
T12	2180	7	0	0
T13	1652	11	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	232798	0	0
T1	55080	141	0	0
T2	9376	121	0	0
T3	286084	11	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	207	0	0
T11	271257	20	0	0
T12	2180	7	0	0
T13	1652	11	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	232798	0	0
T1	55080	141	0	0
T2	9376	121	0	0
T3	286084	11	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	207	0	0
T11	271257	20	0	0
T12	2180	7	0	0
T13	1652	11	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2909694	0	0
T1	55080	939	0	0
T2	9376	119	0	0
T3	286084	36	0	0
T7	247856	55983	0	0
T8	12568	1	0	0
T9	5367	72	0	0
T10	333296	70535	0	0
T11	271257	85	0	0
T12	2180	8	0	0
T13	1652	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	232798	0	0
T1	55080	141	0	0
T2	9376	121	0	0
T3	286084	11	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	207	0	0
T11	271257	20	0	0
T12	2180	7	0	0
T13	1652	11	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	232798	0	0
T1	55080	141	0	0
T2	9376	121	0	0
T3	286084	11	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	207	0	0
T11	271257	20	0	0
T12	2180	7	0	0
T13	1652	11	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	586816	0	0
T1	55080	212	0	0
T2	9376	124	0	0
T3	286084	30	0	0
T7	247856	7962	0	0
T8	12568	0	0	0
T9	5367	81	0	0
T10	333296	4362	0	0
T11	271257	37	0	0
T12	2180	7	0	0
T13	1652	12	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	232798	0	0
T1	55080	141	0	0
T2	9376	121	0	0
T3	286084	11	0	0
T7	247856	192	0	0
T8	12568	0	0	0
T9	5367	76	0	0
T10	333296	207	0	0
T11	271257	20	0	0
T12	2180	7	0	0
T13	1652	11	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	900526	0	0
GntImpliesValid_A	405947867	900526	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	900526	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	10971988	0	0
ReadyAndValidImplyGrant_A	405947867	900526	0	0
ReqAndReadyImplyGrant_A	405947867	900526	0	0
ReqImpliesValid_A	405947867	2300658	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	21631	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	900526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	900526	0	0
T1	55080	604	0	0
T2	9376	508	0	0
T3	286084	36	0	0
T7	247856	709	0	0
T8	12568	377	0	0
T9	5367	340	0	0
T10	333296	841	0	0
T11	271257	49	0	0
T12	2180	42	0	0
T13	1652	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	900526	0	0
T1	55080	604	0	0
T2	9376	508	0	0
T3	286084	36	0	0
T7	247856	709	0	0
T8	12568	377	0	0
T9	5367	340	0	0
T10	333296	841	0	0
T11	271257	49	0	0
T12	2180	42	0	0
T13	1652	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	900526	0	0
T1	55080	604	0	0
T2	9376	508	0	0
T3	286084	36	0	0
T7	247856	709	0	0
T8	12568	377	0	0
T9	5367	340	0	0
T10	333296	841	0	0
T11	271257	49	0	0
T12	2180	42	0	0
T13	1652	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	10971988	0	0
T1	55080	3890	0	0
T2	9376	1	0	0
T3	286084	111	0	0
T7	247856	191626	0	0
T8	12568	1	0	0
T9	5367	1	0	0
T10	333296	254680	0	0
T11	271257	168	0	0
T12	2180	1	0	0
T13	1652	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	900526	0	0
T1	55080	604	0	0
T2	9376	508	0	0
T3	286084	36	0	0
T7	247856	709	0	0
T8	12568	377	0	0
T9	5367	340	0	0
T10	333296	841	0	0
T11	271257	49	0	0
T12	2180	42	0	0
T13	1652	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	900526	0	0
T1	55080	604	0	0
T2	9376	508	0	0
T3	286084	36	0	0
T7	247856	709	0	0
T8	12568	377	0	0
T9	5367	340	0	0
T10	333296	841	0	0
T11	271257	49	0	0
T12	2180	42	0	0
T13	1652	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	2300658	0	0
T1	55080	1059	0	0
T2	9376	508	0	0
T3	286084	59	0	0
T7	247856	21412	0	0
T8	12568	377	0	0
T9	5367	340	0	0
T10	333296	27543	0	0
T11	271257	54	0	0
T12	2180	42	0	0
T13	1652	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	21631	0	900
T2	9376	8	0	1
T3	286084	0	0	1
T4	0	11	0	0
T5	0	1	0	0
T7	247856	0	0	1
T8	12568	0	0	1
T9	5367	3	0	1
T10	333296	1	0	1
T11	271257	0	0	1
T12	2180	0	0	1
T13	1652	0	0	1
T14	112488	0	0	1
T19	0	15	0	0
T20	0	3	0	0
T21	0	77	0	0
T22	0	1	0	0
T23	0	16	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	900526	0	0
T1	55080	604	0	0
T2	9376	508	0	0
T3	286084	36	0	0
T7	247856	709	0	0
T8	12568	377	0	0
T9	5367	340	0	0
T10	333296	841	0	0
T11	271257	49	0	0
T12	2180	42	0	0
T13	1652	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947867	405816881	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947867	882888	0	0
GntImpliesValid_A	405947867	882888	0	0
GrantKnown_A	405947867	405816881	0	0
IdxKnown_A	405947867	405816881	0	0
IndexIsCorrect_A	405947867	882888	0	0
LockArbDecision_A	405947867	0	0	0
NoReadyValidNoGrant_A	405947867	339691166	0	0
ReadyAndValidImplyGrant_A	405947867	882888	0	0
ReqAndReadyImplyGrant_A	405947867	882888	0	0
ReqImpliesValid_A	405947867	12859111	0	0
ReqStaysHighUntilGranted0_M	405947867	0	0	0
RoundRobin_A	405947867	24045	0	900
ValidKnown_A	405947867	405816881	0	0
gen_data_port_assertion.DataFlow_A	405947867	882888	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	882888	0	0
T1	55080	611	0	0
T2	9376	515	0	0
T3	286084	44	0	0
T7	247856	736	0	0
T8	12568	386	0	0
T9	5367	330	0	0
T10	333296	800	0	0
T11	271257	40	0	0
T12	2180	49	0	0
T13	1652	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	882888	0	0
T1	55080	611	0	0
T2	9376	515	0	0
T3	286084	44	0	0
T7	247856	736	0	0
T8	12568	386	0	0
T9	5367	330	0	0
T10	333296	800	0	0
T11	271257	40	0	0
T12	2180	49	0	0
T13	1652	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	882888	0	0
T1	55080	611	0	0
T2	9376	515	0	0
T3	286084	44	0	0
T7	247856	736	0	0
T8	12568	386	0	0
T9	5367	330	0	0
T10	333296	800	0	0
T11	271257	40	0	0
T12	2180	49	0	0
T13	1652	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	339691166	0	0
T1	55080	45614	0	0
T2	9376	1	0	0
T3	286084	238178	0	0
T7	247856	223206	0	0
T8	12568	1	0	0
T9	5367	1	0	0
T10	333296	303710	0	0
T11	271257	225905	0	0
T12	2180	1	0	0
T13	1652	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	882888	0	0
T1	55080	611	0	0
T2	9376	515	0	0
T3	286084	44	0	0
T7	247856	736	0	0
T8	12568	386	0	0
T9	5367	330	0	0
T10	333296	800	0	0
T11	271257	40	0	0
T12	2180	49	0	0
T13	1652	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	882888	0	0
T1	55080	611	0	0
T2	9376	515	0	0
T3	286084	44	0	0
T7	247856	736	0	0
T8	12568	386	0	0
T9	5367	330	0	0
T10	333296	800	0	0
T11	271257	40	0	0
T12	2180	49	0	0
T13	1652	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	12859111	0	0
T1	55080	4975	0	0
T2	9376	515	0	0
T3	286084	169	0	0
T7	247856	242177	0	0
T8	12568	386	0	0
T9	5367	330	0	0
T10	333296	290071	0	0
T11	271257	183	0	0
T12	2180	49	0	0
T13	1652	36	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	24045	0	900
T2	9376	5	0	1
T3	286084	0	0	1
T4	0	2	0	0
T7	247856	0	0	1
T8	12568	0	0	1
T9	5367	2	0	1
T10	333296	0	0	1
T11	271257	0	0	1
T12	2180	0	0	1
T13	1652	0	0	1
T14	112488	0	0	1
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	25	0	0
T19	0	23	0	0
T20	0	3	0	0
T21	0	330	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	405816881	0	0
T1	55080	55019	0	0
T2	9376	9284	0	0
T3	286084	286051	0	0
T7	247856	247851	0	0
T8	12568	12511	0	0
T9	5367	5330	0	0
T10	333296	333293	0	0
T11	271257	271240	0	0
T12	2180	2110	0	0
T13	1652	1630	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947867	882888	0	0
T1	55080	611	0	0
T2	9376	515	0	0
T3	286084	44	0	0
T7	247856	736	0	0
T8	12568	386	0	0
T9	5367	330	0	0
T10	333296	800	0	0
T11	271257	40	0	0
T12	2180	49	0	0
T13	1652	36	0	0